Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	358811	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4434087	1		T1	297		T2	219		T3	14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1179158	1		T1	18		T2	45		T3	1
values[0x0]	1695682	1		T1	194		T2	138		T3	11
values[0x1]	1918058	1		T1	165		T2	141		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	159382	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4633516	1		T1	320		T2	239		T3	15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17069	1		T1	2		T2	9		T4	653
valid_sources[0x01]	18264	1		T1	1		T4	655		T5	132
valid_sources[0x02]	18056	1		T4	611		T5	134		T9	202
valid_sources[0x03]	19030	1		T1	3		T2	13		T4	636
valid_sources[0x04]	20104	1		T4	633		T5	125		T9	186
valid_sources[0x05]	18901	1		T4	612		T5	95		T9	187
valid_sources[0x06]	18124	1		T4	609		T5	125		T9	199
valid_sources[0x07]	19370	1		T1	1		T4	655		T5	127
valid_sources[0x08]	19100	1		T1	4		T4	638		T5	111
valid_sources[0x09]	18835	1		T1	1		T2	2		T4	619
valid_sources[0x0a]	19412	1		T1	2		T4	671		T5	126
valid_sources[0x0b]	19297	1		T1	1		T2	2		T3	22
valid_sources[0x0c]	19113	1		T1	1		T4	679		T5	110
valid_sources[0x0d]	19146	1		T1	2		T4	632		T5	128
valid_sources[0x0e]	18987	1		T1	1		T2	4		T4	585
valid_sources[0x0f]	19639	1		T1	2		T2	2		T4	585
valid_sources[0x10]	18585	1		T1	1		T4	605		T5	143
valid_sources[0x11]	20170	1		T1	4		T4	606		T5	124
valid_sources[0x12]	17682	1		T4	675		T5	158		T9	196
valid_sources[0x13]	18793	1		T1	1		T4	625		T5	125
valid_sources[0x14]	18450	1		T4	580		T5	159		T9	177
valid_sources[0x15]	18534	1		T1	1		T2	3		T4	591
valid_sources[0x16]	17654	1		T4	611		T5	135		T9	203
valid_sources[0x17]	17651	1		T1	2		T4	630		T5	114
valid_sources[0x18]	17890	1		T1	2		T4	628		T5	126
valid_sources[0x19]	19105	1		T1	2		T2	2		T4	640
valid_sources[0x1a]	18463	1		T1	2		T2	2		T4	619
valid_sources[0x1b]	19261	1		T1	1		T4	613		T5	109
valid_sources[0x1c]	19055	1		T4	572		T5	124		T9	200
valid_sources[0x1d]	18910	1		T1	2		T4	612		T5	115
valid_sources[0x1e]	18959	1		T1	1		T4	592		T5	147
valid_sources[0x1f]	19829	1		T1	1		T2	1		T4	617
valid_sources[0x20]	19956	1		T1	6		T2	8		T4	612
valid_sources[0x21]	19150	1		T1	1		T4	636		T5	114
valid_sources[0x22]	18653	1		T2	2		T4	654		T5	135
valid_sources[0x23]	20190	1		T1	2		T4	624		T5	131
valid_sources[0x24]	17021	1		T4	602		T5	120		T9	218
valid_sources[0x25]	18620	1		T1	1		T2	7		T4	643
valid_sources[0x26]	18490	1		T1	3		T4	619		T5	82
valid_sources[0x27]	18597	1		T1	2		T4	596		T5	107
valid_sources[0x28]	17417	1		T4	609		T5	107		T9	222
valid_sources[0x29]	20168	1		T1	2		T2	1		T4	647
valid_sources[0x2a]	17706	1		T1	2		T2	9		T4	671
valid_sources[0x2b]	17441	1		T1	1		T4	644		T5	160
valid_sources[0x2c]	18325	1		T1	3		T2	3		T4	609
valid_sources[0x2d]	18014	1		T4	590		T5	138		T9	199
valid_sources[0x2e]	16516	1		T1	2		T4	590		T5	95
valid_sources[0x2f]	18723	1		T1	3		T4	637		T5	123
valid_sources[0x30]	19365	1		T4	637		T5	154		T9	207
valid_sources[0x31]	19882	1		T1	3		T4	675		T5	127
valid_sources[0x32]	20235	1		T1	2		T4	656		T5	104
valid_sources[0x33]	19283	1		T4	609		T5	101		T9	199
valid_sources[0x34]	18438	1		T1	2		T4	573		T5	118
valid_sources[0x35]	19064	1		T1	2		T4	641		T5	168
valid_sources[0x36]	17219	1		T1	4		T4	566		T5	132
valid_sources[0x37]	18658	1		T1	1		T4	614		T5	114
valid_sources[0x38]	19381	1		T1	1		T4	653		T5	156
valid_sources[0x39]	17955	1		T1	3		T4	585		T5	109
valid_sources[0x3a]	18915	1		T1	2		T4	628		T5	129
valid_sources[0x3b]	18311	1		T1	1		T4	628		T5	137
valid_sources[0x3c]	20615	1		T1	3		T2	10		T4	574
valid_sources[0x3d]	18643	1		T1	4		T4	677		T5	127
valid_sources[0x3e]	18319	1		T1	1		T4	611		T5	105
valid_sources[0x3f]	18790	1		T1	3		T4	616		T5	120
valid_sources[0x40]	18757	1		T4	628		T5	113		T9	164
valid_sources[0x41]	19991	1		T1	2		T2	1		T4	636
valid_sources[0x42]	18407	1		T1	2		T4	600		T5	132
valid_sources[0x43]	19062	1		T1	4		T4	641		T5	115
valid_sources[0x44]	19321	1		T4	610		T5	111		T8	1
valid_sources[0x45]	18307	1		T1	1		T4	610		T5	101
valid_sources[0x46]	19874	1		T1	2		T2	2		T4	631
valid_sources[0x47]	19111	1		T1	1		T2	2		T4	607
valid_sources[0x48]	16702	1		T1	2		T4	619		T5	105
valid_sources[0x49]	18683	1		T1	1		T4	612		T5	148
valid_sources[0x4a]	19485	1		T2	2		T4	627		T5	127
valid_sources[0x4b]	17264	1		T1	3		T2	1		T4	643
valid_sources[0x4c]	18956	1		T1	1		T4	642		T5	148
valid_sources[0x4d]	18191	1		T4	582		T5	123		T9	213
valid_sources[0x4e]	18332	1		T1	1		T2	6		T4	597
valid_sources[0x4f]	18086	1		T4	552		T5	88		T9	206
valid_sources[0x50]	19459	1		T1	1		T4	623		T5	115
valid_sources[0x51]	18345	1		T4	622		T5	159		T9	207
valid_sources[0x52]	19319	1		T1	3		T4	582		T5	139
valid_sources[0x53]	17946	1		T4	677		T5	147		T7	6
valid_sources[0x54]	18336	1		T1	4		T4	676		T5	124
valid_sources[0x55]	18628	1		T1	1		T4	605		T5	95
valid_sources[0x56]	19102	1		T1	1		T4	608		T5	116
valid_sources[0x57]	18285	1		T1	1		T4	631		T5	147
valid_sources[0x58]	16990	1		T1	1		T2	2		T4	644
valid_sources[0x59]	20542	1		T1	1		T4	652		T5	160
valid_sources[0x5a]	18836	1		T2	5		T4	607		T5	131
valid_sources[0x5b]	19658	1		T1	1		T4	576		T5	109
valid_sources[0x5c]	16974	1		T1	1		T2	6		T4	631
valid_sources[0x5d]	18706	1		T1	1		T2	8		T4	634
valid_sources[0x5e]	19034	1		T1	1		T4	650		T5	160
valid_sources[0x5f]	18693	1		T1	2		T4	722		T5	120
valid_sources[0x60]	19139	1		T4	662		T5	136		T9	197
valid_sources[0x61]	17035	1		T1	2		T4	650		T5	117
valid_sources[0x62]	18557	1		T4	656		T5	148		T9	168
valid_sources[0x63]	17921	1		T1	3		T4	602		T5	141
valid_sources[0x64]	19818	1		T4	700		T5	137		T9	180
valid_sources[0x65]	18352	1		T1	2		T4	658		T5	101
valid_sources[0x66]	18713	1		T1	2		T4	632		T5	110
valid_sources[0x67]	17295	1		T1	1		T2	2		T4	633
valid_sources[0x68]	19664	1		T1	2		T4	600		T5	101
valid_sources[0x69]	17890	1		T1	1		T4	597		T5	84
valid_sources[0x6a]	19894	1		T4	648		T5	90		T9	180
valid_sources[0x6b]	17330	1		T1	2		T2	9		T4	649
valid_sources[0x6c]	18343	1		T1	1		T4	613		T5	118
valid_sources[0x6d]	19228	1		T1	3		T2	1		T4	641
valid_sources[0x6e]	18942	1		T1	3		T2	8		T4	634
valid_sources[0x6f]	19888	1		T1	1		T4	581		T5	117
valid_sources[0x70]	20198	1		T1	3		T2	1		T4	615
valid_sources[0x71]	18873	1		T1	1		T4	690		T5	115
valid_sources[0x72]	19504	1		T1	1		T4	620		T5	121
valid_sources[0x73]	17580	1		T1	3		T2	2		T4	617
valid_sources[0x74]	18130	1		T2	7		T4	650		T5	160
valid_sources[0x75]	18743	1		T1	2		T4	619		T5	116
valid_sources[0x76]	17650	1		T4	613		T5	145		T9	206
valid_sources[0x77]	18101	1		T1	3		T2	5		T4	632
valid_sources[0x78]	17917	1		T1	1		T2	6		T4	623
valid_sources[0x79]	20156	1		T4	629		T5	152		T9	199
valid_sources[0x7a]	18963	1		T1	2		T2	5		T4	583
valid_sources[0x7b]	18729	1		T1	2		T4	605		T5	130
valid_sources[0x7c]	18887	1		T1	3		T4	620		T5	139
valid_sources[0x7d]	18833	1		T1	3		T2	1		T4	585
valid_sources[0x7e]	18569	1		T1	1		T4	671		T5	122
valid_sources[0x7f]	18793	1		T1	1		T4	650		T5	91
valid_sources[0x80]	18975	1		T2	3		T4	612		T5	160

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1106943

1

T1

14

T2

21

T4

36658

values[0x0]

all_enables

biggest_size

1665915

1

T1

159

T2

98

T3

8

values[0x1]

all_enables

biggest_size

1661229

1

T1

124

T2

100

T3

6