Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	691644174	5233570	0	0
wdog_bark_thold_rd_A	691644174	61041	0	0
wdog_bite_thold_rd_A	691644174	53766	0	0
wdog_ctrl_rd_A	691644174	54398	0	0
wdog_regwen_rd_A	691644174	63111	0	0
wkup_ctrl_rd_A	691644174	53317	0	0
wkup_thold_hi_rd_A	691644174	62109	0	0
wkup_thold_lo_rd_A	691644174	53288	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	691644174	5233570	0	0
T4	466846	175369	0	0
T5	147433	36346	0	0
T6	114280	0	0	0
T7	25100	0	0	0
T8	50862	0	0	0
T9	150040	54483	0	0
T10	337494	0	0	0
T11	346759	0	0	0
T12	936888	21368	0	0
T13	576053	0	0	0
T14	0	155687	0	0
T21	0	202461	0	0
T27	0	103976	0	0
T28	0	47505	0	0
T29	0	60440	0	0
T30	0	194094	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	691644174	61041	0	0
T5	147433	1906	0	0
T6	114280	0	0	0
T7	25100	0	0	0
T8	50862	0	0	0
T9	150040	0	0	0
T10	337494	0	0	0
T11	346759	0	0	0
T12	936888	2047	0	0
T13	576053	0	0	0
T14	684423	15262	0	0
T27	0	10348	0	0
T28	0	4796	0	0
T70	0	529	0	0
T75	0	6249	0	0
T76	0	4283	0	0
T77	0	7312	0	0
T78	0	6809	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	691644174	53766	0	0
T5	147433	1650	0	0
T6	114280	0	0	0
T7	25100	0	0	0
T8	50862	0	0	0
T9	150040	0	0	0
T10	337494	0	0	0
T11	346759	0	0	0
T12	936888	2033	0	0
T13	576053	0	0	0
T14	684423	13503	0	0
T27	0	9280	0	0
T28	0	4091	0	0
T70	0	487	0	0
T75	0	5622	0	0
T76	0	3812	0	0
T77	0	6231	0	0
T78	0	5535	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	691644174	54398	0	0
T5	147433	1715	0	0
T6	114280	0	0	0
T7	25100	0	0	0
T8	50862	0	0	0
T9	150040	0	0	0
T10	337494	0	0	0
T11	346759	0	0	0
T12	936888	1804	0	0
T13	576053	0	0	0
T14	684423	13577	0	0
T27	0	9372	0	0
T28	0	4089	0	0
T70	0	497	0	0
T75	0	5719	0	0
T76	0	3785	0	0
T77	0	6570	0	0
T78	0	5552	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	691644174	63111	0	0
T5	147433	1973	0	0
T6	114280	0	0	0
T7	25100	0	0	0
T8	50862	0	0	0
T9	150040	0	0	0
T10	337494	0	0	0
T11	346759	0	0	0
T12	936888	2377	0	0
T13	576053	0	0	0
T14	684423	15536	0	0
T27	0	10781	0	0
T28	0	4849	0	0
T70	0	576	0	0
T75	0	6747	0	0
T76	0	4478	0	0
T77	0	7149	0	0
T78	0	6674	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	691644174	53317	0	0
T5	147433	1534	0	0
T6	114280	0	0	0
T7	25100	0	0	0
T8	50862	0	0	0
T9	150040	0	0	0
T10	337494	0	0	0
T11	346759	0	0	0
T12	936888	1808	0	0
T13	576053	0	0	0
T14	684423	13260	0	0
T27	0	9357	0	0
T28	0	4252	0	0
T70	0	508	0	0
T75	0	5526	0	0
T76	0	3950	0	0
T77	0	5973	0	0
T78	0	5566	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	691644174	62109	0	0
T5	147433	1945	0	0
T6	114280	0	0	0
T7	25100	0	0	0
T8	50862	0	0	0
T9	150040	0	0	0
T10	337494	0	0	0
T11	346759	0	0	0
T12	936888	2303	0	0
T13	576053	0	0	0
T14	684423	15196	0	0
T27	0	10756	0	0
T28	0	4724	0	0
T70	0	531	0	0
T75	0	6552	0	0
T76	0	4666	0	0
T77	0	7217	0	0
T78	0	6444	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	691644174	53288	0	0
T5	147433	1663	0	0
T6	114280	0	0	0
T7	25100	0	0	0
T8	50862	0	0	0
T9	150040	0	0	0
T10	337494	0	0	0
T11	346759	0	0	0
T12	936888	1993	0	0
T13	576053	0	0	0
T14	684423	13466	0	0
T27	0	8895	0	0
T28	0	3854	0	0
T70	0	517	0	0
T75	0	5693	0	0
T76	0	3652	0	0
T77	0	6522	0	0
T78	0	5394	0	0