Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	803998563	5682400	0	0
wdog_bark_thold_rd_A	803998563	116154	0	0
wdog_bite_thold_rd_A	803998563	102135	0	0
wdog_ctrl_rd_A	803998563	103121	0	0
wdog_regwen_rd_A	803998563	117018	0	0
wkup_ctrl_rd_A	803998563	102406	0	0
wkup_thold_hi_rd_A	803998563	117206	0	0
wkup_thold_lo_rd_A	803998563	101765	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	803998563	5682400	0	0
T1	698365	190727	0	0
T2	658498	0	0	0
T3	29482	0	0	0
T5	295429	0	0	0
T6	11535	0	0	0
T7	209036	76162	0	0
T8	12288	0	0	0
T9	802739	0	0	0
T10	255556	0	0	0
T11	44236	0	0	0
T13	0	154325	0	0
T18	0	170905	0	0
T28	0	49294	0	0
T29	0	55245	0	0
T30	0	61726	0	0
T31	0	62293	0	0
T32	0	156201	0	0
T33	0	37277	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	803998563	116154	0	0
T13	680056	16362	0	0
T14	192213	0	0	0
T18	630500	0	0	0
T19	40294	0	0	0
T33	0	3713	0	0
T34	533687	0	0	0
T35	176555	0	0	0
T36	35303	0	0	0
T37	317021	0	0	0
T38	154544	0	0	0
T42	134795	0	0	0
T43	0	21696	0	0
T79	0	11593	0	0
T80	0	8022	0	0
T81	0	11799	0	0
T82	0	13300	0	0
T83	0	7945	0	0
T84	0	5074	0	0
T85	0	6412	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	803998563	102135	0	0
T13	680056	14768	0	0
T14	192213	0	0	0
T18	630500	0	0	0
T19	40294	0	0	0
T33	0	3564	0	0
T34	533687	0	0	0
T35	176555	0	0	0
T36	35303	0	0	0
T37	317021	0	0	0
T38	154544	0	0	0
T42	134795	0	0	0
T43	0	18682	0	0
T79	0	9887	0	0
T80	0	7040	0	0
T81	0	10151	0	0
T82	0	12047	0	0
T83	0	6850	0	0
T84	0	4459	0	0
T85	0	5857	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	803998563	103121	0	0
T13	680056	14088	0	0
T14	192213	0	0	0
T18	630500	0	0	0
T19	40294	0	0	0
T33	0	3127	0	0
T34	533687	0	0	0
T35	176555	0	0	0
T36	35303	0	0	0
T37	317021	0	0	0
T38	154544	0	0	0
T42	134795	0	0	0
T43	0	19312	0	0
T79	0	10183	0	0
T80	0	7225	0	0
T81	0	10597	0	0
T82	0	11740	0	0
T83	0	7126	0	0
T84	0	4285	0	0
T85	0	5754	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	803998563	117018	0	0
T13	680056	16045	0	0
T14	192213	0	0	0
T18	630500	0	0	0
T19	40294	0	0	0
T33	0	3782	0	0
T34	533687	0	0	0
T35	176555	0	0	0
T36	35303	0	0	0
T37	317021	0	0	0
T38	154544	0	0	0
T42	134795	0	0	0
T43	0	21537	0	0
T79	0	11712	0	0
T80	0	8397	0	0
T81	0	12060	0	0
T82	0	13207	0	0
T83	0	8073	0	0
T84	0	4903	0	0
T85	0	6719	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	803998563	102406	0	0
T13	680056	14038	0	0
T14	192213	0	0	0
T18	630500	0	0	0
T19	40294	0	0	0
T33	0	3284	0	0
T34	533687	0	0	0
T35	176555	0	0	0
T36	35303	0	0	0
T37	317021	0	0	0
T38	154544	0	0	0
T42	134795	0	0	0
T43	0	19414	0	0
T79	0	9917	0	0
T80	0	7005	0	0
T81	0	10235	0	0
T82	0	11934	0	0
T83	0	7522	0	0
T84	0	4167	0	0
T85	0	5720	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	803998563	117206	0	0
T13	680056	15968	0	0
T14	192213	0	0	0
T18	630500	0	0	0
T19	40294	0	0	0
T33	0	3807	0	0
T34	533687	0	0	0
T35	176555	0	0	0
T36	35303	0	0	0
T37	317021	0	0	0
T38	154544	0	0	0
T42	134795	0	0	0
T43	0	22807	0	0
T79	0	11330	0	0
T80	0	8387	0	0
T81	0	12110	0	0
T82	0	13498	0	0
T83	0	7548	0	0
T84	0	4971	0	0
T85	0	6506	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	803998563	101765	0	0
T13	680056	13643	0	0
T14	192213	0	0	0
T18	630500	0	0	0
T19	40294	0	0	0
T33	0	3331	0	0
T34	533687	0	0	0
T35	176555	0	0	0
T36	35303	0	0	0
T37	317021	0	0	0
T38	154544	0	0	0
T42	134795	0	0	0
T43	0	19733	0	0
T79	0	10155	0	0
T80	0	6888	0	0
T81	0	10356	0	0
T82	0	11413	0	0
T83	0	7204	0	0
T84	0	3958	0	0
T85	0	5791	0	0