Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	371880	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4556093	1		T1	79518		T2	12		T3	15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1213878	1		T1	20971		T2	1		T3	1
values[0x0]	1740388	1		T1	30580		T2	8		T3	13
values[0x1]	1973707	1		T1	34203		T2	11		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	165910	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4762063	1		T1	82875		T2	13		T3	16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18951	1		T1	356		T8	503		T9	1
valid_sources[0x01]	21099	1		T1	292		T5	3		T8	571
valid_sources[0x02]	19790	1		T1	316		T3	6		T5	4
valid_sources[0x03]	17799	1		T1	326		T8	511		T10	213
valid_sources[0x04]	18011	1		T1	319		T5	5		T8	286
valid_sources[0x05]	17659	1		T1	347		T8	546		T10	234
valid_sources[0x06]	21293	1		T1	299		T5	6		T8	505
valid_sources[0x07]	19580	1		T1	296		T8	557		T9	1
valid_sources[0x08]	20509	1		T1	362		T8	526		T10	292
valid_sources[0x09]	19900	1		T1	361		T3	1		T8	431
valid_sources[0x0a]	20041	1		T1	288		T8	498		T10	275
valid_sources[0x0b]	17835	1		T1	324		T5	4		T8	512
valid_sources[0x0c]	17009	1		T1	310		T8	485		T10	263
valid_sources[0x0d]	20218	1		T1	330		T8	519		T10	207
valid_sources[0x0e]	19134	1		T1	373		T8	461		T10	173
valid_sources[0x0f]	16344	1		T1	336		T5	5		T8	434
valid_sources[0x10]	19045	1		T1	325		T8	501		T10	260
valid_sources[0x11]	18407	1		T1	296		T5	4		T8	579
valid_sources[0x12]	19550	1		T1	378		T5	1		T8	450
valid_sources[0x13]	18956	1		T1	344		T8	595		T10	243
valid_sources[0x14]	18814	1		T1	346		T8	545		T10	309
valid_sources[0x15]	18967	1		T1	350		T5	4		T7	2
valid_sources[0x16]	20018	1		T1	323		T5	1		T8	500
valid_sources[0x17]	19922	1		T1	363		T5	3		T7	3
valid_sources[0x18]	19280	1		T1	357		T8	412		T10	204
valid_sources[0x19]	19457	1		T1	361		T8	542		T9	1
valid_sources[0x1a]	18275	1		T1	381		T8	353		T10	262
valid_sources[0x1b]	19933	1		T1	431		T8	507		T10	230
valid_sources[0x1c]	17856	1		T1	338		T8	536		T9	1
valid_sources[0x1d]	20861	1		T1	277		T5	18		T8	549
valid_sources[0x1e]	18646	1		T1	380		T7	3		T8	457
valid_sources[0x1f]	18774	1		T1	315		T8	488		T10	220
valid_sources[0x20]	19468	1		T1	309		T8	450		T10	221
valid_sources[0x21]	19959	1		T1	375		T3	2		T8	445
valid_sources[0x22]	19728	1		T1	265		T8	406		T10	226
valid_sources[0x23]	20438	1		T1	392		T4	2		T8	455
valid_sources[0x24]	19291	1		T1	334		T5	3		T8	452
valid_sources[0x25]	17699	1		T1	293		T8	487		T10	276
valid_sources[0x26]	20743	1		T1	385		T8	511		T10	245
valid_sources[0x27]	20056	1		T1	302		T5	1		T8	461
valid_sources[0x28]	20370	1		T1	334		T3	1		T8	498
valid_sources[0x29]	16374	1		T1	345		T5	1		T8	393
valid_sources[0x2a]	19386	1		T1	295		T8	492		T10	240
valid_sources[0x2b]	18270	1		T1	343		T8	432		T10	229
valid_sources[0x2c]	18724	1		T1	314		T5	3		T8	532
valid_sources[0x2d]	20808	1		T1	300		T8	515		T10	263
valid_sources[0x2e]	20319	1		T1	367		T8	351		T10	238
valid_sources[0x2f]	20762	1		T1	312		T5	1		T8	522
valid_sources[0x30]	19241	1		T1	361		T4	10		T8	544
valid_sources[0x31]	20012	1		T1	328		T8	454		T10	207
valid_sources[0x32]	20269	1		T1	317		T8	453		T10	240
valid_sources[0x33]	19896	1		T1	332		T7	3		T8	547
valid_sources[0x34]	20816	1		T1	341		T2	1		T5	3
valid_sources[0x35]	18885	1		T1	316		T5	5		T8	530
valid_sources[0x36]	20343	1		T1	287		T5	8		T8	648
valid_sources[0x37]	19296	1		T1	386		T5	1		T8	449
valid_sources[0x38]	19918	1		T1	281		T8	404		T9	3
valid_sources[0x39]	17572	1		T1	365		T8	611		T10	267
valid_sources[0x3a]	19125	1		T1	393		T8	561		T10	238
valid_sources[0x3b]	18502	1		T1	328		T8	363		T10	252
valid_sources[0x3c]	19425	1		T1	313		T8	563		T10	263
valid_sources[0x3d]	17484	1		T1	361		T5	4		T8	484
valid_sources[0x3e]	20263	1		T1	329		T8	453		T10	281
valid_sources[0x3f]	19335	1		T1	345		T5	5		T8	460
valid_sources[0x40]	19347	1		T1	311		T8	492		T10	234
valid_sources[0x41]	20997	1		T1	294		T5	3		T8	511
valid_sources[0x42]	19255	1		T1	338		T8	355		T10	218
valid_sources[0x43]	18677	1		T1	306		T8	456		T10	246
valid_sources[0x44]	19736	1		T1	257		T2	5		T5	2
valid_sources[0x45]	20944	1		T1	301		T8	428		T10	299
valid_sources[0x46]	19077	1		T1	288		T8	477		T10	252
valid_sources[0x47]	18418	1		T1	284		T8	383		T10	298
valid_sources[0x48]	20289	1		T1	309		T8	435		T10	272
valid_sources[0x49]	18268	1		T1	333		T8	344		T10	170
valid_sources[0x4a]	20148	1		T1	344		T5	7		T8	415
valid_sources[0x4b]	18405	1		T1	338		T8	460		T10	285
valid_sources[0x4c]	19864	1		T1	326		T8	473		T10	267
valid_sources[0x4d]	18734	1		T1	282		T8	496		T10	240
valid_sources[0x4e]	19213	1		T1	392		T5	2		T8	443
valid_sources[0x4f]	19237	1		T1	362		T4	1		T8	374
valid_sources[0x50]	20709	1		T1	369		T5	1		T8	374
valid_sources[0x51]	20440	1		T1	320		T5	1		T8	403
valid_sources[0x52]	17159	1		T1	299		T5	3		T8	470
valid_sources[0x53]	17772	1		T1	262		T8	449		T10	271
valid_sources[0x54]	19603	1		T1	293		T8	446		T10	266
valid_sources[0x55]	18335	1		T1	328		T5	1		T8	381
valid_sources[0x56]	17971	1		T1	293		T8	279		T10	271
valid_sources[0x57]	19583	1		T1	331		T5	1		T8	603
valid_sources[0x58]	16924	1		T1	336		T8	581		T10	307
valid_sources[0x59]	18882	1		T1	365		T5	3		T8	530
valid_sources[0x5a]	19017	1		T1	308		T8	349		T10	257
valid_sources[0x5b]	19635	1		T1	302		T5	1		T8	456
valid_sources[0x5c]	19065	1		T1	353		T8	461		T10	241
valid_sources[0x5d]	19392	1		T1	379		T8	387		T9	1
valid_sources[0x5e]	18148	1		T1	298		T8	460		T10	244
valid_sources[0x5f]	20000	1		T1	283		T8	471		T10	273
valid_sources[0x60]	18955	1		T1	327		T8	399		T10	254
valid_sources[0x61]	19204	1		T1	298		T8	499		T10	240
valid_sources[0x62]	19433	1		T1	328		T5	3		T8	488
valid_sources[0x63]	19538	1		T1	427		T8	485		T10	254
valid_sources[0x64]	19464	1		T1	338		T7	1		T8	502
valid_sources[0x65]	19491	1		T1	396		T8	515		T10	211
valid_sources[0x66]	19728	1		T1	323		T8	457		T10	267
valid_sources[0x67]	18732	1		T1	279		T5	1		T8	488
valid_sources[0x68]	19115	1		T1	338		T5	5		T8	309
valid_sources[0x69]	18731	1		T1	366		T5	1		T8	491
valid_sources[0x6a]	18814	1		T1	318		T8	513		T10	238
valid_sources[0x6b]	18418	1		T1	340		T5	4		T8	506
valid_sources[0x6c]	18365	1		T1	331		T8	377		T10	197
valid_sources[0x6d]	20092	1		T1	349		T7	1		T8	409
valid_sources[0x6e]	21093	1		T1	366		T3	1		T8	352
valid_sources[0x6f]	17946	1		T1	365		T3	4		T5	4
valid_sources[0x70]	19342	1		T1	349		T5	5		T8	443
valid_sources[0x71]	18791	1		T1	341		T8	390		T10	285
valid_sources[0x72]	19901	1		T1	309		T8	296		T9	1
valid_sources[0x73]	19571	1		T1	378		T8	444		T10	248
valid_sources[0x74]	19670	1		T1	386		T8	448		T10	243
valid_sources[0x75]	19044	1		T1	271		T3	2		T5	1
valid_sources[0x76]	18387	1		T1	279		T8	459		T10	231
valid_sources[0x77]	19617	1		T1	353		T4	3		T8	487
valid_sources[0x78]	19650	1		T1	273		T8	524		T10	220
valid_sources[0x79]	18697	1		T1	351		T5	5		T8	458
valid_sources[0x7a]	19002	1		T1	299		T8	499		T10	233
valid_sources[0x7b]	19503	1		T1	290		T8	589		T10	231
valid_sources[0x7c]	18973	1		T1	371		T5	10		T8	335
valid_sources[0x7d]	19144	1		T1	341		T8	453		T10	246
valid_sources[0x7e]	18623	1		T1	344		T8	656		T10	294
valid_sources[0x7f]	18091	1		T1	361		T5	2		T8	480
valid_sources[0x80]	18935	1		T1	350		T5	6		T8	373

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1138532

1

T1

19733

T5

24

T8

27774

values[0x0]

all_enables

biggest_size

1709338

1

T1

29940

T2

6

T3

10

values[0x1]

all_enables

biggest_size

1708223

1

T1

29845

T2

6

T3

5