Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	670094404	5408692	0	0
wdog_bark_thold_rd_A	670094404	84180	0	0
wdog_bite_thold_rd_A	670094404	73238	0	0
wdog_ctrl_rd_A	670094404	74471	0	0
wdog_regwen_rd_A	670094404	83274	0	0
wkup_ctrl_rd_A	670094404	73087	0	0
wkup_thold_hi_rd_A	670094404	83005	0	0
wkup_thold_lo_rd_A	670094404	72780	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670094404	5408692	0	0
T1	386489	89075	0	0
T2	139764	0	0	0
T3	11524	0	0	0
T4	19560	0	0	0
T5	194175	0	0	0
T6	9460	0	0	0
T7	396316	0	0	0
T8	576217	122792	0	0
T9	12405	0	0	0
T10	282825	69258	0	0
T12	0	49976	0	0
T21	0	123915	0	0
T25	0	85815	0	0
T28	0	66345	0	0
T40	0	77972	0	0
T41	0	75644	0	0
T42	0	166772	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670094404	84180	0	0
T1	386489	8759	0	0
T2	139764	0	0	0
T3	11524	0	0	0
T4	19560	0	0	0
T5	194175	0	0	0
T6	9460	0	0	0
T7	396316	0	0	0
T8	576217	13363	0	0
T9	12405	0	0	0
T10	282825	0	0	0
T12	0	5361	0	0
T25	0	8590	0	0
T89	0	4756	0	0
T90	0	876	0	0
T91	0	6513	0	0
T92	0	2178	0	0
T93	0	3641	0	0
T94	0	8557	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670094404	73238	0	0
T1	386489	8099	0	0
T2	139764	0	0	0
T3	11524	0	0	0
T4	19560	0	0	0
T5	194175	0	0	0
T6	9460	0	0	0
T7	396316	0	0	0
T8	576217	11139	0	0
T9	12405	0	0	0
T10	282825	0	0	0
T12	0	4581	0	0
T25	0	6959	0	0
T89	0	4349	0	0
T90	0	714	0	0
T91	0	6144	0	0
T92	0	1931	0	0
T93	0	3209	0	0
T94	0	7626	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670094404	74471	0	0
T1	386489	7670	0	0
T2	139764	0	0	0
T3	11524	0	0	0
T4	19560	0	0	0
T5	194175	0	0	0
T6	9460	0	0	0
T7	396316	0	0	0
T8	576217	12056	0	0
T9	12405	0	0	0
T10	282825	0	0	0
T12	0	4505	0	0
T25	0	7234	0	0
T89	0	4743	0	0
T90	0	676	0	0
T91	0	5827	0	0
T92	0	1855	0	0
T93	0	3053	0	0
T94	0	7422	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670094404	83274	0	0
T1	386489	9160	0	0
T2	139764	0	0	0
T3	11524	0	0	0
T4	19560	0	0	0
T5	194175	0	0	0
T6	9460	0	0	0
T7	396316	0	0	0
T8	576217	13194	0	0
T9	12405	0	0	0
T10	282825	0	0	0
T12	0	5072	0	0
T25	0	8492	0	0
T89	0	4784	0	0
T90	0	745	0	0
T91	0	6406	0	0
T92	0	2238	0	0
T93	0	3621	0	0
T94	0	8428	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670094404	73087	0	0
T1	386489	7836	0	0
T2	139764	0	0	0
T3	11524	0	0	0
T4	19560	0	0	0
T5	194175	0	0	0
T6	9460	0	0	0
T7	396316	0	0	0
T8	576217	11344	0	0
T9	12405	0	0	0
T10	282825	0	0	0
T12	0	4370	0	0
T25	0	7033	0	0
T89	0	4373	0	0
T90	0	743	0	0
T91	0	5844	0	0
T92	0	1876	0	0
T93	0	3345	0	0
T94	0	7743	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670094404	83005	0	0
T1	386489	9116	0	0
T2	139764	0	0	0
T3	11524	0	0	0
T4	19560	0	0	0
T5	194175	0	0	0
T6	9460	0	0	0
T7	396316	0	0	0
T8	576217	13093	0	0
T9	12405	0	0	0
T10	282825	0	0	0
T12	0	5299	0	0
T25	0	8687	0	0
T89	0	4933	0	0
T90	0	773	0	0
T91	0	6107	0	0
T92	0	2046	0	0
T93	0	3519	0	0
T94	0	8314	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670094404	72780	0	0
T1	386489	7616	0	0
T2	139764	0	0	0
T3	11524	0	0	0
T4	19560	0	0	0
T5	194175	0	0	0
T6	9460	0	0	0
T7	396316	0	0	0
T8	576217	11375	0	0
T9	12405	0	0	0
T10	282825	0	0	0
T12	0	4334	0	0
T25	0	7445	0	0
T89	0	4332	0	0
T90	0	741	0	0
T91	0	5691	0	0
T92	0	2022	0	0
T93	0	3033	0	0
T94	0	7549	0	0