Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.27	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	3	170	98.27

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	0	34	100.00	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	30555	1		T1	12		T3	20		T4	11
bark[1]	416	1		T3	21		T7	21		T168	219
bark[2]	623	1		T3	309		T40	21		T41	21
bark[3]	530	1		T7	78		T11	14		T33	99
bark[4]	400	1		T34	5		T103	14		T41	21
bark[5]	227	1		T11	21		T45	14		T167	21
bark[6]	1264	1		T14	21		T97	273		T91	26
bark[7]	205	1		T35	39		T53	56		T162	21
bark[8]	536	1		T12	21		T30	21		T34	26
bark[9]	160	1		T18	31		T91	7		T98	26
bark[10]	614	1		T52	171		T110	42		T91	94
bark[11]	771	1		T18	21		T30	116		T33	219
bark[12]	404	1		T31	21		T141	21		T131	30
bark[13]	718	1		T3	26		T11	21		T45	21
bark[14]	576	1		T104	14		T54	116		T29	21
bark[15]	778	1		T9	14		T45	21		T54	266
bark[16]	546	1		T11	21		T12	56		T30	21
bark[17]	218	1		T52	26		T162	21		T130	89
bark[18]	917	1		T2	14		T30	21		T28	14
bark[19]	604	1		T31	51		T40	26		T47	14
bark[20]	220	1		T96	35		T141	35		T113	14
bark[21]	1045	1		T3	21		T31	21		T41	196
bark[22]	858	1		T11	30		T18	21		T31	215
bark[23]	743	1		T7	21		T40	120		T41	30
bark[24]	231	1		T30	21		T148	66		T101	14
bark[25]	1177	1		T97	33		T98	511		T168	21
bark[26]	800	1		T7	257		T34	21		T42	7
bark[27]	56	1		T11	21		T98	21		T195	14
bark[28]	382	1		T41	160		T24	21		T148	26
bark[29]	686	1		T52	21		T91	229		T158	42
bark[30]	734	1		T7	59		T32	21		T46	14
bark[31]	174	1		T11	21		T52	7		T97	45
bark_0	4848	1		T1	7		T2	7		T3	44

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	29921	1		T1	11		T3	12		T4	10
bite[1]	456	1		T3	308		T7	21		T52	25
bite[2]	1056	1		T11	51		T12	21		T31	72
bite[3]	342	1		T7	21		T41	21		T53	26
bite[4]	280	1		T183	59		T113	13		T131	30
bite[5]	162	1		T54	21		T110	21		T28	13
bite[6]	517	1		T42	184		T119	13		T174	51
bite[7]	178	1		T11	21		T14	21		T123	18
bite[8]	188	1		T110	21		T98	21		T164	68
bite[9]	528	1		T30	21		T130	423		T94	50
bite[10]	524	1		T48	13		T91	55		T135	13
bite[11]	942	1		T3	4		T41	21		T162	21
bite[12]	622	1		T35	39		T130	21		T168	21
bite[13]	387	1		T31	21		T162	21		T24	21
bite[14]	658	1		T97	277		T140	21		T129	244
bite[15]	217	1		T11	21		T18	30		T40	26
bite[16]	430	1		T2	13		T45	21		T52	73
bite[17]	1122	1		T7	256		T30	116		T42	25
bite[18]	893	1		T7	77		T33	98		T40	21
bite[19]	960	1		T31	214		T104	13		T41	180
bite[20]	589	1		T41	339		T137	21		T97	4
bite[21]	170	1		T18	21		T98	21		T145	13
bite[22]	289	1		T12	56		T24	35		T123	21
bite[23]	1226	1		T7	21		T30	21		T34	4
bite[24]	375	1		T3	21		T30	42		T32	21
bite[25]	120	1		T9	13		T103	13		T162	39
bite[26]	678	1		T18	21		T40	119		T46	13
bite[27]	288	1		T11	42		T41	21		T132	58
bite[28]	1077	1		T3	21		T35	43		T42	26
bite[29]	500	1		T34	21		T155	13		T130	21
bite[30]	869	1		T42	25		T91	119		T191	13
bite[31]	1051	1		T3	26		T7	58		T45	13
bite_0	5401	1		T1	8		T2	8		T3	49

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	44269	1		T1	19		T2	21		T3	441
auto[1]	8747	1		T4	7		T14	39		T18	69

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	0	34	100.00

User Defined Bins for prescale_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale_max	40	1		T98	40		-	-		-	-
prescale[0]	1362	1		T3	105		T7	19		T34	57
prescale[1]	1461	1		T31	41		T34	96		T42	144
prescale[2]	1137	1		T7	80		T33	40		T42	28
prescale[3]	1235	1		T5	28		T7	19		T33	19
prescale[4]	749	1		T1	9		T7	54		T53	36
prescale[5]	709	1		T5	40		T14	19		T33	19
prescale[6]	528	1		T7	90		T14	19		T33	2
prescale[7]	544	1		T3	19		T45	84		T42	24
prescale[8]	651	1		T6	9		T41	19		T96	19
prescale[9]	491	1		T7	2		T10	9		T30	19
prescale[10]	1402	1		T14	113		T31	28		T32	23
prescale[11]	933	1		T33	2		T40	172		T42	2
prescale[12]	813	1		T7	42		T31	2		T40	2
prescale[13]	436	1		T31	40		T34	2		T35	41
prescale[14]	731	1		T40	29		T42	2		T97	140
prescale[15]	447	1		T3	2		T5	2		T12	38
prescale[16]	743	1		T11	63		T13	9		T42	2
prescale[17]	1330	1		T3	61		T14	2		T31	75
prescale[18]	663	1		T14	57		T30	19		T41	24
prescale[19]	480	1		T14	4		T45	19		T52	2
prescale[20]	1042	1		T3	9		T14	9		T18	19
prescale[21]	597	1		T7	19		T31	64		T42	2
prescale[22]	966	1		T5	19		T7	28		T30	65
prescale[23]	1077	1		T7	21		T30	78		T31	239
prescale[24]	668	1		T5	2		T7	29		T12	36
prescale[25]	964	1		T3	93		T7	58		T12	75
prescale[26]	1145	1		T5	24		T30	9		T33	26
prescale[27]	833	1		T5	2		T7	79		T33	2
prescale[28]	638	1		T7	2		T12	28		T40	9
prescale[29]	928	1		T18	19		T31	107		T33	43
prescale[30]	652	1		T3	2		T30	40		T98	115
prescale[31]	1294	1		T5	2		T7	19		T12	45
prescale_0	25367	1		T1	10		T2	21		T3	150

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	40536	1		T1	19		T2	21		T3	322
auto[1]	12480	1		T3	119		T4	9		T5	68

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	53016	1		T1	19		T2	21		T3	441

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	30894	1		T1	14		T2	1		T3	165
wkup[1]	244	1		T40	26		T53	21		T54	21
wkup[2]	273	1		T7	21		T41	21		T53	36
wkup[3]	422	1		T34	21		T40	21		T91	29
wkup[4]	249	1		T14	51		T30	21		T103	15
wkup[5]	249	1		T7	21		T33	21		T53	21
wkup[6]	114	1		T12	21		T31	21		T96	21
wkup[7]	311	1		T7	26		T31	21		T42	39
wkup[8]	212	1		T31	30		T34	21		T41	21
wkup[9]	304	1		T34	21		T46	15		T42	21
wkup[10]	226	1		T31	15		T92	21		T101	75
wkup[11]	153	1		T137	21		T183	26		T141	56
wkup[12]	230	1		T44	15		T33	21		T40	15
wkup[13]	176	1		T11	15		T30	21		T33	26
wkup[14]	466	1		T11	30		T45	21		T52	21
wkup[15]	341	1		T7	26		T11	21		T41	21
wkup[16]	341	1		T41	21		T98	21		T168	42
wkup[17]	343	1		T42	21		T53	21		T54	42
wkup[18]	261	1		T31	21		T97	21		T190	15
wkup[19]	137	1		T11	42		T40	21		T52	6
wkup[20]	331	1		T30	21		T41	21		T54	21
wkup[21]	502	1		T7	30		T40	30		T53	21
wkup[22]	283	1		T53	30		T54	21		T91	26
wkup[23]	311	1		T31	21		T41	8		T53	21
wkup[24]	246	1		T31	21		T33	21		T41	42
wkup[25]	194	1		T42	21		T168	8		T123	21
wkup[26]	167	1		T53	21		T98	36		T148	21
wkup[27]	243	1		T3	21		T53	21		T110	21
wkup[28]	533	1		T3	26		T7	42		T11	21
wkup[29]	406	1		T11	21		T12	35		T41	21
wkup[30]	185	1		T3	21		T54	21		T186	15
wkup[31]	411	1		T3	21		T7	21		T30	21
wkup[32]	129	1		T12	21		T183	21		T113	15
wkup[33]	312	1		T3	21		T34	21		T52	42
wkup[34]	357	1		T14	21		T18	21		T31	15
wkup[35]	423	1		T18	21		T32	21		T33	30
wkup[36]	144	1		T31	21		T45	15		T96	30
wkup[37]	204	1		T30	21		T33	21		T35	39
wkup[38]	556	1		T2	15		T18	21		T40	26
wkup[39]	342	1		T30	21		T31	21		T41	30
wkup[40]	269	1		T7	42		T97	21		T24	21
wkup[41]	336	1		T32	21		T53	21		T131	21
wkup[42]	280	1		T3	6		T9	15		T14	21
wkup[43]	215	1		T42	26		T137	21		T25	15
wkup[44]	371	1		T54	21		T97	15		T130	65
wkup[45]	155	1		T3	21		T24	21		T55	21
wkup[46]	176	1		T53	21		T96	21		T182	15
wkup[47]	327	1		T40	21		T54	21		T97	42
wkup[48]	332	1		T31	30		T32	26		T40	21
wkup[49]	329	1		T3	42		T32	21		T40	26
wkup[50]	367	1		T41	21		T54	21		T91	44
wkup[51]	274	1		T45	21		T52	52		T96	40
wkup[52]	276	1		T30	21		T31	21		T42	47
wkup[53]	388	1		T7	46		T30	21		T35	21
wkup[54]	198	1		T7	21		T33	30		T162	21
wkup[55]	371	1		T3	42		T31	21		T97	21
wkup[56]	320	1		T45	35		T41	42		T168	30
wkup[57]	125	1		T3	21		T5	21		T140	15
wkup[58]	198	1		T52	21		T91	26		T99	21
wkup[59]	239	1		T48	15		T53	26		T23	15
wkup[60]	420	1		T7	21		T33	30		T45	30
wkup[61]	316	1		T40	21		T42	26		T98	21
wkup[62]	342	1		T7	21		T31	21		T34	6
wkup[63]	294	1		T52	8		T98	68		T92	30
wkup_0	3873	1		T1	5		T2	5		T3	34