Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.04 99.33 93.67 100.00 98.40 99.51 49.33


Total test records in report: 422
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T39 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3017183795 Jul 13 06:18:37 PM PDT 24 Jul 13 06:18:40 PM PDT 24 517814626 ps
T285 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3991463088 Jul 13 06:18:50 PM PDT 24 Jul 13 06:18:55 PM PDT 24 542953856 ps
T286 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3341782049 Jul 13 06:18:50 PM PDT 24 Jul 13 06:18:53 PM PDT 24 421563097 ps
T38 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.527621671 Jul 13 06:18:47 PM PDT 24 Jul 13 06:18:55 PM PDT 24 8726558622 ps
T197 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1508803001 Jul 13 06:18:39 PM PDT 24 Jul 13 06:18:46 PM PDT 24 8843985939 ps
T287 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1306388973 Jul 13 06:18:48 PM PDT 24 Jul 13 06:18:50 PM PDT 24 415400241 ps
T82 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1599683072 Jul 13 06:18:39 PM PDT 24 Jul 13 06:18:42 PM PDT 24 1754968293 ps
T83 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3618606067 Jul 13 06:18:47 PM PDT 24 Jul 13 06:18:51 PM PDT 24 2142245913 ps
T288 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.4244470200 Jul 13 06:18:40 PM PDT 24 Jul 13 06:18:43 PM PDT 24 492252087 ps
T84 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3573697698 Jul 13 06:18:49 PM PDT 24 Jul 13 06:18:53 PM PDT 24 2203399492 ps
T56 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2912935001 Jul 13 06:18:23 PM PDT 24 Jul 13 06:18:42 PM PDT 24 6417144506 ps
T289 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3154392549 Jul 13 06:18:31 PM PDT 24 Jul 13 06:18:50 PM PDT 24 7239731001 ps
T290 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.175858831 Jul 13 06:18:56 PM PDT 24 Jul 13 06:18:58 PM PDT 24 425763148 ps
T291 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1550061399 Jul 13 06:18:23 PM PDT 24 Jul 13 06:18:26 PM PDT 24 717755052 ps
T292 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1022783434 Jul 13 06:18:49 PM PDT 24 Jul 13 06:18:52 PM PDT 24 724288412 ps
T293 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.4223804914 Jul 13 06:18:48 PM PDT 24 Jul 13 06:18:51 PM PDT 24 419205740 ps
T294 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2598726450 Jul 13 06:18:24 PM PDT 24 Jul 13 06:18:26 PM PDT 24 397803560 ps
T295 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3875472529 Jul 13 06:18:39 PM PDT 24 Jul 13 06:18:41 PM PDT 24 541593777 ps
T57 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3205553621 Jul 13 06:18:23 PM PDT 24 Jul 13 06:18:25 PM PDT 24 422817023 ps
T296 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3183165794 Jul 13 06:18:41 PM PDT 24 Jul 13 06:18:44 PM PDT 24 822288301 ps
T297 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2308486765 Jul 13 06:18:50 PM PDT 24 Jul 13 06:18:55 PM PDT 24 611713382 ps
T298 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.543060718 Jul 13 06:18:59 PM PDT 24 Jul 13 06:19:01 PM PDT 24 522093038 ps
T299 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.435878271 Jul 13 06:18:41 PM PDT 24 Jul 13 06:18:45 PM PDT 24 8286234845 ps
T300 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1602469662 Jul 13 06:18:29 PM PDT 24 Jul 13 06:18:31 PM PDT 24 359144636 ps
T301 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.4093762411 Jul 13 06:18:50 PM PDT 24 Jul 13 06:18:53 PM PDT 24 356544744 ps
T302 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1451615357 Jul 13 06:18:33 PM PDT 24 Jul 13 06:18:35 PM PDT 24 757795894 ps
T303 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.716171606 Jul 13 06:18:26 PM PDT 24 Jul 13 06:18:28 PM PDT 24 603974355 ps
T304 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.4094671494 Jul 13 06:18:49 PM PDT 24 Jul 13 06:18:51 PM PDT 24 530889855 ps
T305 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.628585874 Jul 13 06:18:39 PM PDT 24 Jul 13 06:18:41 PM PDT 24 641745649 ps
T306 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.75567017 Jul 13 06:18:33 PM PDT 24 Jul 13 06:18:36 PM PDT 24 441445352 ps
T307 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.351520871 Jul 13 06:18:40 PM PDT 24 Jul 13 06:18:43 PM PDT 24 529441201 ps
T58 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2539565873 Jul 13 06:18:22 PM PDT 24 Jul 13 06:18:24 PM PDT 24 392084270 ps
T59 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.4174392290 Jul 13 06:18:48 PM PDT 24 Jul 13 06:18:51 PM PDT 24 451562302 ps
T308 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.594029471 Jul 13 06:18:39 PM PDT 24 Jul 13 06:18:42 PM PDT 24 426928921 ps
T60 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.358981538 Jul 13 06:18:34 PM PDT 24 Jul 13 06:18:36 PM PDT 24 537935242 ps
T309 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.453472335 Jul 13 06:18:49 PM PDT 24 Jul 13 06:18:53 PM PDT 24 402444421 ps
T310 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1293720539 Jul 13 06:18:34 PM PDT 24 Jul 13 06:18:39 PM PDT 24 4677238230 ps
T311 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2391827849 Jul 13 06:18:30 PM PDT 24 Jul 13 06:18:31 PM PDT 24 264726112 ps
T312 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3694137807 Jul 13 06:18:59 PM PDT 24 Jul 13 06:19:00 PM PDT 24 541809447 ps
T85 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.955568945 Jul 13 06:18:31 PM PDT 24 Jul 13 06:18:37 PM PDT 24 2957365908 ps
T313 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2822760133 Jul 13 06:18:27 PM PDT 24 Jul 13 06:18:28 PM PDT 24 469746848 ps
T314 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1016878293 Jul 13 06:18:38 PM PDT 24 Jul 13 06:18:42 PM PDT 24 2184858117 ps
T315 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3581661633 Jul 13 06:18:46 PM PDT 24 Jul 13 06:18:48 PM PDT 24 527212527 ps
T316 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2759090818 Jul 13 06:18:39 PM PDT 24 Jul 13 06:18:43 PM PDT 24 4453520910 ps
T317 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2629592116 Jul 13 06:18:47 PM PDT 24 Jul 13 06:18:49 PM PDT 24 306503173 ps
T318 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2515513074 Jul 13 06:18:25 PM PDT 24 Jul 13 06:18:28 PM PDT 24 317625261 ps
T319 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.4197469180 Jul 13 06:18:23 PM PDT 24 Jul 13 06:18:25 PM PDT 24 705044397 ps
T200 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2672593238 Jul 13 06:18:32 PM PDT 24 Jul 13 06:18:37 PM PDT 24 4286565031 ps
T320 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2532656038 Jul 13 06:18:49 PM PDT 24 Jul 13 06:18:53 PM PDT 24 538280202 ps
T321 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.537379021 Jul 13 06:18:31 PM PDT 24 Jul 13 06:18:33 PM PDT 24 425885856 ps
T322 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2192434586 Jul 13 06:19:00 PM PDT 24 Jul 13 06:19:01 PM PDT 24 357294247 ps
T323 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3413330420 Jul 13 06:18:39 PM PDT 24 Jul 13 06:18:41 PM PDT 24 525276454 ps
T324 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2177921248 Jul 13 06:18:43 PM PDT 24 Jul 13 06:18:45 PM PDT 24 4208856971 ps
T325 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.393772028 Jul 13 06:18:33 PM PDT 24 Jul 13 06:18:38 PM PDT 24 8432201935 ps
T61 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1742286223 Jul 13 06:18:29 PM PDT 24 Jul 13 06:18:30 PM PDT 24 421046714 ps
T326 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2939221718 Jul 13 06:18:38 PM PDT 24 Jul 13 06:18:41 PM PDT 24 356891962 ps
T327 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.361400902 Jul 13 06:18:51 PM PDT 24 Jul 13 06:18:54 PM PDT 24 607246759 ps
T328 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.4198149403 Jul 13 06:19:00 PM PDT 24 Jul 13 06:19:02 PM PDT 24 514797587 ps
T329 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2996507614 Jul 13 06:18:32 PM PDT 24 Jul 13 06:18:34 PM PDT 24 331048564 ps
T330 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.517972690 Jul 13 06:18:24 PM PDT 24 Jul 13 06:18:27 PM PDT 24 289037445 ps
T331 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.753701330 Jul 13 06:18:50 PM PDT 24 Jul 13 06:18:53 PM PDT 24 458859666 ps
T332 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1877939558 Jul 13 06:18:49 PM PDT 24 Jul 13 06:19:02 PM PDT 24 7905090887 ps
T86 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3168194678 Jul 13 06:18:37 PM PDT 24 Jul 13 06:18:39 PM PDT 24 1031759959 ps
T333 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.66216300 Jul 13 06:18:24 PM PDT 24 Jul 13 06:18:27 PM PDT 24 397432292 ps
T334 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1528884778 Jul 13 06:18:25 PM PDT 24 Jul 13 06:18:28 PM PDT 24 270173685 ps
T87 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1033866384 Jul 13 06:18:37 PM PDT 24 Jul 13 06:18:38 PM PDT 24 1089660700 ps
T335 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1349126990 Jul 13 06:18:48 PM PDT 24 Jul 13 06:18:50 PM PDT 24 489636607 ps
T336 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1049590573 Jul 13 06:18:46 PM PDT 24 Jul 13 06:18:48 PM PDT 24 403596003 ps
T337 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2794077900 Jul 13 06:18:45 PM PDT 24 Jul 13 06:18:47 PM PDT 24 367375753 ps
T338 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.806079530 Jul 13 06:18:30 PM PDT 24 Jul 13 06:18:31 PM PDT 24 328375313 ps
T88 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2197392707 Jul 13 06:18:23 PM PDT 24 Jul 13 06:18:27 PM PDT 24 2051067609 ps
T62 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2526245243 Jul 13 06:18:33 PM PDT 24 Jul 13 06:18:35 PM PDT 24 399138975 ps
T89 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.825582192 Jul 13 06:18:48 PM PDT 24 Jul 13 06:18:51 PM PDT 24 2553348173 ps
T63 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2512948917 Jul 13 06:18:47 PM PDT 24 Jul 13 06:18:49 PM PDT 24 327825727 ps
T339 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3240577263 Jul 13 06:18:31 PM PDT 24 Jul 13 06:18:33 PM PDT 24 325673868 ps
T340 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.887663691 Jul 13 06:18:38 PM PDT 24 Jul 13 06:18:39 PM PDT 24 340462714 ps
T201 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.4216866568 Jul 13 06:18:39 PM PDT 24 Jul 13 06:18:47 PM PDT 24 4417364116 ps
T341 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.585905401 Jul 13 06:18:41 PM PDT 24 Jul 13 06:18:50 PM PDT 24 4598652601 ps
T90 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2857214615 Jul 13 06:18:49 PM PDT 24 Jul 13 06:18:52 PM PDT 24 1031343987 ps
T67 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2777284871 Jul 13 06:18:22 PM PDT 24 Jul 13 06:18:25 PM PDT 24 624499200 ps
T342 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2535587561 Jul 13 06:18:31 PM PDT 24 Jul 13 06:18:40 PM PDT 24 14131003225 ps
T68 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1667506022 Jul 13 06:18:38 PM PDT 24 Jul 13 06:18:41 PM PDT 24 540275361 ps
T343 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3260934638 Jul 13 06:18:59 PM PDT 24 Jul 13 06:19:00 PM PDT 24 424205202 ps
T344 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2728645652 Jul 13 06:18:48 PM PDT 24 Jul 13 06:18:53 PM PDT 24 8408787140 ps
T345 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.523302957 Jul 13 06:18:51 PM PDT 24 Jul 13 06:18:54 PM PDT 24 432472063 ps
T346 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.168635893 Jul 13 06:18:49 PM PDT 24 Jul 13 06:18:52 PM PDT 24 440213756 ps
T64 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2796420939 Jul 13 06:18:36 PM PDT 24 Jul 13 06:18:38 PM PDT 24 487434589 ps
T347 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1092017615 Jul 13 06:18:37 PM PDT 24 Jul 13 06:18:42 PM PDT 24 2656063936 ps
T348 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2321256223 Jul 13 06:18:25 PM PDT 24 Jul 13 06:18:27 PM PDT 24 460745613 ps
T69 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2582202751 Jul 13 06:18:39 PM PDT 24 Jul 13 06:18:42 PM PDT 24 298252379 ps
T349 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3223993058 Jul 13 06:18:33 PM PDT 24 Jul 13 06:18:35 PM PDT 24 525698889 ps
T350 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3209948925 Jul 13 06:18:27 PM PDT 24 Jul 13 06:18:28 PM PDT 24 460426267 ps
T351 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.4266133723 Jul 13 06:19:00 PM PDT 24 Jul 13 06:19:01 PM PDT 24 394319901 ps
T352 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2811048541 Jul 13 06:18:57 PM PDT 24 Jul 13 06:18:58 PM PDT 24 325997564 ps
T353 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1363176178 Jul 13 06:18:47 PM PDT 24 Jul 13 06:18:49 PM PDT 24 1394005520 ps
T354 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3464818270 Jul 13 06:18:57 PM PDT 24 Jul 13 06:18:58 PM PDT 24 512071376 ps
T355 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1303442020 Jul 13 06:18:47 PM PDT 24 Jul 13 06:18:48 PM PDT 24 481527105 ps
T356 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1819614773 Jul 13 06:18:47 PM PDT 24 Jul 13 06:18:49 PM PDT 24 390872373 ps
T357 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3857372897 Jul 13 06:18:49 PM PDT 24 Jul 13 06:18:53 PM PDT 24 469018017 ps
T358 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2892152144 Jul 13 06:18:39 PM PDT 24 Jul 13 06:18:41 PM PDT 24 390458273 ps
T359 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3841880000 Jul 13 06:18:39 PM PDT 24 Jul 13 06:18:42 PM PDT 24 474897899 ps
T360 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3546860976 Jul 13 06:18:47 PM PDT 24 Jul 13 06:18:53 PM PDT 24 3752009630 ps
T361 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1454625798 Jul 13 06:18:32 PM PDT 24 Jul 13 06:18:37 PM PDT 24 2579423835 ps
T362 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.692295738 Jul 13 06:18:26 PM PDT 24 Jul 13 06:18:30 PM PDT 24 2510390046 ps
T363 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.818520783 Jul 13 06:18:39 PM PDT 24 Jul 13 06:18:42 PM PDT 24 308413429 ps
T364 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2544471526 Jul 13 06:18:46 PM PDT 24 Jul 13 06:18:47 PM PDT 24 802471760 ps
T65 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2454287179 Jul 13 06:18:37 PM PDT 24 Jul 13 06:18:38 PM PDT 24 382526554 ps
T198 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1281502507 Jul 13 06:18:48 PM PDT 24 Jul 13 06:18:53 PM PDT 24 7639015655 ps
T365 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3201482282 Jul 13 06:18:48 PM PDT 24 Jul 13 06:18:51 PM PDT 24 359597871 ps
T366 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.4238175850 Jul 13 06:18:37 PM PDT 24 Jul 13 06:18:40 PM PDT 24 385798084 ps
T367 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3591916249 Jul 13 06:18:54 PM PDT 24 Jul 13 06:18:55 PM PDT 24 300180064 ps
T368 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.515515160 Jul 13 06:18:50 PM PDT 24 Jul 13 06:18:54 PM PDT 24 398723200 ps
T369 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.722946157 Jul 13 06:18:40 PM PDT 24 Jul 13 06:18:44 PM PDT 24 2999033421 ps
T370 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3892988073 Jul 13 06:18:59 PM PDT 24 Jul 13 06:19:01 PM PDT 24 456268696 ps
T371 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3169049850 Jul 13 06:18:48 PM PDT 24 Jul 13 06:18:50 PM PDT 24 265952653 ps
T372 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2716686717 Jul 13 06:18:49 PM PDT 24 Jul 13 06:18:53 PM PDT 24 547446011 ps
T373 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2481588063 Jul 13 06:18:30 PM PDT 24 Jul 13 06:18:32 PM PDT 24 516580572 ps
T374 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.700710532 Jul 13 06:18:23 PM PDT 24 Jul 13 06:18:25 PM PDT 24 386898181 ps
T375 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3001701287 Jul 13 06:18:38 PM PDT 24 Jul 13 06:18:40 PM PDT 24 326384925 ps
T376 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.449896329 Jul 13 06:18:49 PM PDT 24 Jul 13 06:18:51 PM PDT 24 397488122 ps
T66 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.325161433 Jul 13 06:18:31 PM PDT 24 Jul 13 06:18:33 PM PDT 24 522117338 ps
T70 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.4164209673 Jul 13 06:18:32 PM PDT 24 Jul 13 06:18:35 PM PDT 24 399959079 ps
T202 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1092152302 Jul 13 06:18:24 PM PDT 24 Jul 13 06:18:36 PM PDT 24 7788619383 ps
T377 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.132796930 Jul 13 06:18:25 PM PDT 24 Jul 13 06:18:38 PM PDT 24 8071280662 ps
T378 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1782573110 Jul 13 06:18:25 PM PDT 24 Jul 13 06:18:27 PM PDT 24 898948817 ps
T379 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1711520298 Jul 13 06:18:40 PM PDT 24 Jul 13 06:18:43 PM PDT 24 446196059 ps
T380 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1302545060 Jul 13 06:18:57 PM PDT 24 Jul 13 06:18:59 PM PDT 24 520793994 ps
T381 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1883882571 Jul 13 06:18:23 PM PDT 24 Jul 13 06:18:25 PM PDT 24 519434891 ps
T71 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.317718235 Jul 13 06:18:31 PM PDT 24 Jul 13 06:18:33 PM PDT 24 418314317 ps
T382 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3439057139 Jul 13 06:18:58 PM PDT 24 Jul 13 06:18:59 PM PDT 24 398041539 ps
T383 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1270847621 Jul 13 06:18:31 PM PDT 24 Jul 13 06:18:35 PM PDT 24 2004887700 ps
T384 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1530215862 Jul 13 06:18:50 PM PDT 24 Jul 13 06:18:53 PM PDT 24 436418633 ps
T385 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2784201398 Jul 13 06:18:59 PM PDT 24 Jul 13 06:19:01 PM PDT 24 451845843 ps
T386 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2437520641 Jul 13 06:18:22 PM PDT 24 Jul 13 06:18:23 PM PDT 24 510782444 ps
T387 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.806919093 Jul 13 06:18:57 PM PDT 24 Jul 13 06:18:58 PM PDT 24 362804612 ps
T388 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1974543502 Jul 13 06:18:41 PM PDT 24 Jul 13 06:18:44 PM PDT 24 2151663616 ps
T389 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3255273587 Jul 13 06:18:37 PM PDT 24 Jul 13 06:18:40 PM PDT 24 608109827 ps
T72 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3027304131 Jul 13 06:18:41 PM PDT 24 Jul 13 06:18:43 PM PDT 24 328327183 ps
T390 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.4204379239 Jul 13 06:18:31 PM PDT 24 Jul 13 06:18:33 PM PDT 24 413761920 ps
T391 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1190231927 Jul 13 06:18:49 PM PDT 24 Jul 13 06:18:51 PM PDT 24 410248278 ps
T392 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2878824898 Jul 13 06:18:41 PM PDT 24 Jul 13 06:18:45 PM PDT 24 568737290 ps
T393 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2811283165 Jul 13 06:18:39 PM PDT 24 Jul 13 06:18:42 PM PDT 24 548530731 ps
T394 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3352189217 Jul 13 06:18:40 PM PDT 24 Jul 13 06:18:43 PM PDT 24 522705863 ps
T395 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.751706592 Jul 13 06:18:31 PM PDT 24 Jul 13 06:18:35 PM PDT 24 505047195 ps
T396 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2384623486 Jul 13 06:18:59 PM PDT 24 Jul 13 06:19:00 PM PDT 24 461667584 ps
T397 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2827025694 Jul 13 06:18:40 PM PDT 24 Jul 13 06:18:43 PM PDT 24 291563588 ps
T398 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2131002278 Jul 13 06:18:59 PM PDT 24 Jul 13 06:19:01 PM PDT 24 399517036 ps
T399 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.849946818 Jul 13 06:18:29 PM PDT 24 Jul 13 06:18:32 PM PDT 24 437369277 ps
T400 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2127412792 Jul 13 06:18:32 PM PDT 24 Jul 13 06:18:34 PM PDT 24 477587972 ps
T199 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2591767623 Jul 13 06:18:38 PM PDT 24 Jul 13 06:18:54 PM PDT 24 8571437061 ps
T401 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2952817143 Jul 13 06:18:46 PM PDT 24 Jul 13 06:18:47 PM PDT 24 1268572559 ps
T402 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3833954290 Jul 13 06:19:00 PM PDT 24 Jul 13 06:19:01 PM PDT 24 403045741 ps
T403 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.4176797010 Jul 13 06:18:50 PM PDT 24 Jul 13 06:18:53 PM PDT 24 393965719 ps
T404 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1671416962 Jul 13 06:18:38 PM PDT 24 Jul 13 06:18:40 PM PDT 24 406568745 ps
T405 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2737845715 Jul 13 06:18:33 PM PDT 24 Jul 13 06:18:35 PM PDT 24 787883146 ps
T406 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1240061114 Jul 13 06:18:59 PM PDT 24 Jul 13 06:19:01 PM PDT 24 362416493 ps
T407 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3198836454 Jul 13 06:18:46 PM PDT 24 Jul 13 06:18:48 PM PDT 24 1027260892 ps
T408 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2628367632 Jul 13 06:18:34 PM PDT 24 Jul 13 06:18:38 PM PDT 24 1147616876 ps
T409 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3994006309 Jul 13 06:18:50 PM PDT 24 Jul 13 06:18:53 PM PDT 24 317919112 ps
T410 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1247356476 Jul 13 06:18:56 PM PDT 24 Jul 13 06:18:57 PM PDT 24 513068686 ps
T411 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1950121897 Jul 13 06:18:40 PM PDT 24 Jul 13 06:18:44 PM PDT 24 515714375 ps
T412 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2592922382 Jul 13 06:19:00 PM PDT 24 Jul 13 06:19:01 PM PDT 24 327947755 ps
T413 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.57388169 Jul 13 06:18:22 PM PDT 24 Jul 13 06:18:23 PM PDT 24 1042783161 ps
T414 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3614733692 Jul 13 06:18:50 PM PDT 24 Jul 13 06:18:57 PM PDT 24 4799262869 ps
T415 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.4224925588 Jul 13 06:18:31 PM PDT 24 Jul 13 06:18:34 PM PDT 24 453826353 ps
T416 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3246531339 Jul 13 06:18:31 PM PDT 24 Jul 13 06:18:58 PM PDT 24 7138092535 ps
T417 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1642056245 Jul 13 06:18:30 PM PDT 24 Jul 13 06:18:32 PM PDT 24 520492928 ps
T418 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3968696168 Jul 13 06:18:24 PM PDT 24 Jul 13 06:18:27 PM PDT 24 376564962 ps
T419 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2095803577 Jul 13 06:18:32 PM PDT 24 Jul 13 06:18:36 PM PDT 24 992737844 ps
T420 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2436921071 Jul 13 06:18:22 PM PDT 24 Jul 13 06:18:24 PM PDT 24 403918796 ps
T421 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1356790375 Jul 13 06:18:38 PM PDT 24 Jul 13 06:18:42 PM PDT 24 1007773437 ps
T422 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.188131282 Jul 13 06:18:59 PM PDT 24 Jul 13 06:19:00 PM PDT 24 414475894 ps

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.1487180708
Short name T3
Test name
Test status
Simulation time 69867506295 ps
CPU time 239.27 seconds
Started Jul 13 06:38:20 PM PDT 24
Finished Jul 13 06:42:21 PM PDT 24
Peak memory 198600 kb
Host smart-efbc9892-151d-48d5-a932-3cf1f3197399
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487180708 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.1487180708
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.2073735758
Short name T41
Test name
Test status
Simulation time 170542334666 ps
CPU time 194.71 seconds
Started Jul 13 06:38:36 PM PDT 24
Finished Jul 13 06:41:52 PM PDT 24
Peak memory 199396 kb
Host smart-41800490-7354-48a2-8fe2-78710d5675a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073735758 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.2073735758
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.34058103
Short name T37
Test name
Test status
Simulation time 4352289525 ps
CPU time 2.55 seconds
Started Jul 13 06:18:46 PM PDT 24
Finished Jul 13 06:18:48 PM PDT 24
Peak memory 196908 kb
Host smart-d9fda587-9185-4248-ba1d-a3cbf3ab910d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34058103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_
intg_err.34058103
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.1802881450
Short name T55
Test name
Test status
Simulation time 324468490736 ps
CPU time 781.6 seconds
Started Jul 13 06:38:28 PM PDT 24
Finished Jul 13 06:51:32 PM PDT 24
Peak memory 214940 kb
Host smart-951b6be9-98db-48d1-9ec9-6d7d1affc99a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802881450 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.1802881450
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.661253336
Short name T11
Test name
Test status
Simulation time 165001113568 ps
CPU time 203.86 seconds
Started Jul 13 06:38:09 PM PDT 24
Finished Jul 13 06:41:37 PM PDT 24
Peak memory 198272 kb
Host smart-3da74eca-3ac8-4ac9-ba27-de7292102a87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661253336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_al
l.661253336
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.3346239556
Short name T101
Test name
Test status
Simulation time 59699686359 ps
CPU time 434.47 seconds
Started Jul 13 06:38:07 PM PDT 24
Finished Jul 13 06:45:25 PM PDT 24
Peak memory 201340 kb
Host smart-835bc898-a358-4286-873b-b240e34fbd26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346239556 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.3346239556
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.3781894715
Short name T7
Test name
Test status
Simulation time 226481125718 ps
CPU time 832.08 seconds
Started Jul 13 06:38:21 PM PDT 24
Finished Jul 13 06:52:14 PM PDT 24
Peak memory 207284 kb
Host smart-4f18e0c1-bc71-4df9-8b3b-9befa4a1ae47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781894715 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.3781894715
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.2138243438
Short name T111
Test name
Test status
Simulation time 47758089947 ps
CPU time 231.86 seconds
Started Jul 13 06:38:36 PM PDT 24
Finished Jul 13 06:42:29 PM PDT 24
Peak memory 198592 kb
Host smart-737b23df-d5d6-4648-815b-ad1f042da20e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138243438 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.2138243438
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.4153266116
Short name T91
Test name
Test status
Simulation time 468096846637 ps
CPU time 976.29 seconds
Started Jul 13 06:38:24 PM PDT 24
Finished Jul 13 06:54:44 PM PDT 24
Peak memory 209456 kb
Host smart-93b33641-4faf-48cd-ad0a-6aa87e1819fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153266116 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.4153266116
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.1224140412
Short name T73
Test name
Test status
Simulation time 178398875497 ps
CPU time 272.55 seconds
Started Jul 13 06:38:11 PM PDT 24
Finished Jul 13 06:42:48 PM PDT 24
Peak memory 192948 kb
Host smart-dc2a800e-e5b7-4a65-8c2a-1d6c41519ea1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224140412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.1224140412
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.1616784714
Short name T31
Test name
Test status
Simulation time 348780831240 ps
CPU time 694.18 seconds
Started Jul 13 06:38:07 PM PDT 24
Finished Jul 13 06:49:44 PM PDT 24
Peak memory 206376 kb
Host smart-1c5398a0-08cd-47f6-a3a1-6af2729bac9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616784714 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.1616784714
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.2521226610
Short name T130
Test name
Test status
Simulation time 344646439595 ps
CPU time 458.48 seconds
Started Jul 13 06:38:29 PM PDT 24
Finished Jul 13 06:46:10 PM PDT 24
Peak memory 210604 kb
Host smart-42c7c7e0-ad08-4b0f-ab32-5b92567a9c03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521226610 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.2521226610
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.1801075197
Short name T20
Test name
Test status
Simulation time 4775097874 ps
CPU time 1.71 seconds
Started Jul 13 06:37:53 PM PDT 24
Finished Jul 13 06:37:56 PM PDT 24
Peak memory 215712 kb
Host smart-e1333066-afd9-472b-9f43-ec4df7d2053f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801075197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1801075197
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.98714319
Short name T98
Test name
Test status
Simulation time 98441981665 ps
CPU time 759.03 seconds
Started Jul 13 06:38:33 PM PDT 24
Finished Jul 13 06:51:12 PM PDT 24
Peak memory 207080 kb
Host smart-29bc1d8a-56d5-4d97-9159-46d8154d9e7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98714319 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.98714319
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.893206125
Short name T120
Test name
Test status
Simulation time 130821248678 ps
CPU time 265.51 seconds
Started Jul 13 06:38:38 PM PDT 24
Finished Jul 13 06:43:06 PM PDT 24
Peak memory 209248 kb
Host smart-4fdf1651-0abe-4f1a-9e85-951464918eb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893206125 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.893206125
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.141519122
Short name T118
Test name
Test status
Simulation time 48204537860 ps
CPU time 359.29 seconds
Started Jul 13 06:38:36 PM PDT 24
Finished Jul 13 06:44:36 PM PDT 24
Peak memory 207500 kb
Host smart-efe01b0f-5120-4f7e-8050-fe46c07dd414
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141519122 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.141519122
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.4278945899
Short name T92
Test name
Test status
Simulation time 181721411475 ps
CPU time 616.64 seconds
Started Jul 13 06:38:20 PM PDT 24
Finished Jul 13 06:48:37 PM PDT 24
Peak memory 204988 kb
Host smart-95467f1a-1603-4b26-8411-d420319fdb64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278945899 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.4278945899
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.4193947325
Short name T148
Test name
Test status
Simulation time 89317064407 ps
CPU time 378.03 seconds
Started Jul 13 06:38:09 PM PDT 24
Finished Jul 13 06:44:32 PM PDT 24
Peak memory 202552 kb
Host smart-fdd65657-ce38-49a6-8b3c-ef37d9c19f59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193947325 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.4193947325
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.458122876
Short name T30
Test name
Test status
Simulation time 636031891794 ps
CPU time 1007.71 seconds
Started Jul 13 06:38:37 PM PDT 24
Finished Jul 13 06:55:26 PM PDT 24
Peak memory 192464 kb
Host smart-66cd0413-ff40-482a-a071-af360878a3b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458122876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_a
ll.458122876
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1493732761
Short name T128
Test name
Test status
Simulation time 401497526243 ps
CPU time 647.2 seconds
Started Jul 13 06:38:19 PM PDT 24
Finished Jul 13 06:49:07 PM PDT 24
Peak memory 214084 kb
Host smart-e4a77598-3692-4c3a-9791-d63f099df53e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493732761 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1493732761
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.3670682876
Short name T126
Test name
Test status
Simulation time 176848528947 ps
CPU time 13.88 seconds
Started Jul 13 06:38:21 PM PDT 24
Finished Jul 13 06:38:37 PM PDT 24
Peak memory 193016 kb
Host smart-b64044e3-1024-463b-be2a-46e96336326b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670682876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.3670682876
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.994954136
Short name T116
Test name
Test status
Simulation time 308299872676 ps
CPU time 415.17 seconds
Started Jul 13 06:38:29 PM PDT 24
Finished Jul 13 06:45:26 PM PDT 24
Peak memory 198280 kb
Host smart-f6469fbf-8c77-40f3-b39a-866500761ee5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994954136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_a
ll.994954136
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.739597524
Short name T53
Test name
Test status
Simulation time 42770537343 ps
CPU time 466.48 seconds
Started Jul 13 06:38:20 PM PDT 24
Finished Jul 13 06:46:08 PM PDT 24
Peak memory 200888 kb
Host smart-f10fe701-2a1b-4a28-8d49-441642853f0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739597524 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.739597524
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3286544078
Short name T40
Test name
Test status
Simulation time 112330994930 ps
CPU time 426.32 seconds
Started Jul 13 06:38:38 PM PDT 24
Finished Jul 13 06:45:46 PM PDT 24
Peak memory 214040 kb
Host smart-79120ac2-ac5f-4889-9b1e-ce996d3d505e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286544078 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.3286544078
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.150395394
Short name T54
Test name
Test status
Simulation time 16618970772 ps
CPU time 123.39 seconds
Started Jul 13 06:38:23 PM PDT 24
Finished Jul 13 06:40:29 PM PDT 24
Peak memory 198636 kb
Host smart-1983239f-382e-4f3d-86d6-bb078c9071f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150395394 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.150395394
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2051221682
Short name T42
Test name
Test status
Simulation time 154525479489 ps
CPU time 448.11 seconds
Started Jul 13 06:38:09 PM PDT 24
Finished Jul 13 06:45:41 PM PDT 24
Peak memory 203788 kb
Host smart-22da66bd-8b47-4b9e-9e56-0f259ab14cdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051221682 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2051221682
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.3981117437
Short name T52
Test name
Test status
Simulation time 362797108473 ps
CPU time 1015.85 seconds
Started Jul 13 06:38:26 PM PDT 24
Finished Jul 13 06:55:25 PM PDT 24
Peak memory 210616 kb
Host smart-2bac7250-d288-4014-9b7b-86cbe23893b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981117437 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.3981117437
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.911398299
Short name T117
Test name
Test status
Simulation time 48945298599 ps
CPU time 72.15 seconds
Started Jul 13 06:38:09 PM PDT 24
Finished Jul 13 06:39:25 PM PDT 24
Peak memory 193012 kb
Host smart-71e1b1a1-5bfe-433e-a233-85d0b0e6b807
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911398299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_al
l.911398299
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.410487199
Short name T77
Test name
Test status
Simulation time 40297871660 ps
CPU time 26.44 seconds
Started Jul 13 06:38:24 PM PDT 24
Finished Jul 13 06:38:55 PM PDT 24
Peak memory 192728 kb
Host smart-8ab35ed1-77f7-4e90-acf1-f19266f5837e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410487199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_a
ll.410487199
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.3252690060
Short name T158
Test name
Test status
Simulation time 142776280495 ps
CPU time 199.9 seconds
Started Jul 13 06:38:09 PM PDT 24
Finished Jul 13 06:41:34 PM PDT 24
Peak memory 200160 kb
Host smart-e7ba33fb-4cac-41ea-8a69-ade67f232186
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252690060 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.3252690060
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2777284871
Short name T67
Test name
Test status
Simulation time 624499200 ps
CPU time 2.31 seconds
Started Jul 13 06:18:22 PM PDT 24
Finished Jul 13 06:18:25 PM PDT 24
Peak memory 196260 kb
Host smart-f143fb74-676d-439e-96af-dff607572fac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777284871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.2777284871
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.1851432801
Short name T115
Test name
Test status
Simulation time 291332648262 ps
CPU time 41.61 seconds
Started Jul 13 06:38:36 PM PDT 24
Finished Jul 13 06:39:19 PM PDT 24
Peak memory 192852 kb
Host smart-716350e3-d748-49e4-8a4c-b9f539a6c759
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851432801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.1851432801
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.477980585
Short name T137
Test name
Test status
Simulation time 421416149649 ps
CPU time 605.03 seconds
Started Jul 13 06:38:40 PM PDT 24
Finished Jul 13 06:48:47 PM PDT 24
Peak memory 198216 kb
Host smart-95ce24dc-bd59-4a54-9267-340e966c6ad8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477980585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_a
ll.477980585
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.2017262773
Short name T108
Test name
Test status
Simulation time 384436608694 ps
CPU time 476.64 seconds
Started Jul 13 06:38:22 PM PDT 24
Finished Jul 13 06:46:21 PM PDT 24
Peak memory 203156 kb
Host smart-d00761a2-6ad0-413c-a504-8cc03e909ad1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017262773 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.2017262773
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3394619973
Short name T147
Test name
Test status
Simulation time 41745299654 ps
CPU time 52.59 seconds
Started Jul 13 06:38:24 PM PDT 24
Finished Jul 13 06:39:20 PM PDT 24
Peak memory 198612 kb
Host smart-0f927e8e-fb96-4e10-acd6-cbec9febaed9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394619973 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3394619973
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1481724306
Short name T97
Test name
Test status
Simulation time 27798617773 ps
CPU time 217.6 seconds
Started Jul 13 06:38:08 PM PDT 24
Finished Jul 13 06:41:50 PM PDT 24
Peak memory 206844 kb
Host smart-989b15a2-b28b-4405-8bcd-d4684fa96b71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481724306 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1481724306
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.2838798581
Short name T131
Test name
Test status
Simulation time 35429175029 ps
CPU time 12.43 seconds
Started Jul 13 06:38:39 PM PDT 24
Finished Jul 13 06:38:53 PM PDT 24
Peak memory 198220 kb
Host smart-31be0e1b-a5a7-4376-9f15-2da8f195f5d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838798581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.2838798581
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.373936349
Short name T144
Test name
Test status
Simulation time 108932376054 ps
CPU time 158.59 seconds
Started Jul 13 06:38:22 PM PDT 24
Finished Jul 13 06:41:04 PM PDT 24
Peak memory 198268 kb
Host smart-cf0c7c58-bda1-474e-8a26-e2d36851f311
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373936349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a
ll.373936349
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.1034515542
Short name T24
Test name
Test status
Simulation time 131601480780 ps
CPU time 41.45 seconds
Started Jul 13 06:38:25 PM PDT 24
Finished Jul 13 06:39:11 PM PDT 24
Peak memory 192384 kb
Host smart-e9d5003b-1abc-45f1-ac02-c774e376e01d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034515542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.1034515542
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.3368601569
Short name T129
Test name
Test status
Simulation time 14941604579 ps
CPU time 47.13 seconds
Started Jul 13 06:38:39 PM PDT 24
Finished Jul 13 06:39:28 PM PDT 24
Peak memory 198608 kb
Host smart-b6cf0c84-3774-445f-9489-bc42fc3dae82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368601569 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.3368601569
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2217708669
Short name T161
Test name
Test status
Simulation time 195934354635 ps
CPU time 55.03 seconds
Started Jul 13 06:38:23 PM PDT 24
Finished Jul 13 06:39:21 PM PDT 24
Peak memory 192956 kb
Host smart-2a16c105-ccc5-4290-9451-1e1e8f7cb071
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217708669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2217708669
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.2503942906
Short name T140
Test name
Test status
Simulation time 219443580378 ps
CPU time 140.55 seconds
Started Jul 13 06:38:38 PM PDT 24
Finished Jul 13 06:41:00 PM PDT 24
Peak memory 198264 kb
Host smart-74466ddb-ab8c-47a0-b9bc-f7498f8d67ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503942906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.2503942906
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.3084423922
Short name T142
Test name
Test status
Simulation time 128987271846 ps
CPU time 551.07 seconds
Started Jul 13 06:38:39 PM PDT 24
Finished Jul 13 06:47:52 PM PDT 24
Peak memory 204256 kb
Host smart-81628da6-88dc-42e0-b131-17bdd049a15a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084423922 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.3084423922
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.2761952191
Short name T132
Test name
Test status
Simulation time 142706914629 ps
CPU time 50.9 seconds
Started Jul 13 06:38:33 PM PDT 24
Finished Jul 13 06:39:24 PM PDT 24
Peak memory 198224 kb
Host smart-0b30aebd-67a6-42ee-8097-31f5d487555b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761952191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.2761952191
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3276596669
Short name T146
Test name
Test status
Simulation time 21473430103 ps
CPU time 34.07 seconds
Started Jul 13 06:38:21 PM PDT 24
Finished Jul 13 06:38:57 PM PDT 24
Peak memory 192036 kb
Host smart-8a3bb523-6d08-4dc2-b336-c0ebe7fb99d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276596669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3276596669
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3265697123
Short name T29
Test name
Test status
Simulation time 602944728824 ps
CPU time 828.16 seconds
Started Jul 13 06:38:26 PM PDT 24
Finished Jul 13 06:52:17 PM PDT 24
Peak memory 192948 kb
Host smart-4435a95e-1a58-4a1b-be2c-96ea4edaeb78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265697123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3265697123
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3551632890
Short name T33
Test name
Test status
Simulation time 60038180938 ps
CPU time 274.64 seconds
Started Jul 13 06:38:18 PM PDT 24
Finished Jul 13 06:42:54 PM PDT 24
Peak memory 207552 kb
Host smart-26985f45-3fad-4369-9f4e-5bc132a1f830
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551632890 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3551632890
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.618743535
Short name T110
Test name
Test status
Simulation time 192032166645 ps
CPU time 29.45 seconds
Started Jul 13 06:38:24 PM PDT 24
Finished Jul 13 06:38:58 PM PDT 24
Peak memory 198404 kb
Host smart-9b91c08b-ffac-4ca7-97af-95823ae3d400
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618743535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.618743535
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3622487683
Short name T133
Test name
Test status
Simulation time 225771101405 ps
CPU time 512.07 seconds
Started Jul 13 06:38:21 PM PDT 24
Finished Jul 13 06:46:54 PM PDT 24
Peak memory 203612 kb
Host smart-326006db-06d5-4a8b-9c42-8e0edaa323c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622487683 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.3622487683
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.3596165428
Short name T95
Test name
Test status
Simulation time 127205227466 ps
CPU time 960.95 seconds
Started Jul 13 06:38:25 PM PDT 24
Finished Jul 13 06:54:30 PM PDT 24
Peak memory 210556 kb
Host smart-ac9c241c-2057-4b67-bf4f-f89f2616e250
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596165428 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.3596165428
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.3543716137
Short name T162
Test name
Test status
Simulation time 341915803710 ps
CPU time 96.97 seconds
Started Jul 13 06:38:35 PM PDT 24
Finished Jul 13 06:40:12 PM PDT 24
Peak memory 192916 kb
Host smart-16e2c45d-fbbe-45c5-9f67-b3fb1819af24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543716137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.3543716137
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.4237849008
Short name T107
Test name
Test status
Simulation time 197671541740 ps
CPU time 42.85 seconds
Started Jul 13 06:38:41 PM PDT 24
Finished Jul 13 06:39:25 PM PDT 24
Peak memory 192636 kb
Host smart-9b9d23ad-a7cd-405a-808c-4e34f20f5893
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237849008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.4237849008
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.792543115
Short name T123
Test name
Test status
Simulation time 177199354637 ps
CPU time 287.5 seconds
Started Jul 13 06:38:18 PM PDT 24
Finished Jul 13 06:43:07 PM PDT 24
Peak memory 193020 kb
Host smart-950962af-af64-4a8c-8d16-dd8e2415192d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792543115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.792543115
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.370209443
Short name T164
Test name
Test status
Simulation time 135642157462 ps
CPU time 197.04 seconds
Started Jul 13 06:38:37 PM PDT 24
Finished Jul 13 06:41:55 PM PDT 24
Peak memory 198184 kb
Host smart-af3150b0-7001-4468-be8a-063402551b20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370209443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_a
ll.370209443
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3205553621
Short name T57
Test name
Test status
Simulation time 422817023 ps
CPU time 0.76 seconds
Started Jul 13 06:18:23 PM PDT 24
Finished Jul 13 06:18:25 PM PDT 24
Peak memory 193320 kb
Host smart-511816e7-6ea6-4be3-97d7-02de8df5e9c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205553621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3205553621
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.2084776063
Short name T35
Test name
Test status
Simulation time 62539900169 ps
CPU time 25.15 seconds
Started Jul 13 06:38:11 PM PDT 24
Finished Jul 13 06:38:40 PM PDT 24
Peak memory 193016 kb
Host smart-8d7455df-0d75-49b4-8dc8-1d753459ad6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084776063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.2084776063
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.4018191013
Short name T45
Test name
Test status
Simulation time 344461334635 ps
CPU time 213.5 seconds
Started Jul 13 06:38:21 PM PDT 24
Finished Jul 13 06:41:55 PM PDT 24
Peak memory 191928 kb
Host smart-c9c4eea6-87c6-45f7-87c9-c5521d144802
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018191013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.4018191013
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3973873521
Short name T136
Test name
Test status
Simulation time 255474302779 ps
CPU time 86.7 seconds
Started Jul 13 06:38:39 PM PDT 24
Finished Jul 13 06:40:08 PM PDT 24
Peak memory 198136 kb
Host smart-f8a09fbc-b2da-42b9-ba4c-d9d246bdb49c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973873521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3973873521
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.1941276998
Short name T12
Test name
Test status
Simulation time 481883415083 ps
CPU time 142.03 seconds
Started Jul 13 06:38:08 PM PDT 24
Finished Jul 13 06:40:34 PM PDT 24
Peak memory 192668 kb
Host smart-d6a87f3e-d9de-4ee7-b3ca-f325e5f54966
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941276998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.1941276998
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.4171964301
Short name T141
Test name
Test status
Simulation time 123136825704 ps
CPU time 43.58 seconds
Started Jul 13 06:37:54 PM PDT 24
Finished Jul 13 06:38:38 PM PDT 24
Peak memory 192148 kb
Host smart-ddb782ac-47ac-4427-8d58-ddfb0d928930
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171964301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.4171964301
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2025102430
Short name T151
Test name
Test status
Simulation time 73701415513 ps
CPU time 54.42 seconds
Started Jul 13 06:38:19 PM PDT 24
Finished Jul 13 06:39:15 PM PDT 24
Peak memory 198220 kb
Host smart-7ad3cbda-b09d-4a7c-a814-2764b714dbe9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025102430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2025102430
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.932716745
Short name T138
Test name
Test status
Simulation time 309449634756 ps
CPU time 201.6 seconds
Started Jul 13 06:38:23 PM PDT 24
Finished Jul 13 06:41:48 PM PDT 24
Peak memory 193020 kb
Host smart-6d40364f-61da-43f6-bed8-9d2d1ede2db3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932716745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_a
ll.932716745
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.97577890
Short name T171
Test name
Test status
Simulation time 310314697039 ps
CPU time 503.02 seconds
Started Jul 13 06:38:23 PM PDT 24
Finished Jul 13 06:46:49 PM PDT 24
Peak memory 192496 kb
Host smart-2ec05130-f279-4052-9f69-02806f798674
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97577890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_al
l.97577890
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.132202654
Short name T100
Test name
Test status
Simulation time 12418254040 ps
CPU time 87.98 seconds
Started Jul 13 06:38:39 PM PDT 24
Finished Jul 13 06:40:09 PM PDT 24
Peak memory 198552 kb
Host smart-716d7a02-d4c5-4e34-92ca-5c8f9c0c69ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132202654 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.132202654
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.869378477
Short name T34
Test name
Test status
Simulation time 36221016824 ps
CPU time 392.64 seconds
Started Jul 13 06:38:38 PM PDT 24
Finished Jul 13 06:45:12 PM PDT 24
Peak memory 214520 kb
Host smart-364d3c81-26fc-4085-a149-42b448915538
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869378477 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.869378477
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3392958460
Short name T96
Test name
Test status
Simulation time 39455879075 ps
CPU time 303.68 seconds
Started Jul 13 06:38:10 PM PDT 24
Finished Jul 13 06:43:18 PM PDT 24
Peak memory 198620 kb
Host smart-23f2ec49-c84c-49ac-b9cf-0bc7dfa79f71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392958460 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.3392958460
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.1504748696
Short name T153
Test name
Test status
Simulation time 557852828573 ps
CPU time 195.93 seconds
Started Jul 13 06:38:11 PM PDT 24
Finished Jul 13 06:41:31 PM PDT 24
Peak memory 198192 kb
Host smart-fa84a966-55a8-444c-9b14-99d336301b4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504748696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.1504748696
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.2110424371
Short name T18
Test name
Test status
Simulation time 150803013276 ps
CPU time 206.7 seconds
Started Jul 13 06:38:19 PM PDT 24
Finished Jul 13 06:41:47 PM PDT 24
Peak memory 191924 kb
Host smart-759f9491-0b86-445e-b132-ef8180b2ff1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110424371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.2110424371
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_jump.430836770
Short name T163
Test name
Test status
Simulation time 465920841 ps
CPU time 0.77 seconds
Started Jul 13 06:38:23 PM PDT 24
Finished Jul 13 06:38:28 PM PDT 24
Peak memory 196624 kb
Host smart-d0461114-6868-47de-af1f-0b5dfad9e87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430836770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.430836770
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.92604784
Short name T79
Test name
Test status
Simulation time 481383876 ps
CPU time 0.9 seconds
Started Jul 13 06:38:24 PM PDT 24
Finished Jul 13 06:38:29 PM PDT 24
Peak memory 196720 kb
Host smart-e03eabfb-94a2-4766-adc1-38dbcc37f0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92604784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.92604784
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.3535965841
Short name T149
Test name
Test status
Simulation time 98852841907 ps
CPU time 128.8 seconds
Started Jul 13 06:38:23 PM PDT 24
Finished Jul 13 06:40:36 PM PDT 24
Peak memory 198276 kb
Host smart-de7bad54-02c6-4540-a2a3-e4c45634d5b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535965841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.3535965841
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.493815700
Short name T182
Test name
Test status
Simulation time 27163135892 ps
CPU time 225.15 seconds
Started Jul 13 06:38:22 PM PDT 24
Finished Jul 13 06:42:09 PM PDT 24
Peak memory 199088 kb
Host smart-b9905ed7-683c-453a-9ed3-cb6462975f9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493815700 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.493815700
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3774964006
Short name T139
Test name
Test status
Simulation time 409456371 ps
CPU time 0.74 seconds
Started Jul 13 06:38:33 PM PDT 24
Finished Jul 13 06:38:35 PM PDT 24
Peak memory 196708 kb
Host smart-fb810b52-c239-4e4b-a0ea-f69d3fa0d9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774964006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3774964006
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.120103356
Short name T119
Test name
Test status
Simulation time 519247065 ps
CPU time 1.33 seconds
Started Jul 13 06:38:29 PM PDT 24
Finished Jul 13 06:38:32 PM PDT 24
Peak memory 196760 kb
Host smart-a4b74bde-27e4-48ef-9b44-c8c4036bb35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120103356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.120103356
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.3131530413
Short name T99
Test name
Test status
Simulation time 169786316682 ps
CPU time 349.98 seconds
Started Jul 13 06:38:37 PM PDT 24
Finished Jul 13 06:44:28 PM PDT 24
Peak memory 210124 kb
Host smart-9ee603d1-0581-4427-9663-b36c572f2041
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131530413 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.3131530413
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.1858107509
Short name T113
Test name
Test status
Simulation time 386392459 ps
CPU time 0.92 seconds
Started Jul 13 06:38:30 PM PDT 24
Finished Jul 13 06:38:33 PM PDT 24
Peak memory 196660 kb
Host smart-df34754c-f06e-4ca8-a287-5ece9043466d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858107509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1858107509
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.290838272
Short name T106
Test name
Test status
Simulation time 440645564 ps
CPU time 0.69 seconds
Started Jul 13 06:37:52 PM PDT 24
Finished Jul 13 06:37:53 PM PDT 24
Peak memory 196788 kb
Host smart-22826ef4-c97e-4c52-8806-957d5c31874d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290838272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.290838272
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1216897318
Short name T127
Test name
Test status
Simulation time 442936822 ps
CPU time 1.31 seconds
Started Jul 13 06:38:10 PM PDT 24
Finished Jul 13 06:38:16 PM PDT 24
Peak memory 196760 kb
Host smart-6c5acd4f-c7bc-43f0-9c00-d5afdc360c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216897318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1216897318
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.787857216
Short name T23
Test name
Test status
Simulation time 445648942 ps
CPU time 0.88 seconds
Started Jul 13 06:38:28 PM PDT 24
Finished Jul 13 06:38:32 PM PDT 24
Peak memory 196580 kb
Host smart-65bdd3d7-d089-434a-9102-545a76639973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787857216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.787857216
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3141522840
Short name T177
Test name
Test status
Simulation time 471891803472 ps
CPU time 666.74 seconds
Started Jul 13 06:38:08 PM PDT 24
Finished Jul 13 06:49:18 PM PDT 24
Peak memory 192672 kb
Host smart-fc2b6993-bf96-4487-bcc9-9a8b2529d1c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141522840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3141522840
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_jump.3027768110
Short name T109
Test name
Test status
Simulation time 503795137 ps
CPU time 0.86 seconds
Started Jul 13 06:38:09 PM PDT 24
Finished Jul 13 06:38:14 PM PDT 24
Peak memory 196664 kb
Host smart-ea73e31f-c130-4d6e-a8fd-5543e36c617c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027768110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.3027768110
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.1219051670
Short name T124
Test name
Test status
Simulation time 199334029458 ps
CPU time 155.43 seconds
Started Jul 13 06:38:37 PM PDT 24
Finished Jul 13 06:41:14 PM PDT 24
Peak memory 192428 kb
Host smart-7a34ba7c-9520-4f2e-9d39-3051518ec2e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219051670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.1219051670
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_jump.2700241799
Short name T112
Test name
Test status
Simulation time 617446747 ps
CPU time 0.76 seconds
Started Jul 13 06:38:07 PM PDT 24
Finished Jul 13 06:38:12 PM PDT 24
Peak memory 196664 kb
Host smart-d1c60c93-660b-47d7-9d9c-9205c582b6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700241799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2700241799
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.1886547512
Short name T94
Test name
Test status
Simulation time 123191073371 ps
CPU time 359.85 seconds
Started Jul 13 06:38:24 PM PDT 24
Finished Jul 13 06:44:28 PM PDT 24
Peak memory 209744 kb
Host smart-f2e4c447-97c0-4b85-bf0f-81e55f712293
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886547512 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.1886547512
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.1298026195
Short name T145
Test name
Test status
Simulation time 467065452 ps
CPU time 0.71 seconds
Started Jul 13 06:38:23 PM PDT 24
Finished Jul 13 06:38:28 PM PDT 24
Peak memory 196708 kb
Host smart-7ceca0e4-3113-420a-8afd-a1369a299c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298026195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.1298026195
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2757954911
Short name T168
Test name
Test status
Simulation time 199954951182 ps
CPU time 897.17 seconds
Started Jul 13 06:38:29 PM PDT 24
Finished Jul 13 06:53:28 PM PDT 24
Peak memory 214912 kb
Host smart-b92c9aea-722b-4850-b91a-ffd2c0bf9742
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757954911 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2757954911
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.3650008825
Short name T150
Test name
Test status
Simulation time 485153539 ps
CPU time 1.29 seconds
Started Jul 13 06:38:31 PM PDT 24
Finished Jul 13 06:38:34 PM PDT 24
Peak memory 196676 kb
Host smart-1acf024b-a825-49a2-9fb3-f95d6a641bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650008825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3650008825
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.1639243920
Short name T183
Test name
Test status
Simulation time 351297794326 ps
CPU time 230.12 seconds
Started Jul 13 06:38:36 PM PDT 24
Finished Jul 13 06:42:27 PM PDT 24
Peak memory 198188 kb
Host smart-c118928a-fc50-49cc-88e5-736c89529c6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639243920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.1639243920
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_jump.521540286
Short name T159
Test name
Test status
Simulation time 359791044 ps
CPU time 0.74 seconds
Started Jul 13 06:38:39 PM PDT 24
Finished Jul 13 06:38:42 PM PDT 24
Peak memory 196572 kb
Host smart-eea12be4-6b29-425b-be0a-0806ff645733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521540286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.521540286
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_jump.1052230885
Short name T114
Test name
Test status
Simulation time 426042133 ps
CPU time 1.01 seconds
Started Jul 13 06:38:08 PM PDT 24
Finished Jul 13 06:38:13 PM PDT 24
Peak memory 196740 kb
Host smart-6c32e788-2a4d-44de-a2d8-a860db9cdf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052230885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1052230885
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3032520862
Short name T105
Test name
Test status
Simulation time 96631047630 ps
CPU time 72.2 seconds
Started Jul 13 06:38:24 PM PDT 24
Finished Jul 13 06:39:40 PM PDT 24
Peak memory 191944 kb
Host smart-167be3f9-b9aa-4d3c-8691-cce65b09781f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032520862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3032520862
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_jump.4138255173
Short name T121
Test name
Test status
Simulation time 561668773 ps
CPU time 0.63 seconds
Started Jul 13 06:38:23 PM PDT 24
Finished Jul 13 06:38:27 PM PDT 24
Peak memory 196532 kb
Host smart-7e353e7a-8d4e-4963-9d6d-8d2cb007bb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138255173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.4138255173
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2088150585
Short name T143
Test name
Test status
Simulation time 422590168 ps
CPU time 0.91 seconds
Started Jul 13 06:38:20 PM PDT 24
Finished Jul 13 06:38:22 PM PDT 24
Peak memory 196708 kb
Host smart-f729c574-abc7-4b6a-9ed0-5f63a692a325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088150585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2088150585
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.3215407431
Short name T125
Test name
Test status
Simulation time 422215035 ps
CPU time 0.72 seconds
Started Jul 13 06:38:45 PM PDT 24
Finished Jul 13 06:38:46 PM PDT 24
Peak memory 196724 kb
Host smart-e039efcd-f043-41c9-bec9-28ef6afd882d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215407431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3215407431
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.3904895096
Short name T173
Test name
Test status
Simulation time 372146922780 ps
CPU time 120.02 seconds
Started Jul 13 06:38:40 PM PDT 24
Finished Jul 13 06:40:42 PM PDT 24
Peak memory 192964 kb
Host smart-cdc98201-9084-4dc1-b998-a75ffe499a1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904895096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.3904895096
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_jump.93272071
Short name T47
Test name
Test status
Simulation time 564036602 ps
CPU time 1.37 seconds
Started Jul 13 06:38:08 PM PDT 24
Finished Jul 13 06:38:13 PM PDT 24
Peak memory 196792 kb
Host smart-9d79c4d3-993b-4bed-92b3-dc4b01fd7dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93272071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.93272071
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.1894278140
Short name T93
Test name
Test status
Simulation time 126983013450 ps
CPU time 217.81 seconds
Started Jul 13 06:37:52 PM PDT 24
Finished Jul 13 06:41:30 PM PDT 24
Peak memory 198560 kb
Host smart-64c34f16-beea-49c4-b8ac-31a9bd24a206
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894278140 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.1894278140
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.3455651464
Short name T157
Test name
Test status
Simulation time 503597099 ps
CPU time 1.39 seconds
Started Jul 13 06:38:19 PM PDT 24
Finished Jul 13 06:38:22 PM PDT 24
Peak memory 196768 kb
Host smart-d8ed9523-7e51-4d3c-87f3-342022222998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455651464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3455651464
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.2639804553
Short name T167
Test name
Test status
Simulation time 188551007997 ps
CPU time 247.41 seconds
Started Jul 13 06:38:25 PM PDT 24
Finished Jul 13 06:42:36 PM PDT 24
Peak memory 191964 kb
Host smart-5a0c92e0-1720-4112-b094-4a6abdf43657
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639804553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.2639804553
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.4210925234
Short name T172
Test name
Test status
Simulation time 44009908386 ps
CPU time 292.81 seconds
Started Jul 13 06:38:23 PM PDT 24
Finished Jul 13 06:43:19 PM PDT 24
Peak memory 206712 kb
Host smart-e499ccdb-49d6-4a4b-88e9-67095ccbf45d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210925234 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.4210925234
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.1140473793
Short name T156
Test name
Test status
Simulation time 384027390 ps
CPU time 1.11 seconds
Started Jul 13 06:38:21 PM PDT 24
Finished Jul 13 06:38:23 PM PDT 24
Peak memory 196656 kb
Host smart-77860df4-a3a4-4421-bd0c-87684d674a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140473793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1140473793
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.850338259
Short name T48
Test name
Test status
Simulation time 493109316 ps
CPU time 0.76 seconds
Started Jul 13 06:38:23 PM PDT 24
Finished Jul 13 06:38:28 PM PDT 24
Peak memory 196516 kb
Host smart-62568434-df1d-4693-9f9a-6f68518da547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850338259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.850338259
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.4190377908
Short name T176
Test name
Test status
Simulation time 17711619980 ps
CPU time 146.89 seconds
Started Jul 13 06:38:36 PM PDT 24
Finished Jul 13 06:41:05 PM PDT 24
Peak memory 206712 kb
Host smart-4ae3187f-dc7a-4848-842e-7dc3c289ecb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190377908 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.4190377908
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.2781808065
Short name T122
Test name
Test status
Simulation time 205114890852 ps
CPU time 296.83 seconds
Started Jul 13 06:38:45 PM PDT 24
Finished Jul 13 06:43:42 PM PDT 24
Peak memory 198276 kb
Host smart-e8bf429f-33e1-47aa-bca7-4661859c7beb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781808065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.2781808065
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_jump.2411924231
Short name T135
Test name
Test status
Simulation time 357536118 ps
CPU time 0.93 seconds
Started Jul 13 06:38:07 PM PDT 24
Finished Jul 13 06:38:09 PM PDT 24
Peak memory 196656 kb
Host smart-ee614b0a-e193-4f3f-9b99-a1bdecde36ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411924231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.2411924231
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.113525281
Short name T160
Test name
Test status
Simulation time 163923698406 ps
CPU time 30.82 seconds
Started Jul 13 06:38:20 PM PDT 24
Finished Jul 13 06:38:51 PM PDT 24
Peak memory 192852 kb
Host smart-7757a757-1aea-40d6-8f4a-b51b19459b74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113525281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_a
ll.113525281
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_jump.3087645834
Short name T152
Test name
Test status
Simulation time 429299832 ps
CPU time 0.64 seconds
Started Jul 13 06:38:21 PM PDT 24
Finished Jul 13 06:38:23 PM PDT 24
Peak memory 196696 kb
Host smart-b8980a4f-95ce-4453-a78e-d6db6ebe944a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087645834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3087645834
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.567844865
Short name T175
Test name
Test status
Simulation time 133567401392 ps
CPU time 190.98 seconds
Started Jul 13 06:38:26 PM PDT 24
Finished Jul 13 06:41:40 PM PDT 24
Peak memory 191912 kb
Host smart-a7e046f7-f40e-4c9b-9352-a96810fcf6de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567844865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_a
ll.567844865
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.648456458
Short name T181
Test name
Test status
Simulation time 149437039298 ps
CPU time 52.25 seconds
Started Jul 13 06:38:22 PM PDT 24
Finished Jul 13 06:39:16 PM PDT 24
Peak memory 191832 kb
Host smart-9ef3139a-7216-4448-9713-ef143322c111
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648456458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_a
ll.648456458
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1984510919
Short name T154
Test name
Test status
Simulation time 519929885 ps
CPU time 1.36 seconds
Started Jul 13 06:38:22 PM PDT 24
Finished Jul 13 06:38:27 PM PDT 24
Peak memory 196696 kb
Host smart-ca56ffa7-a3c2-40fd-b4d8-b586ada921e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984510919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1984510919
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1977199749
Short name T178
Test name
Test status
Simulation time 523582808 ps
CPU time 0.95 seconds
Started Jul 13 06:38:35 PM PDT 24
Finished Jul 13 06:38:37 PM PDT 24
Peak memory 196636 kb
Host smart-ab67b2d2-ddc6-46d3-9423-164dbefc5d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977199749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1977199749
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1313198661
Short name T134
Test name
Test status
Simulation time 193211947737 ps
CPU time 284.04 seconds
Started Jul 13 06:38:36 PM PDT 24
Finished Jul 13 06:43:21 PM PDT 24
Peak memory 198272 kb
Host smart-71c57316-a362-470a-9119-4ae237725963
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313198661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1313198661
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_jump.547729385
Short name T169
Test name
Test status
Simulation time 418800619 ps
CPU time 1.08 seconds
Started Jul 13 06:38:35 PM PDT 24
Finished Jul 13 06:38:36 PM PDT 24
Peak memory 196532 kb
Host smart-17f4920b-aa90-4413-a47f-efc90c8ee4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547729385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.547729385
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.1475443547
Short name T184
Test name
Test status
Simulation time 6505325600 ps
CPU time 1.45 seconds
Started Jul 13 06:38:09 PM PDT 24
Finished Jul 13 06:38:15 PM PDT 24
Peak memory 191916 kb
Host smart-44e5c25c-3e3d-4b6f-96fc-0207ab419646
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475443547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.1475443547
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2672593238
Short name T200
Test name
Test status
Simulation time 4286565031 ps
CPU time 3.59 seconds
Started Jul 13 06:18:32 PM PDT 24
Finished Jul 13 06:18:37 PM PDT 24
Peak memory 197924 kb
Host smart-73edcdcb-4e21-46d4-8a68-1eb835291855
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672593238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.2672593238
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/13.aon_timer_jump.3596607211
Short name T186
Test name
Test status
Simulation time 565708095 ps
CPU time 1.26 seconds
Started Jul 13 06:38:21 PM PDT 24
Finished Jul 13 06:38:24 PM PDT 24
Peak memory 195364 kb
Host smart-4a632c72-6615-41ac-afc8-3cfc56123ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596607211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3596607211
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.4287193271
Short name T46
Test name
Test status
Simulation time 446775126 ps
CPU time 1.24 seconds
Started Jul 13 06:38:18 PM PDT 24
Finished Jul 13 06:38:21 PM PDT 24
Peak memory 196608 kb
Host smart-42cf0b7a-9776-459d-bed8-fe2fd4f2fb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287193271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.4287193271
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1725398691
Short name T103
Test name
Test status
Simulation time 532825766 ps
CPU time 1.4 seconds
Started Jul 13 06:38:09 PM PDT 24
Finished Jul 13 06:38:15 PM PDT 24
Peak memory 196668 kb
Host smart-9e3d84c3-ef32-42c1-973a-cdbe52fb0c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725398691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1725398691
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.3632550864
Short name T5
Test name
Test status
Simulation time 206670237062 ps
CPU time 518.3 seconds
Started Jul 13 06:38:11 PM PDT 24
Finished Jul 13 06:46:53 PM PDT 24
Peak memory 212524 kb
Host smart-4de7d34d-2256-455e-b715-b55fabd5eeee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632550864 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.3632550864
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.2295024287
Short name T179
Test name
Test status
Simulation time 292239276017 ps
CPU time 435.83 seconds
Started Jul 13 06:38:24 PM PDT 24
Finished Jul 13 06:45:43 PM PDT 24
Peak memory 191948 kb
Host smart-158a0869-68f1-428d-8c00-1d17290e6854
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295024287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.2295024287
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2781770631
Short name T155
Test name
Test status
Simulation time 402385665 ps
CPU time 0.77 seconds
Started Jul 13 06:38:09 PM PDT 24
Finished Jul 13 06:38:14 PM PDT 24
Peak memory 196712 kb
Host smart-18acf3b3-1319-439f-b836-39694c8f789a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781770631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2781770631
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.2169877519
Short name T14
Test name
Test status
Simulation time 86872058222 ps
CPU time 175.11 seconds
Started Jul 13 06:38:30 PM PDT 24
Finished Jul 13 06:41:27 PM PDT 24
Peak memory 207972 kb
Host smart-c5e2e710-e48e-41eb-ae3a-72fcf90851d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169877519 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.2169877519
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.770339219
Short name T187
Test name
Test status
Simulation time 365492763 ps
CPU time 1.2 seconds
Started Jul 13 06:38:36 PM PDT 24
Finished Jul 13 06:38:39 PM PDT 24
Peak memory 196620 kb
Host smart-30bb5e56-f5f2-468b-a3c9-f2e9061e4ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770339219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.770339219
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.1230184248
Short name T76
Test name
Test status
Simulation time 486197951 ps
CPU time 0.96 seconds
Started Jul 13 06:38:35 PM PDT 24
Finished Jul 13 06:38:37 PM PDT 24
Peak memory 196756 kb
Host smart-c21ed0d8-9bc0-4f80-bfb5-c45a952300dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230184248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1230184248
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.124487223
Short name T185
Test name
Test status
Simulation time 527235302 ps
CPU time 0.81 seconds
Started Jul 13 06:38:08 PM PDT 24
Finished Jul 13 06:38:12 PM PDT 24
Peak memory 196736 kb
Host smart-e576b1d6-fb4e-48d1-b1b1-2d11b9931491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124487223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.124487223
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.4247176937
Short name T180
Test name
Test status
Simulation time 428082087 ps
CPU time 0.85 seconds
Started Jul 13 06:38:23 PM PDT 24
Finished Jul 13 06:38:28 PM PDT 24
Peak memory 196680 kb
Host smart-18b90322-9f93-4f82-ac87-d2445992138b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247176937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.4247176937
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.3941026988
Short name T170
Test name
Test status
Simulation time 22442742648 ps
CPU time 128.98 seconds
Started Jul 13 06:38:25 PM PDT 24
Finished Jul 13 06:40:38 PM PDT 24
Peak memory 206688 kb
Host smart-ea23a811-e480-4f20-88b5-3c38ad98acd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941026988 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.3941026988
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.2904121832
Short name T78
Test name
Test status
Simulation time 66405691856 ps
CPU time 128.08 seconds
Started Jul 13 06:38:22 PM PDT 24
Finished Jul 13 06:40:32 PM PDT 24
Peak memory 206824 kb
Host smart-cf512e21-dd34-4b74-aa04-19ce8132ad23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904121832 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.2904121832
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.1480872397
Short name T104
Test name
Test status
Simulation time 455332477 ps
CPU time 0.71 seconds
Started Jul 13 06:38:22 PM PDT 24
Finished Jul 13 06:38:24 PM PDT 24
Peak memory 196732 kb
Host smart-d9b6edd9-0e39-439b-a3e8-95a7f83d2752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480872397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.1480872397
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.395613562
Short name T189
Test name
Test status
Simulation time 564197707 ps
CPU time 0.89 seconds
Started Jul 13 06:38:22 PM PDT 24
Finished Jul 13 06:38:25 PM PDT 24
Peak memory 196568 kb
Host smart-5aa95232-8e0e-46c9-bf6b-b33fb43d7b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395613562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.395613562
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.1311221419
Short name T166
Test name
Test status
Simulation time 64029771149 ps
CPU time 366.31 seconds
Started Jul 13 06:38:28 PM PDT 24
Finished Jul 13 06:44:37 PM PDT 24
Peak memory 206804 kb
Host smart-248f57d4-cdb5-4d5b-9702-a91698320eba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311221419 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.1311221419
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.3501436278
Short name T25
Test name
Test status
Simulation time 628717938 ps
CPU time 1.1 seconds
Started Jul 13 06:38:33 PM PDT 24
Finished Jul 13 06:38:35 PM PDT 24
Peak memory 196648 kb
Host smart-96a72330-ba52-4512-a183-e0f668b201e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501436278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3501436278
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.1955841537
Short name T75
Test name
Test status
Simulation time 535604528 ps
CPU time 0.62 seconds
Started Jul 13 06:38:38 PM PDT 24
Finished Jul 13 06:38:41 PM PDT 24
Peak memory 196636 kb
Host smart-52ed5d46-b8ef-4d77-a749-7e4bb8db8e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955841537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1955841537
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3867758815
Short name T9
Test name
Test status
Simulation time 422800115 ps
CPU time 0.75 seconds
Started Jul 13 06:38:39 PM PDT 24
Finished Jul 13 06:38:42 PM PDT 24
Peak memory 196552 kb
Host smart-6f1cd3a2-b8ab-48cb-8a59-ad94f955a08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867758815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3867758815
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.787239296
Short name T32
Test name
Test status
Simulation time 17275051745 ps
CPU time 25.26 seconds
Started Jul 13 06:38:08 PM PDT 24
Finished Jul 13 06:38:37 PM PDT 24
Peak memory 192524 kb
Host smart-dbf36779-5c51-481c-9df4-740debc30735
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787239296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_al
l.787239296
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_jump.223673499
Short name T193
Test name
Test status
Simulation time 591261156 ps
CPU time 0.78 seconds
Started Jul 13 06:38:07 PM PDT 24
Finished Jul 13 06:38:11 PM PDT 24
Peak memory 196636 kb
Host smart-1f27730f-5715-43ad-a072-3d8c79430295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223673499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.223673499
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.4197469180
Short name T319
Test name
Test status
Simulation time 705044397 ps
CPU time 1.46 seconds
Started Jul 13 06:18:23 PM PDT 24
Finished Jul 13 06:18:25 PM PDT 24
Peak memory 183580 kb
Host smart-650cac9b-822b-4e0e-87d7-f65d994bddd1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197469180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.4197469180
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1782573110
Short name T378
Test name
Test status
Simulation time 898948817 ps
CPU time 0.66 seconds
Started Jul 13 06:18:25 PM PDT 24
Finished Jul 13 06:18:27 PM PDT 24
Peak memory 193008 kb
Host smart-8d93851e-1d34-4916-9cbd-35c2c71fb3a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782573110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.1782573110
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.66216300
Short name T333
Test name
Test status
Simulation time 397432292 ps
CPU time 1.23 seconds
Started Jul 13 06:18:24 PM PDT 24
Finished Jul 13 06:18:27 PM PDT 24
Peak memory 196408 kb
Host smart-ec4a1291-99e0-44dc-b341-81b6dea7e6b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66216300 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.66216300
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2539565873
Short name T58
Test name
Test status
Simulation time 392084270 ps
CPU time 0.67 seconds
Started Jul 13 06:18:22 PM PDT 24
Finished Jul 13 06:18:24 PM PDT 24
Peak memory 192060 kb
Host smart-8f6a63de-4d71-456c-b30e-0990864203fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539565873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2539565873
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2598726450
Short name T294
Test name
Test status
Simulation time 397803560 ps
CPU time 0.6 seconds
Started Jul 13 06:18:24 PM PDT 24
Finished Jul 13 06:18:26 PM PDT 24
Peak memory 183680 kb
Host smart-461c9364-fe94-4060-addc-2742605577e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598726450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.2598726450
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2436921071
Short name T420
Test name
Test status
Simulation time 403918796 ps
CPU time 0.66 seconds
Started Jul 13 06:18:22 PM PDT 24
Finished Jul 13 06:18:24 PM PDT 24
Peak memory 183668 kb
Host smart-23466572-b429-4823-bcd5-a47353aa211e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436921071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2436921071
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.517972690
Short name T330
Test name
Test status
Simulation time 289037445 ps
CPU time 0.91 seconds
Started Jul 13 06:18:24 PM PDT 24
Finished Jul 13 06:18:27 PM PDT 24
Peak memory 183708 kb
Host smart-31657946-a9dd-46eb-a994-906b74da81f5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517972690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_wa
lk.517972690
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.692295738
Short name T362
Test name
Test status
Simulation time 2510390046 ps
CPU time 3.17 seconds
Started Jul 13 06:18:26 PM PDT 24
Finished Jul 13 06:18:30 PM PDT 24
Peak memory 193868 kb
Host smart-f9c09205-3168-416b-934e-5a49b7316bef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692295738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.692295738
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1550061399
Short name T291
Test name
Test status
Simulation time 717755052 ps
CPU time 2.14 seconds
Started Jul 13 06:18:23 PM PDT 24
Finished Jul 13 06:18:26 PM PDT 24
Peak memory 198628 kb
Host smart-7c39e757-1e85-4532-9adf-84dc30b48b28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550061399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1550061399
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.132796930
Short name T377
Test name
Test status
Simulation time 8071280662 ps
CPU time 11.8 seconds
Started Jul 13 06:18:25 PM PDT 24
Finished Jul 13 06:18:38 PM PDT 24
Peak memory 198196 kb
Host smart-2bdd0151-93f4-40a8-b1ba-72db6e748ad9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132796930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_
intg_err.132796930
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.716171606
Short name T303
Test name
Test status
Simulation time 603974355 ps
CPU time 0.92 seconds
Started Jul 13 06:18:26 PM PDT 24
Finished Jul 13 06:18:28 PM PDT 24
Peak memory 183896 kb
Host smart-0ebbddf9-801c-48a2-a732-4aeb6efc999e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716171606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al
iasing.716171606
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2912935001
Short name T56
Test name
Test status
Simulation time 6417144506 ps
CPU time 18.01 seconds
Started Jul 13 06:18:23 PM PDT 24
Finished Jul 13 06:18:42 PM PDT 24
Peak memory 196196 kb
Host smart-7fe1fb9b-cebb-4428-a715-5818148aade5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912935001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.2912935001
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.57388169
Short name T413
Test name
Test status
Simulation time 1042783161 ps
CPU time 0.65 seconds
Started Jul 13 06:18:22 PM PDT 24
Finished Jul 13 06:18:23 PM PDT 24
Peak memory 193036 kb
Host smart-e2e0dc05-6000-4b23-85e7-3028af8a6a42
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57388169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw_
reset.57388169
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3209948925
Short name T350
Test name
Test status
Simulation time 460426267 ps
CPU time 0.89 seconds
Started Jul 13 06:18:27 PM PDT 24
Finished Jul 13 06:18:28 PM PDT 24
Peak memory 196040 kb
Host smart-2b79573d-e116-42bd-8b42-7621f34f0bba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209948925 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3209948925
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.700710532
Short name T374
Test name
Test status
Simulation time 386898181 ps
CPU time 0.63 seconds
Started Jul 13 06:18:23 PM PDT 24
Finished Jul 13 06:18:25 PM PDT 24
Peak memory 183740 kb
Host smart-ed88a394-ff75-41bf-afbe-98c964e9a451
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700710532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.700710532
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2437520641
Short name T386
Test name
Test status
Simulation time 510782444 ps
CPU time 0.72 seconds
Started Jul 13 06:18:22 PM PDT 24
Finished Jul 13 06:18:23 PM PDT 24
Peak memory 183588 kb
Host smart-26d98b17-6897-4356-bb88-6f6db3fc7272
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437520641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.2437520641
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1528884778
Short name T334
Test name
Test status
Simulation time 270173685 ps
CPU time 0.99 seconds
Started Jul 13 06:18:25 PM PDT 24
Finished Jul 13 06:18:28 PM PDT 24
Peak memory 183716 kb
Host smart-0bd78b61-39c6-45e7-a450-d192ce185bbf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528884778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.1528884778
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2197392707
Short name T88
Test name
Test status
Simulation time 2051067609 ps
CPU time 2.73 seconds
Started Jul 13 06:18:23 PM PDT 24
Finished Jul 13 06:18:27 PM PDT 24
Peak memory 194040 kb
Host smart-6ec3155c-391f-4665-badc-bad3ee3f3570
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197392707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2197392707
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3968696168
Short name T418
Test name
Test status
Simulation time 376564962 ps
CPU time 1.28 seconds
Started Jul 13 06:18:24 PM PDT 24
Finished Jul 13 06:18:27 PM PDT 24
Peak memory 198440 kb
Host smart-6be7ab10-a043-4c06-abca-85f67b824a68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968696168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.3968696168
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.668982357
Short name T36
Test name
Test status
Simulation time 4561296741 ps
CPU time 4.39 seconds
Started Jul 13 06:18:24 PM PDT 24
Finished Jul 13 06:18:30 PM PDT 24
Peak memory 196404 kb
Host smart-b8108e41-0960-4ba7-a668-887a5189f343
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668982357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_
intg_err.668982357
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1711520298
Short name T379
Test name
Test status
Simulation time 446196059 ps
CPU time 0.97 seconds
Started Jul 13 06:18:40 PM PDT 24
Finished Jul 13 06:18:43 PM PDT 24
Peak memory 196140 kb
Host smart-507f2969-3a49-465f-b0f7-99d98500fdea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711520298 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1711520298
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3027304131
Short name T72
Test name
Test status
Simulation time 328327183 ps
CPU time 0.73 seconds
Started Jul 13 06:18:41 PM PDT 24
Finished Jul 13 06:18:43 PM PDT 24
Peak memory 193164 kb
Host smart-b9495938-01ac-4619-93a6-75917b05279a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027304131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3027304131
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2939221718
Short name T326
Test name
Test status
Simulation time 356891962 ps
CPU time 1.01 seconds
Started Jul 13 06:18:38 PM PDT 24
Finished Jul 13 06:18:41 PM PDT 24
Peak memory 183648 kb
Host smart-7bf6d15b-2bd0-4d80-8f26-0b4999eca45c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939221718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2939221718
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1599683072
Short name T82
Test name
Test status
Simulation time 1754968293 ps
CPU time 1.18 seconds
Started Jul 13 06:18:39 PM PDT 24
Finished Jul 13 06:18:42 PM PDT 24
Peak memory 193068 kb
Host smart-facfac40-51cb-47b1-a107-fc3b3169740f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599683072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1599683072
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1950121897
Short name T411
Test name
Test status
Simulation time 515714375 ps
CPU time 2.36 seconds
Started Jul 13 06:18:40 PM PDT 24
Finished Jul 13 06:18:44 PM PDT 24
Peak memory 198540 kb
Host smart-afd5d740-a032-4c6b-b79c-9629423d17f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950121897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1950121897
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.435878271
Short name T299
Test name
Test status
Simulation time 8286234845 ps
CPU time 2.93 seconds
Started Jul 13 06:18:41 PM PDT 24
Finished Jul 13 06:18:45 PM PDT 24
Peak memory 198316 kb
Host smart-f198d044-f2d1-4346-88b7-0adc70710fff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435878271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl
_intg_err.435878271
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2544471526
Short name T364
Test name
Test status
Simulation time 802471760 ps
CPU time 0.9 seconds
Started Jul 13 06:18:46 PM PDT 24
Finished Jul 13 06:18:47 PM PDT 24
Peak memory 197056 kb
Host smart-77afb59d-56b4-4227-955b-c63ac4a631fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544471526 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2544471526
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.818520783
Short name T363
Test name
Test status
Simulation time 308413429 ps
CPU time 1.09 seconds
Started Jul 13 06:18:39 PM PDT 24
Finished Jul 13 06:18:42 PM PDT 24
Peak memory 193400 kb
Host smart-32235d01-f620-4b5d-a1be-542f2aa6f04c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818520783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.818520783
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3001701287
Short name T375
Test name
Test status
Simulation time 326384925 ps
CPU time 0.64 seconds
Started Jul 13 06:18:38 PM PDT 24
Finished Jul 13 06:18:40 PM PDT 24
Peak memory 192972 kb
Host smart-1892bc83-2216-4963-9766-1dd110ed4230
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001701287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.3001701287
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1092017615
Short name T347
Test name
Test status
Simulation time 2656063936 ps
CPU time 3.76 seconds
Started Jul 13 06:18:37 PM PDT 24
Finished Jul 13 06:18:42 PM PDT 24
Peak memory 193828 kb
Host smart-648eccda-fdbf-45ad-9f7b-859d3a2a56ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092017615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1092017615
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3255273587
Short name T389
Test name
Test status
Simulation time 608109827 ps
CPU time 1.25 seconds
Started Jul 13 06:18:37 PM PDT 24
Finished Jul 13 06:18:40 PM PDT 24
Peak memory 198632 kb
Host smart-0e9f042d-d679-41fc-bf1a-aef4b599b6cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255273587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3255273587
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.351520871
Short name T307
Test name
Test status
Simulation time 529441201 ps
CPU time 0.92 seconds
Started Jul 13 06:18:40 PM PDT 24
Finished Jul 13 06:18:43 PM PDT 24
Peak memory 198388 kb
Host smart-732cdb01-4a3e-4d0d-9426-50fdecd5dd0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351520871 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.351520871
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1667506022
Short name T68
Test name
Test status
Simulation time 540275361 ps
CPU time 0.95 seconds
Started Jul 13 06:18:38 PM PDT 24
Finished Jul 13 06:18:41 PM PDT 24
Peak memory 193332 kb
Host smart-1adeb5db-7868-44d6-9d8b-ec94ea77bfa7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667506022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1667506022
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3413330420
Short name T323
Test name
Test status
Simulation time 525276454 ps
CPU time 0.62 seconds
Started Jul 13 06:18:39 PM PDT 24
Finished Jul 13 06:18:41 PM PDT 24
Peak memory 192924 kb
Host smart-c793bc07-85f0-4f2f-86c8-91991633a810
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413330420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.3413330420
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1356790375
Short name T421
Test name
Test status
Simulation time 1007773437 ps
CPU time 1.74 seconds
Started Jul 13 06:18:38 PM PDT 24
Finished Jul 13 06:18:42 PM PDT 24
Peak memory 193304 kb
Host smart-96908fc5-e113-4965-a79f-03dcd3b6417a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356790375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1356790375
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3183165794
Short name T296
Test name
Test status
Simulation time 822288301 ps
CPU time 2.15 seconds
Started Jul 13 06:18:41 PM PDT 24
Finished Jul 13 06:18:44 PM PDT 24
Peak memory 198512 kb
Host smart-9b4c8881-a457-4f3e-9b04-024000725296
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183165794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3183165794
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2591767623
Short name T199
Test name
Test status
Simulation time 8571437061 ps
CPU time 13.83 seconds
Started Jul 13 06:18:38 PM PDT 24
Finished Jul 13 06:18:54 PM PDT 24
Peak memory 198084 kb
Host smart-da9a93ea-11fb-47c6-b69f-25314a400e2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591767623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.2591767623
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3857372897
Short name T357
Test name
Test status
Simulation time 469018017 ps
CPU time 1.25 seconds
Started Jul 13 06:18:49 PM PDT 24
Finished Jul 13 06:18:53 PM PDT 24
Peak memory 195444 kb
Host smart-e04cba61-1583-440d-8349-369d255d8dc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857372897 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3857372897
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2454287179
Short name T65
Test name
Test status
Simulation time 382526554 ps
CPU time 0.85 seconds
Started Jul 13 06:18:37 PM PDT 24
Finished Jul 13 06:18:38 PM PDT 24
Peak memory 193420 kb
Host smart-6ec084b4-a4c6-41df-9ed8-6d59ea723e4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454287179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2454287179
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2827025694
Short name T397
Test name
Test status
Simulation time 291563588 ps
CPU time 0.74 seconds
Started Jul 13 06:18:40 PM PDT 24
Finished Jul 13 06:18:43 PM PDT 24
Peak memory 192852 kb
Host smart-26d3e78a-67d7-40c0-a2ed-d82f08304be9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827025694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.2827025694
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.825582192
Short name T89
Test name
Test status
Simulation time 2553348173 ps
CPU time 2.07 seconds
Started Jul 13 06:18:48 PM PDT 24
Finished Jul 13 06:18:51 PM PDT 24
Peak memory 194836 kb
Host smart-1c2e7345-3fda-4d25-b34f-5140e17330ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825582192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon
_timer_same_csr_outstanding.825582192
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2794077900
Short name T337
Test name
Test status
Simulation time 367375753 ps
CPU time 1.58 seconds
Started Jul 13 06:18:45 PM PDT 24
Finished Jul 13 06:18:47 PM PDT 24
Peak memory 198620 kb
Host smart-6222f949-b886-4d7c-85ac-5dce6b3e1047
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794077900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2794077900
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1508803001
Short name T197
Test name
Test status
Simulation time 8843985939 ps
CPU time 4.29 seconds
Started Jul 13 06:18:39 PM PDT 24
Finished Jul 13 06:18:46 PM PDT 24
Peak memory 198308 kb
Host smart-f53e0169-f37c-4ccd-a53e-40ebf8bfb80d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508803001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.1508803001
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.361400902
Short name T327
Test name
Test status
Simulation time 607246759 ps
CPU time 1.15 seconds
Started Jul 13 06:18:51 PM PDT 24
Finished Jul 13 06:18:54 PM PDT 24
Peak memory 198400 kb
Host smart-ebf8b6a5-6fb4-495b-869d-97401607bd16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361400902 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.361400902
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1819614773
Short name T356
Test name
Test status
Simulation time 390872373 ps
CPU time 0.71 seconds
Started Jul 13 06:18:47 PM PDT 24
Finished Jul 13 06:18:49 PM PDT 24
Peak memory 192064 kb
Host smart-9cb19a3c-59a7-4f29-808f-adc698cf84a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819614773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1819614773
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3169049850
Short name T371
Test name
Test status
Simulation time 265952653 ps
CPU time 0.94 seconds
Started Jul 13 06:18:48 PM PDT 24
Finished Jul 13 06:18:50 PM PDT 24
Peak memory 183732 kb
Host smart-c4610406-4e51-4b59-8582-229dfbabcb37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169049850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.3169049850
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1363176178
Short name T353
Test name
Test status
Simulation time 1394005520 ps
CPU time 1.27 seconds
Started Jul 13 06:18:47 PM PDT 24
Finished Jul 13 06:18:49 PM PDT 24
Peak memory 192804 kb
Host smart-41bdb131-7294-458b-aa63-60ad4e7483e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363176178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.1363176178
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1049590573
Short name T336
Test name
Test status
Simulation time 403596003 ps
CPU time 1.29 seconds
Started Jul 13 06:18:46 PM PDT 24
Finished Jul 13 06:18:48 PM PDT 24
Peak memory 198440 kb
Host smart-f05baf79-83eb-4d8d-a85a-76a3b3c55417
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049590573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.1049590573
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.527621671
Short name T38
Test name
Test status
Simulation time 8726558622 ps
CPU time 7.45 seconds
Started Jul 13 06:18:47 PM PDT 24
Finished Jul 13 06:18:55 PM PDT 24
Peak memory 198220 kb
Host smart-38134eec-f079-4f20-9db5-ab6637162a5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527621671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.527621671
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.4223804914
Short name T293
Test name
Test status
Simulation time 419205740 ps
CPU time 1.18 seconds
Started Jul 13 06:18:48 PM PDT 24
Finished Jul 13 06:18:51 PM PDT 24
Peak memory 195252 kb
Host smart-f1549e9f-38f3-45c6-bd1b-a69aea50771b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223804914 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.4223804914
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.4174392290
Short name T59
Test name
Test status
Simulation time 451562302 ps
CPU time 0.9 seconds
Started Jul 13 06:18:48 PM PDT 24
Finished Jul 13 06:18:51 PM PDT 24
Peak memory 192996 kb
Host smart-c7ebd687-9df9-449b-8906-809b8800d8fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174392290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.4174392290
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.449896329
Short name T376
Test name
Test status
Simulation time 397488122 ps
CPU time 1.12 seconds
Started Jul 13 06:18:49 PM PDT 24
Finished Jul 13 06:18:51 PM PDT 24
Peak memory 192960 kb
Host smart-78de11c4-5166-4d4f-b247-16606d9f6930
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449896329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.449896329
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3198836454
Short name T407
Test name
Test status
Simulation time 1027260892 ps
CPU time 0.97 seconds
Started Jul 13 06:18:46 PM PDT 24
Finished Jul 13 06:18:48 PM PDT 24
Peak memory 193016 kb
Host smart-e51c76b0-cd12-4945-a839-13057a2551fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198836454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.3198836454
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1022783434
Short name T292
Test name
Test status
Simulation time 724288412 ps
CPU time 1.81 seconds
Started Jul 13 06:18:49 PM PDT 24
Finished Jul 13 06:18:52 PM PDT 24
Peak memory 198616 kb
Host smart-817007d0-d5b5-4dbf-854d-6cc6b07147e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022783434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.1022783434
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2728645652
Short name T344
Test name
Test status
Simulation time 8408787140 ps
CPU time 3.16 seconds
Started Jul 13 06:18:48 PM PDT 24
Finished Jul 13 06:18:53 PM PDT 24
Peak memory 198304 kb
Host smart-d481be27-e851-42dc-b323-2021903cd6ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728645652 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2728645652
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2532656038
Short name T320
Test name
Test status
Simulation time 538280202 ps
CPU time 1.44 seconds
Started Jul 13 06:18:49 PM PDT 24
Finished Jul 13 06:18:53 PM PDT 24
Peak memory 196236 kb
Host smart-faabf57a-cca2-465e-8b60-754c34d427b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532656038 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.2532656038
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1306388973
Short name T287
Test name
Test status
Simulation time 415400241 ps
CPU time 0.7 seconds
Started Jul 13 06:18:48 PM PDT 24
Finished Jul 13 06:18:50 PM PDT 24
Peak memory 192044 kb
Host smart-a60719cd-4835-4116-8939-6e162d689ed6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306388973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1306388973
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2629592116
Short name T317
Test name
Test status
Simulation time 306503173 ps
CPU time 0.69 seconds
Started Jul 13 06:18:47 PM PDT 24
Finished Jul 13 06:18:49 PM PDT 24
Peak memory 192952 kb
Host smart-23bfe606-b560-4329-a8e6-adc5bcd08738
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629592116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2629592116
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2857214615
Short name T90
Test name
Test status
Simulation time 1031343987 ps
CPU time 1.36 seconds
Started Jul 13 06:18:49 PM PDT 24
Finished Jul 13 06:18:52 PM PDT 24
Peak memory 193604 kb
Host smart-04984d97-031d-42ea-9e1f-71fc9a03ae94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857214615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2857214615
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2308486765
Short name T297
Test name
Test status
Simulation time 611713382 ps
CPU time 2.15 seconds
Started Jul 13 06:18:50 PM PDT 24
Finished Jul 13 06:18:55 PM PDT 24
Peak memory 198564 kb
Host smart-10f5439e-8327-4db1-a5f6-dc8636d64bba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308486765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2308486765
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1877939558
Short name T332
Test name
Test status
Simulation time 7905090887 ps
CPU time 12.07 seconds
Started Jul 13 06:18:49 PM PDT 24
Finished Jul 13 06:19:02 PM PDT 24
Peak memory 198132 kb
Host smart-8c550209-177d-4aee-8c4c-f2f323d34b16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877939558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1877939558
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1530215862
Short name T384
Test name
Test status
Simulation time 436418633 ps
CPU time 0.89 seconds
Started Jul 13 06:18:50 PM PDT 24
Finished Jul 13 06:18:53 PM PDT 24
Peak memory 196220 kb
Host smart-e568f05a-803e-4a71-bc22-378c6afbb0f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530215862 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.1530215862
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2512948917
Short name T63
Test name
Test status
Simulation time 327825727 ps
CPU time 0.67 seconds
Started Jul 13 06:18:47 PM PDT 24
Finished Jul 13 06:18:49 PM PDT 24
Peak memory 193000 kb
Host smart-caa8ca8c-57b4-4092-80f7-aa51bd079d62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512948917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2512948917
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3581661633
Short name T315
Test name
Test status
Simulation time 527212527 ps
CPU time 0.76 seconds
Started Jul 13 06:18:46 PM PDT 24
Finished Jul 13 06:18:48 PM PDT 24
Peak memory 183648 kb
Host smart-f366ea65-64a0-434f-8a81-c619fc5e952d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581661633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3581661633
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3573697698
Short name T84
Test name
Test status
Simulation time 2203399492 ps
CPU time 2.7 seconds
Started Jul 13 06:18:49 PM PDT 24
Finished Jul 13 06:18:53 PM PDT 24
Peak memory 195148 kb
Host smart-a884c571-d084-4ea9-946d-739489489500
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573697698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3573697698
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2716686717
Short name T372
Test name
Test status
Simulation time 547446011 ps
CPU time 2.37 seconds
Started Jul 13 06:18:49 PM PDT 24
Finished Jul 13 06:18:53 PM PDT 24
Peak memory 198644 kb
Host smart-8eb8c0d8-fcb7-40a4-a30e-c716aa97c8af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716686717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2716686717
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3546860976
Short name T360
Test name
Test status
Simulation time 3752009630 ps
CPU time 5.89 seconds
Started Jul 13 06:18:47 PM PDT 24
Finished Jul 13 06:18:53 PM PDT 24
Peak memory 197796 kb
Host smart-a9a7846b-e66a-4adc-a666-f9254dcdda1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546860976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.3546860976
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3201482282
Short name T365
Test name
Test status
Simulation time 359597871 ps
CPU time 1.23 seconds
Started Jul 13 06:18:48 PM PDT 24
Finished Jul 13 06:18:51 PM PDT 24
Peak memory 196212 kb
Host smart-959fa0ca-13f3-4bda-b4ae-1ee64a331fb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201482282 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.3201482282
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.4094671494
Short name T304
Test name
Test status
Simulation time 530889855 ps
CPU time 1.01 seconds
Started Jul 13 06:18:49 PM PDT 24
Finished Jul 13 06:18:51 PM PDT 24
Peak memory 193952 kb
Host smart-a759d139-68e6-4739-8f1e-0495fb656d00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094671494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.4094671494
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1303442020
Short name T355
Test name
Test status
Simulation time 481527105 ps
CPU time 0.72 seconds
Started Jul 13 06:18:47 PM PDT 24
Finished Jul 13 06:18:48 PM PDT 24
Peak memory 192948 kb
Host smart-ddd53be1-32ba-4ae4-834f-9fea4048bfbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303442020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.1303442020
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2952817143
Short name T401
Test name
Test status
Simulation time 1268572559 ps
CPU time 1.02 seconds
Started Jul 13 06:18:46 PM PDT 24
Finished Jul 13 06:18:47 PM PDT 24
Peak memory 193972 kb
Host smart-dd12976f-436c-40f7-b4cd-3871aa2d816d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952817143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.2952817143
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3991463088
Short name T285
Test name
Test status
Simulation time 542953856 ps
CPU time 2.54 seconds
Started Jul 13 06:18:50 PM PDT 24
Finished Jul 13 06:18:55 PM PDT 24
Peak memory 198576 kb
Host smart-a33a9c44-b21f-432f-b1c5-978d9bc75525
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991463088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3991463088
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1281502507
Short name T198
Test name
Test status
Simulation time 7639015655 ps
CPU time 3.92 seconds
Started Jul 13 06:18:48 PM PDT 24
Finished Jul 13 06:18:53 PM PDT 24
Peak memory 198364 kb
Host smart-01589bd0-1825-450f-af90-8fd9830541e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281502507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1281502507
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.753701330
Short name T331
Test name
Test status
Simulation time 458859666 ps
CPU time 0.94 seconds
Started Jul 13 06:18:50 PM PDT 24
Finished Jul 13 06:18:53 PM PDT 24
Peak memory 195348 kb
Host smart-5c2a1a93-6df9-4131-b08b-b3cac72e0ed5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753701330 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.753701330
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.168635893
Short name T346
Test name
Test status
Simulation time 440213756 ps
CPU time 1.19 seconds
Started Jul 13 06:18:49 PM PDT 24
Finished Jul 13 06:18:52 PM PDT 24
Peak memory 192064 kb
Host smart-f6d35314-0974-409a-ae27-66c6fc95a383
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168635893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.168635893
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3994006309
Short name T409
Test name
Test status
Simulation time 317919112 ps
CPU time 0.62 seconds
Started Jul 13 06:18:50 PM PDT 24
Finished Jul 13 06:18:53 PM PDT 24
Peak memory 192880 kb
Host smart-d1fa7b49-44f8-4b22-8f41-ab997014fd0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994006309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3994006309
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3618606067
Short name T83
Test name
Test status
Simulation time 2142245913 ps
CPU time 3.09 seconds
Started Jul 13 06:18:47 PM PDT 24
Finished Jul 13 06:18:51 PM PDT 24
Peak memory 193800 kb
Host smart-ee84748d-49ef-4fa5-8788-eac8857087fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618606067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.3618606067
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1349126990
Short name T335
Test name
Test status
Simulation time 489636607 ps
CPU time 1.25 seconds
Started Jul 13 06:18:48 PM PDT 24
Finished Jul 13 06:18:50 PM PDT 24
Peak memory 198428 kb
Host smart-fe806143-1216-4943-893f-11f1770caaf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349126990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.1349126990
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3614733692
Short name T414
Test name
Test status
Simulation time 4799262869 ps
CPU time 4.18 seconds
Started Jul 13 06:18:50 PM PDT 24
Finished Jul 13 06:18:57 PM PDT 24
Peak memory 196820 kb
Host smart-d5868fe5-4fff-472b-95f9-9e6f47066bd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614733692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.3614733692
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.4164209673
Short name T70
Test name
Test status
Simulation time 399959079 ps
CPU time 1.19 seconds
Started Jul 13 06:18:32 PM PDT 24
Finished Jul 13 06:18:35 PM PDT 24
Peak memory 193220 kb
Host smart-669b51ff-6843-4458-8d00-9c14e6e66f4e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164209673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.4164209673
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2535587561
Short name T342
Test name
Test status
Simulation time 14131003225 ps
CPU time 6.72 seconds
Started Jul 13 06:18:31 PM PDT 24
Finished Jul 13 06:18:40 PM PDT 24
Peak memory 196332 kb
Host smart-0ca65291-02d8-4593-b581-9dfcd0daf5b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535587561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.2535587561
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2737845715
Short name T405
Test name
Test status
Simulation time 787883146 ps
CPU time 1.71 seconds
Started Jul 13 06:18:33 PM PDT 24
Finished Jul 13 06:18:35 PM PDT 24
Peak memory 192144 kb
Host smart-40d04a5c-2f14-46b1-95f3-75f40a5c9645
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737845715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.2737845715
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.751706592
Short name T395
Test name
Test status
Simulation time 505047195 ps
CPU time 1.49 seconds
Started Jul 13 06:18:31 PM PDT 24
Finished Jul 13 06:18:35 PM PDT 24
Peak memory 197396 kb
Host smart-0df8ede1-1526-42f8-aee5-b2d53b0d57f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751706592 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.751706592
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2526245243
Short name T62
Test name
Test status
Simulation time 399138975 ps
CPU time 1.12 seconds
Started Jul 13 06:18:33 PM PDT 24
Finished Jul 13 06:18:35 PM PDT 24
Peak memory 192064 kb
Host smart-0b7b8f75-0c1b-46c2-8ccc-2d9c0dc5a90b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526245243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2526245243
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1883882571
Short name T381
Test name
Test status
Simulation time 519434891 ps
CPU time 1.45 seconds
Started Jul 13 06:18:23 PM PDT 24
Finished Jul 13 06:18:25 PM PDT 24
Peak memory 183652 kb
Host smart-9c120fc0-a4c5-40f8-a570-cb1ed1282521
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883882571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1883882571
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2822760133
Short name T313
Test name
Test status
Simulation time 469746848 ps
CPU time 0.62 seconds
Started Jul 13 06:18:27 PM PDT 24
Finished Jul 13 06:18:28 PM PDT 24
Peak memory 183648 kb
Host smart-17375ca4-5584-4c3e-9996-97ab0cc6dc8a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822760133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.2822760133
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2321256223
Short name T348
Test name
Test status
Simulation time 460745613 ps
CPU time 0.79 seconds
Started Jul 13 06:18:25 PM PDT 24
Finished Jul 13 06:18:27 PM PDT 24
Peak memory 183716 kb
Host smart-bb1fbf00-d061-42d2-bfcb-d47759270cdf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321256223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.2321256223
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1454625798
Short name T361
Test name
Test status
Simulation time 2579423835 ps
CPU time 3.98 seconds
Started Jul 13 06:18:32 PM PDT 24
Finished Jul 13 06:18:37 PM PDT 24
Peak memory 194056 kb
Host smart-ccb921d4-4f3d-437b-8a61-00791175a439
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454625798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.1454625798
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2515513074
Short name T318
Test name
Test status
Simulation time 317625261 ps
CPU time 1.62 seconds
Started Jul 13 06:18:25 PM PDT 24
Finished Jul 13 06:18:28 PM PDT 24
Peak memory 198648 kb
Host smart-c62be4d5-ab48-4706-be59-5b3773526a0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515513074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2515513074
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1092152302
Short name T202
Test name
Test status
Simulation time 7788619383 ps
CPU time 11.06 seconds
Started Jul 13 06:18:24 PM PDT 24
Finished Jul 13 06:18:36 PM PDT 24
Peak memory 198304 kb
Host smart-4fab41d2-b5dc-4dce-abfa-9df19444cab5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092152302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.1092152302
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3341782049
Short name T286
Test name
Test status
Simulation time 421563097 ps
CPU time 1.16 seconds
Started Jul 13 06:18:50 PM PDT 24
Finished Jul 13 06:18:53 PM PDT 24
Peak memory 192868 kb
Host smart-c073b923-3e89-4480-90a0-8251a4e952c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341782049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3341782049
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1190231927
Short name T391
Test name
Test status
Simulation time 410248278 ps
CPU time 1.16 seconds
Started Jul 13 06:18:49 PM PDT 24
Finished Jul 13 06:18:51 PM PDT 24
Peak memory 183744 kb
Host smart-3fd3f5ca-05d9-4060-9c94-54be475c57f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190231927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1190231927
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.453472335
Short name T309
Test name
Test status
Simulation time 402444421 ps
CPU time 1.14 seconds
Started Jul 13 06:18:49 PM PDT 24
Finished Jul 13 06:18:53 PM PDT 24
Peak memory 192868 kb
Host smart-0578acd0-7b68-4231-8db4-5458a6555fa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453472335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.453472335
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.4176797010
Short name T403
Test name
Test status
Simulation time 393965719 ps
CPU time 0.83 seconds
Started Jul 13 06:18:50 PM PDT 24
Finished Jul 13 06:18:53 PM PDT 24
Peak memory 183648 kb
Host smart-e892e005-1101-43ed-9b2c-0e6f560536d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176797010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.4176797010
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.523302957
Short name T345
Test name
Test status
Simulation time 432472063 ps
CPU time 0.9 seconds
Started Jul 13 06:18:51 PM PDT 24
Finished Jul 13 06:18:54 PM PDT 24
Peak memory 183660 kb
Host smart-e35de269-adcc-4311-ac5f-18ff0d1dd4d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523302957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.523302957
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.515515160
Short name T368
Test name
Test status
Simulation time 398723200 ps
CPU time 1.12 seconds
Started Jul 13 06:18:50 PM PDT 24
Finished Jul 13 06:18:54 PM PDT 24
Peak memory 183724 kb
Host smart-d83fa5e9-48e4-4a9c-b68d-62d6604598c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515515160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.515515160
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.4093762411
Short name T301
Test name
Test status
Simulation time 356544744 ps
CPU time 0.64 seconds
Started Jul 13 06:18:50 PM PDT 24
Finished Jul 13 06:18:53 PM PDT 24
Peak memory 183716 kb
Host smart-5e48d8ec-3943-437c-9518-f9235f0d61a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093762411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.4093762411
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2811048541
Short name T352
Test name
Test status
Simulation time 325997564 ps
CPU time 0.62 seconds
Started Jul 13 06:18:57 PM PDT 24
Finished Jul 13 06:18:58 PM PDT 24
Peak memory 192928 kb
Host smart-0296866f-a3cd-421e-b011-b046dbf63ba8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811048541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2811048541
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3439057139
Short name T382
Test name
Test status
Simulation time 398041539 ps
CPU time 0.7 seconds
Started Jul 13 06:18:58 PM PDT 24
Finished Jul 13 06:18:59 PM PDT 24
Peak memory 183664 kb
Host smart-509d0b01-ab95-4ed5-bccc-5ab1c0580170
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439057139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3439057139
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1247356476
Short name T410
Test name
Test status
Simulation time 513068686 ps
CPU time 1.03 seconds
Started Jul 13 06:18:56 PM PDT 24
Finished Jul 13 06:18:57 PM PDT 24
Peak memory 183732 kb
Host smart-09c58bde-3743-4bdd-8910-43e5106c63b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247356476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.1247356476
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.325161433
Short name T66
Test name
Test status
Simulation time 522117338 ps
CPU time 1 seconds
Started Jul 13 06:18:31 PM PDT 24
Finished Jul 13 06:18:33 PM PDT 24
Peak memory 191988 kb
Host smart-cea91931-6770-4ac3-be71-04108a677dd4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325161433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_al
iasing.325161433
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3246531339
Short name T416
Test name
Test status
Simulation time 7138092535 ps
CPU time 25.59 seconds
Started Jul 13 06:18:31 PM PDT 24
Finished Jul 13 06:18:58 PM PDT 24
Peak memory 196588 kb
Host smart-e24e7801-a706-409c-b5ee-1161bb94df53
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246531339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3246531339
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2095803577
Short name T419
Test name
Test status
Simulation time 992737844 ps
CPU time 2.1 seconds
Started Jul 13 06:18:32 PM PDT 24
Finished Jul 13 06:18:36 PM PDT 24
Peak memory 183772 kb
Host smart-c8eb80f3-6ba9-4bde-b1c1-06bb0636b6f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095803577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2095803577
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2481588063
Short name T373
Test name
Test status
Simulation time 516580572 ps
CPU time 0.88 seconds
Started Jul 13 06:18:30 PM PDT 24
Finished Jul 13 06:18:32 PM PDT 24
Peak memory 195552 kb
Host smart-248d86ab-c596-4a4f-807b-514839ea1a0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481588063 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2481588063
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2127412792
Short name T400
Test name
Test status
Simulation time 477587972 ps
CPU time 0.74 seconds
Started Jul 13 06:18:32 PM PDT 24
Finished Jul 13 06:18:34 PM PDT 24
Peak memory 193280 kb
Host smart-6997c5f0-fb11-4b79-9e08-5d26e0ee05a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127412792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.2127412792
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3240577263
Short name T339
Test name
Test status
Simulation time 325673868 ps
CPU time 0.64 seconds
Started Jul 13 06:18:31 PM PDT 24
Finished Jul 13 06:18:33 PM PDT 24
Peak memory 183728 kb
Host smart-7fe4c4b1-885e-4307-9e5c-98b3d02fe800
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240577263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3240577263
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1642056245
Short name T417
Test name
Test status
Simulation time 520492928 ps
CPU time 0.59 seconds
Started Jul 13 06:18:30 PM PDT 24
Finished Jul 13 06:18:32 PM PDT 24
Peak memory 183648 kb
Host smart-d1d81447-605b-4c76-873e-c7817a54e2a0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642056245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.1642056245
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.537379021
Short name T321
Test name
Test status
Simulation time 425885856 ps
CPU time 1.06 seconds
Started Jul 13 06:18:31 PM PDT 24
Finished Jul 13 06:18:33 PM PDT 24
Peak memory 183744 kb
Host smart-a86fa66a-4207-43fc-91a3-4320d811f43d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537379021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wa
lk.537379021
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.955568945
Short name T85
Test name
Test status
Simulation time 2957365908 ps
CPU time 4.58 seconds
Started Jul 13 06:18:31 PM PDT 24
Finished Jul 13 06:18:37 PM PDT 24
Peak memory 191972 kb
Host smart-e95d8495-1b95-4eb9-9e06-9d68cba6ee6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955568945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_
timer_same_csr_outstanding.955568945
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.4224925588
Short name T415
Test name
Test status
Simulation time 453826353 ps
CPU time 2.32 seconds
Started Jul 13 06:18:31 PM PDT 24
Finished Jul 13 06:18:34 PM PDT 24
Peak memory 198540 kb
Host smart-9ba8a33a-f38f-41a9-b8fb-a7b09146fe95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224925588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.4224925588
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2592922382
Short name T412
Test name
Test status
Simulation time 327947755 ps
CPU time 0.69 seconds
Started Jul 13 06:19:00 PM PDT 24
Finished Jul 13 06:19:01 PM PDT 24
Peak memory 183652 kb
Host smart-6efc0d96-2a5b-4d56-82fe-f0fa32f8b0ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592922382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.2592922382
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1240061114
Short name T406
Test name
Test status
Simulation time 362416493 ps
CPU time 1.07 seconds
Started Jul 13 06:18:59 PM PDT 24
Finished Jul 13 06:19:01 PM PDT 24
Peak memory 183724 kb
Host smart-7fc0b272-9069-44ac-8c9f-e83a8c71485c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240061114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1240061114
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3694137807
Short name T312
Test name
Test status
Simulation time 541809447 ps
CPU time 0.68 seconds
Started Jul 13 06:18:59 PM PDT 24
Finished Jul 13 06:19:00 PM PDT 24
Peak memory 183752 kb
Host smart-6b620193-d897-4ac7-a76b-284a9df2c2fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694137807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3694137807
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.175858831
Short name T290
Test name
Test status
Simulation time 425763148 ps
CPU time 1.14 seconds
Started Jul 13 06:18:56 PM PDT 24
Finished Jul 13 06:18:58 PM PDT 24
Peak memory 192876 kb
Host smart-fba4522e-a956-4f4f-a940-f9127a9812da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175858831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.175858831
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2784201398
Short name T385
Test name
Test status
Simulation time 451845843 ps
CPU time 1.16 seconds
Started Jul 13 06:18:59 PM PDT 24
Finished Jul 13 06:19:01 PM PDT 24
Peak memory 183744 kb
Host smart-c0c5f1d6-f00e-40af-a5c2-54eb2f6d4d6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784201398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2784201398
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.806919093
Short name T387
Test name
Test status
Simulation time 362804612 ps
CPU time 0.73 seconds
Started Jul 13 06:18:57 PM PDT 24
Finished Jul 13 06:18:58 PM PDT 24
Peak memory 183752 kb
Host smart-494c8cae-4e62-4284-a568-1001f74bea86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806919093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.806919093
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2192434586
Short name T322
Test name
Test status
Simulation time 357294247 ps
CPU time 0.63 seconds
Started Jul 13 06:19:00 PM PDT 24
Finished Jul 13 06:19:01 PM PDT 24
Peak memory 192948 kb
Host smart-18944f15-fe18-4756-b3e9-33486c15d6cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192434586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.2192434586
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3892988073
Short name T370
Test name
Test status
Simulation time 456268696 ps
CPU time 0.89 seconds
Started Jul 13 06:18:59 PM PDT 24
Finished Jul 13 06:19:01 PM PDT 24
Peak memory 183728 kb
Host smart-84fd285e-1577-4b30-ad82-3b67c91d3459
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892988073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3892988073
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.543060718
Short name T298
Test name
Test status
Simulation time 522093038 ps
CPU time 0.8 seconds
Started Jul 13 06:18:59 PM PDT 24
Finished Jul 13 06:19:01 PM PDT 24
Peak memory 192948 kb
Host smart-b41f6d00-54fc-4697-a338-10f478f52c6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543060718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.543060718
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2131002278
Short name T398
Test name
Test status
Simulation time 399517036 ps
CPU time 1.11 seconds
Started Jul 13 06:18:59 PM PDT 24
Finished Jul 13 06:19:01 PM PDT 24
Peak memory 183724 kb
Host smart-9c998fd4-2333-4ded-941d-ba4b85b0be85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131002278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.2131002278
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.317718235
Short name T71
Test name
Test status
Simulation time 418314317 ps
CPU time 0.95 seconds
Started Jul 13 06:18:31 PM PDT 24
Finished Jul 13 06:18:33 PM PDT 24
Peak memory 191980 kb
Host smart-82880ba2-b99b-4550-be25-b3237967d2c9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317718235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_al
iasing.317718235
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3154392549
Short name T289
Test name
Test status
Simulation time 7239731001 ps
CPU time 18.4 seconds
Started Jul 13 06:18:31 PM PDT 24
Finished Jul 13 06:18:50 PM PDT 24
Peak memory 192216 kb
Host smart-d7d43c18-62a0-4ffe-8760-c7fccbbfb90f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154392549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.3154392549
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1451615357
Short name T302
Test name
Test status
Simulation time 757795894 ps
CPU time 1.61 seconds
Started Jul 13 06:18:33 PM PDT 24
Finished Jul 13 06:18:35 PM PDT 24
Peak memory 192784 kb
Host smart-65dd0aa7-706d-4e56-adac-cc23f3d9e9e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451615357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.1451615357
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2996507614
Short name T329
Test name
Test status
Simulation time 331048564 ps
CPU time 0.86 seconds
Started Jul 13 06:18:32 PM PDT 24
Finished Jul 13 06:18:34 PM PDT 24
Peak memory 195828 kb
Host smart-d9cdf0c9-b9c6-46ac-8fb4-6b2c54602c64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996507614 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.2996507614
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.358981538
Short name T60
Test name
Test status
Simulation time 537935242 ps
CPU time 0.82 seconds
Started Jul 13 06:18:34 PM PDT 24
Finished Jul 13 06:18:36 PM PDT 24
Peak memory 192960 kb
Host smart-7927e5b4-7c6c-408c-9244-957c6166cee3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358981538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.358981538
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1602469662
Short name T300
Test name
Test status
Simulation time 359144636 ps
CPU time 1.04 seconds
Started Jul 13 06:18:29 PM PDT 24
Finished Jul 13 06:18:31 PM PDT 24
Peak memory 183728 kb
Host smart-32d42d47-3b91-4078-8d39-ffce0e7c2c3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602469662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1602469662
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.4204379239
Short name T390
Test name
Test status
Simulation time 413761920 ps
CPU time 0.61 seconds
Started Jul 13 06:18:31 PM PDT 24
Finished Jul 13 06:18:33 PM PDT 24
Peak memory 183672 kb
Host smart-c4b1910d-9134-458d-a540-0c4769e391d2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204379239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.4204379239
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2391827849
Short name T311
Test name
Test status
Simulation time 264726112 ps
CPU time 0.88 seconds
Started Jul 13 06:18:30 PM PDT 24
Finished Jul 13 06:18:31 PM PDT 24
Peak memory 183636 kb
Host smart-211cea50-3f6a-425d-b827-cc02c9302ecb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391827849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2391827849
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1270847621
Short name T383
Test name
Test status
Simulation time 2004887700 ps
CPU time 2.61 seconds
Started Jul 13 06:18:31 PM PDT 24
Finished Jul 13 06:18:35 PM PDT 24
Peak memory 193012 kb
Host smart-85d9e72d-9138-416d-8151-d7bafbcce052
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270847621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.1270847621
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.849946818
Short name T399
Test name
Test status
Simulation time 437369277 ps
CPU time 2.18 seconds
Started Jul 13 06:18:29 PM PDT 24
Finished Jul 13 06:18:32 PM PDT 24
Peak memory 198628 kb
Host smart-2080c547-f5e8-4975-a47d-88857fae4ea6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849946818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.849946818
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1293720539
Short name T310
Test name
Test status
Simulation time 4677238230 ps
CPU time 4.17 seconds
Started Jul 13 06:18:34 PM PDT 24
Finished Jul 13 06:18:39 PM PDT 24
Peak memory 197976 kb
Host smart-7b9717f3-38d8-4d10-982b-8be597a988a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293720539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1293720539
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3260934638
Short name T343
Test name
Test status
Simulation time 424205202 ps
CPU time 0.71 seconds
Started Jul 13 06:18:59 PM PDT 24
Finished Jul 13 06:19:00 PM PDT 24
Peak memory 183744 kb
Host smart-2f39615d-e6ad-4b9e-a393-c0775bc0b9e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260934638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3260934638
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.188131282
Short name T422
Test name
Test status
Simulation time 414475894 ps
CPU time 0.68 seconds
Started Jul 13 06:18:59 PM PDT 24
Finished Jul 13 06:19:00 PM PDT 24
Peak memory 183704 kb
Host smart-ec5af695-2d07-44c1-9848-53fa94d920e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188131282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.188131282
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.4198149403
Short name T328
Test name
Test status
Simulation time 514797587 ps
CPU time 1.35 seconds
Started Jul 13 06:19:00 PM PDT 24
Finished Jul 13 06:19:02 PM PDT 24
Peak memory 192972 kb
Host smart-8693bfb4-ab31-4d5f-a3b5-6e83028b8b8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198149403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.4198149403
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3464818270
Short name T354
Test name
Test status
Simulation time 512071376 ps
CPU time 0.93 seconds
Started Jul 13 06:18:57 PM PDT 24
Finished Jul 13 06:18:58 PM PDT 24
Peak memory 183752 kb
Host smart-c2991272-b1b2-494f-9aa2-afb704a0eb30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464818270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.3464818270
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.4266133723
Short name T351
Test name
Test status
Simulation time 394319901 ps
CPU time 1.13 seconds
Started Jul 13 06:19:00 PM PDT 24
Finished Jul 13 06:19:01 PM PDT 24
Peak memory 192872 kb
Host smart-c40146e3-5c85-47da-ba4e-602fdb3a90c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266133723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.4266133723
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3833954290
Short name T402
Test name
Test status
Simulation time 403045741 ps
CPU time 0.64 seconds
Started Jul 13 06:19:00 PM PDT 24
Finished Jul 13 06:19:01 PM PDT 24
Peak memory 183644 kb
Host smart-1b484750-8ca9-426d-930e-4dfe27089b19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833954290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3833954290
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1302545060
Short name T380
Test name
Test status
Simulation time 520793994 ps
CPU time 0.91 seconds
Started Jul 13 06:18:57 PM PDT 24
Finished Jul 13 06:18:59 PM PDT 24
Peak memory 192944 kb
Host smart-db231de0-011f-450a-8f0f-8c7e130cd528
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302545060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1302545060
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3591916249
Short name T367
Test name
Test status
Simulation time 300180064 ps
CPU time 1.06 seconds
Started Jul 13 06:18:54 PM PDT 24
Finished Jul 13 06:18:55 PM PDT 24
Peak memory 183748 kb
Host smart-7819f36d-a1c8-4db1-bc8b-3be6ad6114df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591916249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3591916249
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2384623486
Short name T396
Test name
Test status
Simulation time 461667584 ps
CPU time 0.7 seconds
Started Jul 13 06:18:59 PM PDT 24
Finished Jul 13 06:19:00 PM PDT 24
Peak memory 183732 kb
Host smart-021b3022-01a1-4a7d-aaac-a4f5ad79e9cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384623486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.2384623486
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.4184864861
Short name T284
Test name
Test status
Simulation time 464601908 ps
CPU time 1.19 seconds
Started Jul 13 06:18:59 PM PDT 24
Finished Jul 13 06:19:01 PM PDT 24
Peak memory 183732 kb
Host smart-70525734-3a02-4a44-8e07-23b5fbfc08aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184864861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.4184864861
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3223993058
Short name T349
Test name
Test status
Simulation time 525698889 ps
CPU time 0.68 seconds
Started Jul 13 06:18:33 PM PDT 24
Finished Jul 13 06:18:35 PM PDT 24
Peak memory 195468 kb
Host smart-896cd9a1-ae9f-4ba7-b9f9-edfa098e34de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223993058 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.3223993058
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1742286223
Short name T61
Test name
Test status
Simulation time 421046714 ps
CPU time 0.96 seconds
Started Jul 13 06:18:29 PM PDT 24
Finished Jul 13 06:18:30 PM PDT 24
Peak memory 193168 kb
Host smart-899cb101-3ca3-4e86-b21e-46bbe4961deb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742286223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1742286223
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.806079530
Short name T338
Test name
Test status
Simulation time 328375313 ps
CPU time 1.01 seconds
Started Jul 13 06:18:30 PM PDT 24
Finished Jul 13 06:18:31 PM PDT 24
Peak memory 183740 kb
Host smart-6e762991-e2b3-4871-89dd-6c606e3e5bce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806079530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.806079530
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2628367632
Short name T408
Test name
Test status
Simulation time 1147616876 ps
CPU time 2.82 seconds
Started Jul 13 06:18:34 PM PDT 24
Finished Jul 13 06:18:38 PM PDT 24
Peak memory 192920 kb
Host smart-608ae54a-cef4-46c9-9ffa-71826e2eb4dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628367632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2628367632
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.75567017
Short name T306
Test name
Test status
Simulation time 441445352 ps
CPU time 2.07 seconds
Started Jul 13 06:18:33 PM PDT 24
Finished Jul 13 06:18:36 PM PDT 24
Peak memory 198612 kb
Host smart-008278c6-7086-45d7-8984-8e26e10dba1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75567017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.75567017
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.393772028
Short name T325
Test name
Test status
Simulation time 8432201935 ps
CPU time 4.18 seconds
Started Jul 13 06:18:33 PM PDT 24
Finished Jul 13 06:18:38 PM PDT 24
Peak memory 198060 kb
Host smart-2eb1dc93-ebb4-4e80-8680-0bd34a27f726
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393772028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.393772028
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.4244470200
Short name T288
Test name
Test status
Simulation time 492252087 ps
CPU time 1.2 seconds
Started Jul 13 06:18:40 PM PDT 24
Finished Jul 13 06:18:43 PM PDT 24
Peak memory 197040 kb
Host smart-2ba22e75-9e75-450e-8071-0b96877f5bc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244470200 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.4244470200
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1671416962
Short name T404
Test name
Test status
Simulation time 406568745 ps
CPU time 1.14 seconds
Started Jul 13 06:18:38 PM PDT 24
Finished Jul 13 06:18:40 PM PDT 24
Peak memory 193344 kb
Host smart-84e6e7ea-30ff-4a1d-892f-b82aa485347f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671416962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1671416962
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3875472529
Short name T295
Test name
Test status
Simulation time 541593777 ps
CPU time 0.58 seconds
Started Jul 13 06:18:39 PM PDT 24
Finished Jul 13 06:18:41 PM PDT 24
Peak memory 192944 kb
Host smart-be28e81c-695b-4020-8dd5-e6b8a6fa03ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875472529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3875472529
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.722946157
Short name T369
Test name
Test status
Simulation time 2999033421 ps
CPU time 2.72 seconds
Started Jul 13 06:18:40 PM PDT 24
Finished Jul 13 06:18:44 PM PDT 24
Peak memory 195432 kb
Host smart-b5a55769-33ff-4246-9695-9df0e32e9c41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722946157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.722946157
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1016878293
Short name T314
Test name
Test status
Simulation time 2184858117 ps
CPU time 2.57 seconds
Started Jul 13 06:18:38 PM PDT 24
Finished Jul 13 06:18:42 PM PDT 24
Peak memory 198576 kb
Host smart-6e4fc574-a5b3-4a5a-bd84-81cac8818e9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016878293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1016878293
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.585905401
Short name T341
Test name
Test status
Simulation time 4598652601 ps
CPU time 7.13 seconds
Started Jul 13 06:18:41 PM PDT 24
Finished Jul 13 06:18:50 PM PDT 24
Peak memory 197584 kb
Host smart-2791a0a1-235f-45f4-b6e0-2fd1c3dc04e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585905401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_
intg_err.585905401
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.628585874
Short name T305
Test name
Test status
Simulation time 641745649 ps
CPU time 0.94 seconds
Started Jul 13 06:18:39 PM PDT 24
Finished Jul 13 06:18:41 PM PDT 24
Peak memory 196740 kb
Host smart-da56cf6c-b835-41c6-bced-f9cc5bd2b8a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628585874 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.628585874
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3841880000
Short name T359
Test name
Test status
Simulation time 474897899 ps
CPU time 1.2 seconds
Started Jul 13 06:18:39 PM PDT 24
Finished Jul 13 06:18:42 PM PDT 24
Peak memory 194028 kb
Host smart-4db081ce-a3de-47d8-b75a-2440718fac44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841880000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3841880000
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2892152144
Short name T358
Test name
Test status
Simulation time 390458273 ps
CPU time 0.71 seconds
Started Jul 13 06:18:39 PM PDT 24
Finished Jul 13 06:18:41 PM PDT 24
Peak memory 192952 kb
Host smart-4ba629e4-c9e1-4cbe-83fa-dc35604a4131
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892152144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.2892152144
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1033866384
Short name T87
Test name
Test status
Simulation time 1089660700 ps
CPU time 1.35 seconds
Started Jul 13 06:18:37 PM PDT 24
Finished Jul 13 06:18:38 PM PDT 24
Peak memory 193488 kb
Host smart-dbb5fd51-c475-4884-87a6-575df91c246a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033866384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.1033866384
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2811283165
Short name T393
Test name
Test status
Simulation time 548530731 ps
CPU time 1.45 seconds
Started Jul 13 06:18:39 PM PDT 24
Finished Jul 13 06:18:42 PM PDT 24
Peak memory 198624 kb
Host smart-89ec0d75-8551-4c7b-ab76-51172cc234a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811283165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.2811283165
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2759090818
Short name T316
Test name
Test status
Simulation time 4453520910 ps
CPU time 2.18 seconds
Started Jul 13 06:18:39 PM PDT 24
Finished Jul 13 06:18:43 PM PDT 24
Peak memory 197896 kb
Host smart-282f8048-3327-4720-89f4-2f1457a94bc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759090818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.2759090818
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3352189217
Short name T394
Test name
Test status
Simulation time 522705863 ps
CPU time 1.34 seconds
Started Jul 13 06:18:40 PM PDT 24
Finished Jul 13 06:18:43 PM PDT 24
Peak memory 196556 kb
Host smart-c435c2fd-bb38-491a-ad6d-1bd9266d6533
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352189217 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.3352189217
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2796420939
Short name T64
Test name
Test status
Simulation time 487434589 ps
CPU time 1.34 seconds
Started Jul 13 06:18:36 PM PDT 24
Finished Jul 13 06:18:38 PM PDT 24
Peak memory 194020 kb
Host smart-e90697eb-62ca-47df-9122-f4d52b4e00bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796420939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2796420939
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.594029471
Short name T308
Test name
Test status
Simulation time 426928921 ps
CPU time 1.19 seconds
Started Jul 13 06:18:39 PM PDT 24
Finished Jul 13 06:18:42 PM PDT 24
Peak memory 183736 kb
Host smart-b5287145-fa8e-4380-ad8f-119816d905e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594029471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.594029471
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1974543502
Short name T388
Test name
Test status
Simulation time 2151663616 ps
CPU time 1.42 seconds
Started Jul 13 06:18:41 PM PDT 24
Finished Jul 13 06:18:44 PM PDT 24
Peak memory 193992 kb
Host smart-ae8ae9b1-d7d5-49aa-aac5-c25b00d47cc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974543502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1974543502
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.4238175850
Short name T366
Test name
Test status
Simulation time 385798084 ps
CPU time 2.35 seconds
Started Jul 13 06:18:37 PM PDT 24
Finished Jul 13 06:18:40 PM PDT 24
Peak memory 198648 kb
Host smart-6c8dab9e-a5fa-4a94-9925-8a67e52348ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238175850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.4238175850
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.4216866568
Short name T201
Test name
Test status
Simulation time 4417364116 ps
CPU time 6.91 seconds
Started Jul 13 06:18:39 PM PDT 24
Finished Jul 13 06:18:47 PM PDT 24
Peak memory 197780 kb
Host smart-c173dcbc-efe9-4533-bcd8-f3b32e492f1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216866568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.4216866568
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3017183795
Short name T39
Test name
Test status
Simulation time 517814626 ps
CPU time 1.22 seconds
Started Jul 13 06:18:37 PM PDT 24
Finished Jul 13 06:18:40 PM PDT 24
Peak memory 196296 kb
Host smart-bb3d3728-cf5a-4e72-9910-155cb20285d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017183795 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.3017183795
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2582202751
Short name T69
Test name
Test status
Simulation time 298252379 ps
CPU time 1.06 seconds
Started Jul 13 06:18:39 PM PDT 24
Finished Jul 13 06:18:42 PM PDT 24
Peak memory 194028 kb
Host smart-3fca2097-906e-4a2b-88b6-f2f0703e95f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582202751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2582202751
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.887663691
Short name T340
Test name
Test status
Simulation time 340462714 ps
CPU time 0.81 seconds
Started Jul 13 06:18:38 PM PDT 24
Finished Jul 13 06:18:39 PM PDT 24
Peak memory 192960 kb
Host smart-9a87d012-a9a4-4c07-b99d-a6442467742b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887663691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.887663691
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3168194678
Short name T86
Test name
Test status
Simulation time 1031759959 ps
CPU time 1 seconds
Started Jul 13 06:18:37 PM PDT 24
Finished Jul 13 06:18:39 PM PDT 24
Peak memory 193592 kb
Host smart-ec01ff68-892b-4ffb-ba56-925a7e2e35b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168194678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.3168194678
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2878824898
Short name T392
Test name
Test status
Simulation time 568737290 ps
CPU time 2.34 seconds
Started Jul 13 06:18:41 PM PDT 24
Finished Jul 13 06:18:45 PM PDT 24
Peak memory 198620 kb
Host smart-e2c2073c-da26-4fc1-820c-28a6e50f06b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878824898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2878824898
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2177921248
Short name T324
Test name
Test status
Simulation time 4208856971 ps
CPU time 1.36 seconds
Started Jul 13 06:18:43 PM PDT 24
Finished Jul 13 06:18:45 PM PDT 24
Peak memory 196492 kb
Host smart-17457ad6-eac5-4a65-8f62-d0f93d0a443d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177921248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2177921248
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.1841554391
Short name T211
Test name
Test status
Simulation time 21672047342 ps
CPU time 8.42 seconds
Started Jul 13 06:37:53 PM PDT 24
Finished Jul 13 06:38:02 PM PDT 24
Peak memory 191948 kb
Host smart-f0874c1f-6d12-4e49-9483-7e556256d615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841554391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1841554391
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.215804650
Short name T205
Test name
Test status
Simulation time 372497722 ps
CPU time 0.83 seconds
Started Jul 13 06:37:53 PM PDT 24
Finished Jul 13 06:37:54 PM PDT 24
Peak memory 191864 kb
Host smart-4eabed10-8424-4116-9977-7bf52464cce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215804650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.215804650
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.1440565033
Short name T1
Test name
Test status
Simulation time 9752118420 ps
CPU time 4.29 seconds
Started Jul 13 06:38:09 PM PDT 24
Finished Jul 13 06:38:18 PM PDT 24
Peak memory 191776 kb
Host smart-bc7e945b-384e-459a-9624-c994f96e3cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440565033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.1440565033
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3337872799
Short name T16
Test name
Test status
Simulation time 4997116126 ps
CPU time 2.43 seconds
Started Jul 13 06:38:07 PM PDT 24
Finished Jul 13 06:38:11 PM PDT 24
Peak memory 215732 kb
Host smart-85a0ffa2-a2cc-41dc-8832-05017147bbad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337872799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3337872799
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.3970963348
Short name T270
Test name
Test status
Simulation time 513193486 ps
CPU time 0.82 seconds
Started Jul 13 06:37:54 PM PDT 24
Finished Jul 13 06:37:55 PM PDT 24
Peak memory 191864 kb
Host smart-97736451-86e3-405a-b3a2-84a99f5290d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970963348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.3970963348
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_jump.4061523766
Short name T190
Test name
Test status
Simulation time 567299545 ps
CPU time 0.73 seconds
Started Jul 13 06:38:09 PM PDT 24
Finished Jul 13 06:38:14 PM PDT 24
Peak memory 196676 kb
Host smart-4bbcf017-a045-4eda-8c7e-9143e7db55ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061523766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.4061523766
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.3761400130
Short name T258
Test name
Test status
Simulation time 40891007856 ps
CPU time 28.87 seconds
Started Jul 13 06:38:09 PM PDT 24
Finished Jul 13 06:38:42 PM PDT 24
Peak memory 191844 kb
Host smart-8bf9a679-3d7b-4c13-ab33-eae052cd8488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761400130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3761400130
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.2855717310
Short name T260
Test name
Test status
Simulation time 490577468 ps
CPU time 0.75 seconds
Started Jul 13 06:38:09 PM PDT 24
Finished Jul 13 06:38:14 PM PDT 24
Peak memory 191864 kb
Host smart-b5247aa1-165e-47eb-89d9-9db68d1bd600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855717310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.2855717310
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.1386501364
Short name T207
Test name
Test status
Simulation time 43982659161 ps
CPU time 8.12 seconds
Started Jul 13 06:38:07 PM PDT 24
Finished Jul 13 06:38:19 PM PDT 24
Peak memory 196924 kb
Host smart-0ef6fb82-8498-4000-a8a2-aa114c44e456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386501364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1386501364
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.3351993658
Short name T237
Test name
Test status
Simulation time 577545658 ps
CPU time 1.44 seconds
Started Jul 13 06:38:09 PM PDT 24
Finished Jul 13 06:38:15 PM PDT 24
Peak memory 196676 kb
Host smart-1d41a2a0-f856-47e2-9114-53c0f2ea430f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351993658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3351993658
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.1808091482
Short name T13
Test name
Test status
Simulation time 21075828644 ps
CPU time 28.45 seconds
Started Jul 13 06:38:20 PM PDT 24
Finished Jul 13 06:38:49 PM PDT 24
Peak memory 191936 kb
Host smart-663f2db4-1061-4dba-b1ce-2a15ba4aec75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808091482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1808091482
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.242191881
Short name T26
Test name
Test status
Simulation time 576138104 ps
CPU time 0.66 seconds
Started Jul 13 06:38:21 PM PDT 24
Finished Jul 13 06:38:23 PM PDT 24
Peak memory 190500 kb
Host smart-a11282c5-6cc2-449c-8f89-445d912e9433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242191881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.242191881
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3424572996
Short name T246
Test name
Test status
Simulation time 41074823991 ps
CPU time 52.66 seconds
Started Jul 13 06:38:22 PM PDT 24
Finished Jul 13 06:39:18 PM PDT 24
Peak memory 196904 kb
Host smart-974f40a7-15aa-464f-abf2-fb5b810a96f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424572996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3424572996
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.2875824765
Short name T245
Test name
Test status
Simulation time 398080341 ps
CPU time 0.87 seconds
Started Jul 13 06:38:19 PM PDT 24
Finished Jul 13 06:38:21 PM PDT 24
Peak memory 191772 kb
Host smart-62602dd2-9366-42d5-a2be-d04e572da63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875824765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2875824765
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.685624818
Short name T174
Test name
Test status
Simulation time 271299621679 ps
CPU time 262.94 seconds
Started Jul 13 06:38:21 PM PDT 24
Finished Jul 13 06:42:46 PM PDT 24
Peak memory 209068 kb
Host smart-1ecbfd76-1730-4671-9557-c26b25ec0762
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685624818 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.685624818
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.1168181139
Short name T209
Test name
Test status
Simulation time 35700402683 ps
CPU time 52.61 seconds
Started Jul 13 06:38:23 PM PDT 24
Finished Jul 13 06:39:19 PM PDT 24
Peak memory 191776 kb
Host smart-c93640e6-0123-47e0-9e36-3811b6ffb1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168181139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1168181139
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.1851336088
Short name T231
Test name
Test status
Simulation time 513785974 ps
CPU time 1.44 seconds
Started Jul 13 06:38:23 PM PDT 24
Finished Jul 13 06:38:28 PM PDT 24
Peak memory 191872 kb
Host smart-9d75e60d-f7c0-42ab-a961-e92532e8f28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851336088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.1851336088
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_jump.3572386427
Short name T194
Test name
Test status
Simulation time 456703552 ps
CPU time 0.75 seconds
Started Jul 13 06:38:17 PM PDT 24
Finished Jul 13 06:38:18 PM PDT 24
Peak memory 196620 kb
Host smart-00d737f1-02bf-4444-aee4-d8b8692232c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572386427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3572386427
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.3791137734
Short name T80
Test name
Test status
Simulation time 29958104197 ps
CPU time 21.27 seconds
Started Jul 13 06:38:19 PM PDT 24
Finished Jul 13 06:38:41 PM PDT 24
Peak memory 191920 kb
Host smart-0eaf1e1f-87f0-4eb3-9ad4-7251af71bd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791137734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3791137734
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.430957368
Short name T102
Test name
Test status
Simulation time 444877083 ps
CPU time 0.78 seconds
Started Jul 13 06:38:20 PM PDT 24
Finished Jul 13 06:38:22 PM PDT 24
Peak memory 196632 kb
Host smart-eab290bb-a8c6-43af-85d1-079565b7af18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430957368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.430957368
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.2266732778
Short name T256
Test name
Test status
Simulation time 44416956077 ps
CPU time 64.47 seconds
Started Jul 13 06:38:21 PM PDT 24
Finished Jul 13 06:39:26 PM PDT 24
Peak memory 191940 kb
Host smart-c6f1a2a5-5f23-431b-a09b-ca629c9299f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266732778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.2266732778
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2054342062
Short name T216
Test name
Test status
Simulation time 571225795 ps
CPU time 0.82 seconds
Started Jul 13 06:38:20 PM PDT 24
Finished Jul 13 06:38:22 PM PDT 24
Peak memory 196628 kb
Host smart-33ea06c1-6e92-4b4b-af1d-2e7a4fd2b379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054342062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2054342062
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1254751370
Short name T51
Test name
Test status
Simulation time 33050784020 ps
CPU time 11.72 seconds
Started Jul 13 06:38:20 PM PDT 24
Finished Jul 13 06:38:33 PM PDT 24
Peak memory 191884 kb
Host smart-0702ad92-a8b8-4600-a3d3-d594095ee06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254751370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1254751370
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1590805507
Short name T233
Test name
Test status
Simulation time 596622678 ps
CPU time 1.39 seconds
Started Jul 13 06:38:18 PM PDT 24
Finished Jul 13 06:38:20 PM PDT 24
Peak memory 191864 kb
Host smart-5325f5ca-c607-4fc6-868f-17e0f736eb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590805507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1590805507
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.589502546
Short name T226
Test name
Test status
Simulation time 40192892326 ps
CPU time 31.5 seconds
Started Jul 13 06:38:22 PM PDT 24
Finished Jul 13 06:38:55 PM PDT 24
Peak memory 191844 kb
Host smart-0f110d3b-861a-4d40-9f18-b9ae7a75df65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589502546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.589502546
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.2897088247
Short name T278
Test name
Test status
Simulation time 514766253 ps
CPU time 0.92 seconds
Started Jul 13 06:38:23 PM PDT 24
Finished Jul 13 06:38:27 PM PDT 24
Peak memory 191824 kb
Host smart-dcc0a467-23cd-4e09-abdd-38be050f2e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897088247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2897088247
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_jump.714633267
Short name T188
Test name
Test status
Simulation time 411686156 ps
CPU time 1.11 seconds
Started Jul 13 06:38:20 PM PDT 24
Finished Jul 13 06:38:22 PM PDT 24
Peak memory 196616 kb
Host smart-e3336f76-f80e-48c8-8fd9-2268ed4ad7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714633267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.714633267
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.476276691
Short name T213
Test name
Test status
Simulation time 9838010659 ps
CPU time 13 seconds
Started Jul 13 06:38:23 PM PDT 24
Finished Jul 13 06:38:41 PM PDT 24
Peak memory 191928 kb
Host smart-b2a7e12b-b709-4646-a8fd-009a89094f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476276691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.476276691
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1066763522
Short name T8
Test name
Test status
Simulation time 387001995 ps
CPU time 0.91 seconds
Started Jul 13 06:38:22 PM PDT 24
Finished Jul 13 06:38:26 PM PDT 24
Peak memory 191860 kb
Host smart-7824ecfd-600f-417b-9cd7-1eedf0c45cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066763522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1066763522
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.542489048
Short name T261
Test name
Test status
Simulation time 34629682777 ps
CPU time 44.28 seconds
Started Jul 13 06:38:07 PM PDT 24
Finished Jul 13 06:38:55 PM PDT 24
Peak memory 196948 kb
Host smart-8cf96a33-a2a6-43f1-861e-2573a258b7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542489048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.542489048
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.269503797
Short name T15
Test name
Test status
Simulation time 8098387525 ps
CPU time 3.73 seconds
Started Jul 13 06:38:08 PM PDT 24
Finished Jul 13 06:38:15 PM PDT 24
Peak memory 215676 kb
Host smart-2751c88a-8bce-407c-8e7a-fdd1cc7c730b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269503797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.269503797
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.2949015752
Short name T273
Test name
Test status
Simulation time 568488706 ps
CPU time 1.45 seconds
Started Jul 13 06:38:09 PM PDT 24
Finished Jul 13 06:38:15 PM PDT 24
Peak memory 197012 kb
Host smart-b1cb3026-878e-47e3-b2e5-9d41c8b69da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949015752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2949015752
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.48082986
Short name T204
Test name
Test status
Simulation time 35720014663 ps
CPU time 52.33 seconds
Started Jul 13 06:38:24 PM PDT 24
Finished Jul 13 06:39:20 PM PDT 24
Peak memory 196852 kb
Host smart-977f9e0a-cf77-4052-b74f-35a04f7242b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48082986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.48082986
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2745668258
Short name T212
Test name
Test status
Simulation time 589077695 ps
CPU time 0.67 seconds
Started Jul 13 06:38:22 PM PDT 24
Finished Jul 13 06:38:26 PM PDT 24
Peak memory 191772 kb
Host smart-e35580f6-62df-4fa0-99ab-d08b40c3c8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745668258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2745668258
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.2717473894
Short name T281
Test name
Test status
Simulation time 10924921280 ps
CPU time 8.43 seconds
Started Jul 13 06:38:26 PM PDT 24
Finished Jul 13 06:38:38 PM PDT 24
Peak memory 196832 kb
Host smart-30c164fc-572b-40c9-ab3c-68eab7149fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717473894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.2717473894
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.2946243492
Short name T268
Test name
Test status
Simulation time 542914141 ps
CPU time 0.95 seconds
Started Jul 13 06:38:24 PM PDT 24
Finished Jul 13 06:38:28 PM PDT 24
Peak memory 196652 kb
Host smart-86fb3b76-b9fb-44d2-89b3-1898347846a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946243492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.2946243492
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2740572366
Short name T248
Test name
Test status
Simulation time 40438409341 ps
CPU time 5.85 seconds
Started Jul 13 06:38:19 PM PDT 24
Finished Jul 13 06:38:26 PM PDT 24
Peak memory 191932 kb
Host smart-85f0a723-799e-43f1-b14f-bf0cec4c2e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740572366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2740572366
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1719221179
Short name T236
Test name
Test status
Simulation time 544263383 ps
CPU time 1.28 seconds
Started Jul 13 06:38:24 PM PDT 24
Finished Jul 13 06:38:29 PM PDT 24
Peak memory 191884 kb
Host smart-3f66d012-611d-4f33-8c09-0061523543cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719221179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1719221179
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.1570072390
Short name T272
Test name
Test status
Simulation time 54952576280 ps
CPU time 74.58 seconds
Started Jul 13 06:38:20 PM PDT 24
Finished Jul 13 06:39:36 PM PDT 24
Peak memory 191876 kb
Host smart-eaddb699-671c-49b8-ac5a-8dced408e393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570072390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1570072390
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.789470956
Short name T244
Test name
Test status
Simulation time 474542300 ps
CPU time 0.73 seconds
Started Jul 13 06:38:25 PM PDT 24
Finished Jul 13 06:38:29 PM PDT 24
Peak memory 191840 kb
Host smart-c0fee851-2ec2-469f-a036-a60f5dcaefa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789470956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.789470956
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2194969086
Short name T227
Test name
Test status
Simulation time 4708448358 ps
CPU time 7.58 seconds
Started Jul 13 06:38:22 PM PDT 24
Finished Jul 13 06:38:32 PM PDT 24
Peak memory 191940 kb
Host smart-2575b065-4086-4bf9-9582-e0297215c59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194969086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2194969086
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.1631496153
Short name T274
Test name
Test status
Simulation time 467788077 ps
CPU time 1.27 seconds
Started Jul 13 06:38:24 PM PDT 24
Finished Jul 13 06:38:29 PM PDT 24
Peak memory 191864 kb
Host smart-1d38e5f4-bd6b-4ccd-b363-40b212e2cdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631496153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.1631496153
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3392006144
Short name T28
Test name
Test status
Simulation time 500538215 ps
CPU time 1.02 seconds
Started Jul 13 06:38:24 PM PDT 24
Finished Jul 13 06:38:29 PM PDT 24
Peak memory 196744 kb
Host smart-95efc46d-673e-41b8-a0a7-4eac884cb7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392006144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3392006144
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.2703110549
Short name T266
Test name
Test status
Simulation time 33678227946 ps
CPU time 43.97 seconds
Started Jul 13 06:38:25 PM PDT 24
Finished Jul 13 06:39:13 PM PDT 24
Peak memory 191828 kb
Host smart-240ae574-f82e-445a-8463-5d1ba686c912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703110549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.2703110549
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3568000514
Short name T271
Test name
Test status
Simulation time 503071335 ps
CPU time 1.31 seconds
Started Jul 13 06:38:25 PM PDT 24
Finished Jul 13 06:38:30 PM PDT 24
Peak memory 191772 kb
Host smart-c0a1d4cf-6743-4727-b356-c7b5d55b88a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568000514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3568000514
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2453866449
Short name T252
Test name
Test status
Simulation time 1031912813 ps
CPU time 1.32 seconds
Started Jul 13 06:38:24 PM PDT 24
Finished Jul 13 06:38:30 PM PDT 24
Peak memory 191884 kb
Host smart-07e21ea8-99e1-47fa-9637-09c46793643b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453866449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2453866449
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2812466446
Short name T218
Test name
Test status
Simulation time 394011287 ps
CPU time 0.88 seconds
Started Jul 13 06:38:25 PM PDT 24
Finished Jul 13 06:38:30 PM PDT 24
Peak memory 196616 kb
Host smart-f5293451-a380-4558-9b9b-06a32ac6400a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812466446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2812466446
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2546356851
Short name T2
Test name
Test status
Simulation time 542921962 ps
CPU time 1.33 seconds
Started Jul 13 06:38:24 PM PDT 24
Finished Jul 13 06:38:29 PM PDT 24
Peak memory 196200 kb
Host smart-d0404593-721c-46cc-ba55-7f904c10d969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546356851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2546356851
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.2870707605
Short name T234
Test name
Test status
Simulation time 38742758996 ps
CPU time 13.62 seconds
Started Jul 13 06:38:41 PM PDT 24
Finished Jul 13 06:38:56 PM PDT 24
Peak memory 196932 kb
Host smart-f6b70ef3-eeb7-48e9-91b2-d06d7cd25f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870707605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2870707605
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.615482539
Short name T251
Test name
Test status
Simulation time 576417511 ps
CPU time 0.71 seconds
Started Jul 13 06:38:24 PM PDT 24
Finished Jul 13 06:38:28 PM PDT 24
Peak memory 191852 kb
Host smart-d99bd450-b1a9-4194-b0ff-df6160d21500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615482539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.615482539
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1610249812
Short name T74
Test name
Test status
Simulation time 41314860237 ps
CPU time 27.83 seconds
Started Jul 13 06:38:22 PM PDT 24
Finished Jul 13 06:38:53 PM PDT 24
Peak memory 196948 kb
Host smart-dec31b21-ce82-4365-845a-a088f2437779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610249812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1610249812
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1283405528
Short name T219
Test name
Test status
Simulation time 584376520 ps
CPU time 1.03 seconds
Started Jul 13 06:38:28 PM PDT 24
Finished Jul 13 06:38:32 PM PDT 24
Peak memory 191868 kb
Host smart-d02ae009-a34f-4d6c-9571-e8c117c32348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283405528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1283405528
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.4229199951
Short name T217
Test name
Test status
Simulation time 28344947235 ps
CPU time 20.34 seconds
Started Jul 13 06:38:26 PM PDT 24
Finished Jul 13 06:38:50 PM PDT 24
Peak memory 191920 kb
Host smart-0ccfb44b-11d6-4416-8f76-b0895849d35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229199951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.4229199951
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.1461688221
Short name T220
Test name
Test status
Simulation time 473870391 ps
CPU time 0.89 seconds
Started Jul 13 06:38:27 PM PDT 24
Finished Jul 13 06:38:31 PM PDT 24
Peak memory 191872 kb
Host smart-7e13c79f-2334-473b-a93f-b5779f6219a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461688221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1461688221
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.2075991549
Short name T208
Test name
Test status
Simulation time 43294577144 ps
CPU time 15.78 seconds
Started Jul 13 06:38:09 PM PDT 24
Finished Jul 13 06:38:29 PM PDT 24
Peak memory 191828 kb
Host smart-6598c98f-e82a-4d6b-a7be-bbd0093e1eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075991549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2075991549
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2428286973
Short name T17
Test name
Test status
Simulation time 8311944419 ps
CPU time 2.3 seconds
Started Jul 13 06:38:07 PM PDT 24
Finished Jul 13 06:38:11 PM PDT 24
Peak memory 215760 kb
Host smart-51225362-97ac-4def-9313-6a8a012563c8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428286973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2428286973
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.206585926
Short name T225
Test name
Test status
Simulation time 438500534 ps
CPU time 0.91 seconds
Started Jul 13 06:38:08 PM PDT 24
Finished Jul 13 06:38:13 PM PDT 24
Peak memory 191880 kb
Host smart-5ba1513b-381f-44e2-8d3f-55647d294157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206585926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.206585926
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.4191850223
Short name T277
Test name
Test status
Simulation time 18592933944 ps
CPU time 7.05 seconds
Started Jul 13 06:38:26 PM PDT 24
Finished Jul 13 06:38:37 PM PDT 24
Peak memory 191916 kb
Host smart-3d050206-0786-449c-adcf-5073e010be95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191850223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.4191850223
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.315153147
Short name T43
Test name
Test status
Simulation time 432448591 ps
CPU time 0.86 seconds
Started Jul 13 06:38:24 PM PDT 24
Finished Jul 13 06:38:28 PM PDT 24
Peak memory 191852 kb
Host smart-35a090db-772f-409a-987b-69de1453d4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315153147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.315153147
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.2015936717
Short name T241
Test name
Test status
Simulation time 33565071817 ps
CPU time 48.58 seconds
Started Jul 13 06:38:26 PM PDT 24
Finished Jul 13 06:39:18 PM PDT 24
Peak memory 191828 kb
Host smart-9bd77e5a-8dab-4bf4-8eec-19434cd9862d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015936717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.2015936717
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.731988401
Short name T267
Test name
Test status
Simulation time 497216285 ps
CPU time 1.28 seconds
Started Jul 13 06:38:26 PM PDT 24
Finished Jul 13 06:38:31 PM PDT 24
Peak memory 196684 kb
Host smart-de33f7e9-6a51-4dd9-bc4d-3946766fcfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731988401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.731988401
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_jump.63976743
Short name T195
Test name
Test status
Simulation time 442297332 ps
CPU time 0.67 seconds
Started Jul 13 06:38:25 PM PDT 24
Finished Jul 13 06:38:29 PM PDT 24
Peak memory 196576 kb
Host smart-c9cddd9b-4fd7-48d5-a5f5-ed71fe797370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63976743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.63976743
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2534817107
Short name T275
Test name
Test status
Simulation time 32992023768 ps
CPU time 41.49 seconds
Started Jul 13 06:38:27 PM PDT 24
Finished Jul 13 06:39:12 PM PDT 24
Peak memory 196924 kb
Host smart-76857abd-f87f-4cc8-8cd3-c5ad5b03fb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534817107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2534817107
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.1325632486
Short name T27
Test name
Test status
Simulation time 355754151 ps
CPU time 1.18 seconds
Started Jul 13 06:38:24 PM PDT 24
Finished Jul 13 06:38:29 PM PDT 24
Peak memory 191832 kb
Host smart-5ff92757-9bf9-47bf-ab74-1dd032a33a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325632486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1325632486
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.10806101
Short name T242
Test name
Test status
Simulation time 16911030063 ps
CPU time 21.96 seconds
Started Jul 13 06:38:33 PM PDT 24
Finished Jul 13 06:38:56 PM PDT 24
Peak memory 191932 kb
Host smart-b4d03fd5-5b0e-4b23-ac96-7bbffbcd2bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10806101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.10806101
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.920777687
Short name T243
Test name
Test status
Simulation time 459284894 ps
CPU time 0.92 seconds
Started Jul 13 06:38:39 PM PDT 24
Finished Jul 13 06:38:42 PM PDT 24
Peak memory 196600 kb
Host smart-d5088728-fa42-4b8a-9916-b25ac24f14fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920777687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.920777687
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3496338840
Short name T10
Test name
Test status
Simulation time 19425210434 ps
CPU time 2.98 seconds
Started Jul 13 06:38:29 PM PDT 24
Finished Jul 13 06:38:34 PM PDT 24
Peak memory 196824 kb
Host smart-ae8cc0fd-c9e0-4381-9023-614abe4b9c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496338840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3496338840
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.3956795041
Short name T232
Test name
Test status
Simulation time 499922816 ps
CPU time 0.73 seconds
Started Jul 13 06:38:29 PM PDT 24
Finished Jul 13 06:38:32 PM PDT 24
Peak memory 191864 kb
Host smart-edd075d3-29c2-4379-b8a0-8a0f30dae8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956795041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3956795041
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1167457120
Short name T210
Test name
Test status
Simulation time 31940563353 ps
CPU time 41.64 seconds
Started Jul 13 06:38:31 PM PDT 24
Finished Jul 13 06:39:14 PM PDT 24
Peak memory 196920 kb
Host smart-7ea184b8-6973-43de-bdd3-7ed95e4d4da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167457120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1167457120
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.3290029994
Short name T250
Test name
Test status
Simulation time 631479707 ps
CPU time 0.68 seconds
Started Jul 13 06:38:36 PM PDT 24
Finished Jul 13 06:38:38 PM PDT 24
Peak memory 191896 kb
Host smart-a56eeab4-8bef-4cc5-9c75-714907f439c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290029994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3290029994
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.3893765778
Short name T265
Test name
Test status
Simulation time 7469329961 ps
CPU time 2.01 seconds
Started Jul 13 06:38:29 PM PDT 24
Finished Jul 13 06:38:33 PM PDT 24
Peak memory 196944 kb
Host smart-290582d1-7d23-45e7-b5c4-bbd3d1b7ef71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893765778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.3893765778
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.2423754166
Short name T269
Test name
Test status
Simulation time 456597310 ps
CPU time 0.68 seconds
Started Jul 13 06:38:29 PM PDT 24
Finished Jul 13 06:38:32 PM PDT 24
Peak memory 196592 kb
Host smart-83e5b9bd-c3fe-4923-a57b-2fe14ba9dda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423754166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.2423754166
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.4139085101
Short name T215
Test name
Test status
Simulation time 6646980160 ps
CPU time 5.91 seconds
Started Jul 13 06:38:37 PM PDT 24
Finished Jul 13 06:38:44 PM PDT 24
Peak memory 191788 kb
Host smart-dfec410c-077e-4148-9018-872b3912f12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139085101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.4139085101
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2701947929
Short name T263
Test name
Test status
Simulation time 505830936 ps
CPU time 1.14 seconds
Started Jul 13 06:38:31 PM PDT 24
Finished Jul 13 06:38:34 PM PDT 24
Peak memory 191856 kb
Host smart-0dcb11e5-2670-4b00-82e4-7adfb8d9bbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701947929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2701947929
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_jump.900429825
Short name T192
Test name
Test status
Simulation time 502841214 ps
CPU time 0.94 seconds
Started Jul 13 06:38:36 PM PDT 24
Finished Jul 13 06:38:38 PM PDT 24
Peak memory 196648 kb
Host smart-7c177e21-7edd-4825-908b-95c25dd5fb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900429825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.900429825
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2551068028
Short name T254
Test name
Test status
Simulation time 2002069550 ps
CPU time 1.11 seconds
Started Jul 13 06:38:36 PM PDT 24
Finished Jul 13 06:38:38 PM PDT 24
Peak memory 191764 kb
Host smart-14c6d085-c73a-4ed8-b6a3-b739f07e654e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551068028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2551068028
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.2350984174
Short name T4
Test name
Test status
Simulation time 498009156 ps
CPU time 0.79 seconds
Started Jul 13 06:38:30 PM PDT 24
Finished Jul 13 06:38:33 PM PDT 24
Peak memory 196684 kb
Host smart-c4cc0fb3-1bc3-4f39-91b0-fcc5f6fa2f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350984174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.2350984174
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.588955016
Short name T230
Test name
Test status
Simulation time 38727331570 ps
CPU time 25.38 seconds
Started Jul 13 06:38:36 PM PDT 24
Finished Jul 13 06:39:03 PM PDT 24
Peak memory 191828 kb
Host smart-ddd983cc-76b9-4c81-b98d-a49a889b2db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588955016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.588955016
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.4140071986
Short name T214
Test name
Test status
Simulation time 456595195 ps
CPU time 0.74 seconds
Started Jul 13 06:38:31 PM PDT 24
Finished Jul 13 06:38:33 PM PDT 24
Peak memory 196712 kb
Host smart-9d1fa6f2-9739-4a68-a25f-cf8d1273b8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140071986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.4140071986
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3505571691
Short name T240
Test name
Test status
Simulation time 13509001516 ps
CPU time 19.6 seconds
Started Jul 13 06:38:10 PM PDT 24
Finished Jul 13 06:38:34 PM PDT 24
Peak memory 191920 kb
Host smart-702904ba-782e-4928-8b27-153e32e628b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505571691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3505571691
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2653202971
Short name T19
Test name
Test status
Simulation time 3836753000 ps
CPU time 6.44 seconds
Started Jul 13 06:38:08 PM PDT 24
Finished Jul 13 06:38:19 PM PDT 24
Peak memory 215400 kb
Host smart-c6c4634e-4717-468f-948a-9689fe1518d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653202971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2653202971
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.752993303
Short name T279
Test name
Test status
Simulation time 506750085 ps
CPU time 0.74 seconds
Started Jul 13 06:38:09 PM PDT 24
Finished Jul 13 06:38:14 PM PDT 24
Peak memory 191860 kb
Host smart-724e7b9d-f688-44cd-9a5d-f4516b90b436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752993303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.752993303
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.691677496
Short name T249
Test name
Test status
Simulation time 39759701729 ps
CPU time 58.43 seconds
Started Jul 13 06:38:37 PM PDT 24
Finished Jul 13 06:39:37 PM PDT 24
Peak memory 191744 kb
Host smart-58f54898-aec5-46cf-beaf-b66fdf19bf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691677496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.691677496
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.2504052192
Short name T262
Test name
Test status
Simulation time 487196200 ps
CPU time 1.25 seconds
Started Jul 13 06:38:31 PM PDT 24
Finished Jul 13 06:38:34 PM PDT 24
Peak memory 191864 kb
Host smart-2c4ab048-d15d-4fe3-b914-2767942fbb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504052192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2504052192
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.477889159
Short name T239
Test name
Test status
Simulation time 31714623622 ps
CPU time 10.76 seconds
Started Jul 13 06:38:29 PM PDT 24
Finished Jul 13 06:38:42 PM PDT 24
Peak memory 192124 kb
Host smart-606430fe-00ab-45bb-9194-ac24e53e48a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477889159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.477889159
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2278935112
Short name T21
Test name
Test status
Simulation time 589364141 ps
CPU time 1 seconds
Started Jul 13 06:38:31 PM PDT 24
Finished Jul 13 06:38:33 PM PDT 24
Peak memory 196612 kb
Host smart-68f747c8-e3fa-40bc-8b87-40d1fb4fab4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278935112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2278935112
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.3593063663
Short name T238
Test name
Test status
Simulation time 27237920726 ps
CPU time 7.87 seconds
Started Jul 13 06:38:36 PM PDT 24
Finished Jul 13 06:38:46 PM PDT 24
Peak memory 191968 kb
Host smart-3a85c7d9-206e-4d7f-94fe-6fd11776a343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593063663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.3593063663
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2373952277
Short name T235
Test name
Test status
Simulation time 533045694 ps
CPU time 1.44 seconds
Started Jul 13 06:38:31 PM PDT 24
Finished Jul 13 06:38:34 PM PDT 24
Peak memory 191772 kb
Host smart-782e787f-382d-46d5-a671-56d36fdc3629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373952277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2373952277
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1887166845
Short name T196
Test name
Test status
Simulation time 386217514 ps
CPU time 1.28 seconds
Started Jul 13 06:38:31 PM PDT 24
Finished Jul 13 06:38:34 PM PDT 24
Peak memory 196724 kb
Host smart-94d0b6a7-a551-487c-b12d-7beb6ac73276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887166845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1887166845
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2279332311
Short name T264
Test name
Test status
Simulation time 51750688538 ps
CPU time 80.58 seconds
Started Jul 13 06:38:35 PM PDT 24
Finished Jul 13 06:39:56 PM PDT 24
Peak memory 191828 kb
Host smart-bd85c8af-29fc-49cc-a821-86296363b57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279332311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2279332311
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.1910736129
Short name T282
Test name
Test status
Simulation time 438302228 ps
CPU time 0.72 seconds
Started Jul 13 06:38:31 PM PDT 24
Finished Jul 13 06:38:33 PM PDT 24
Peak memory 191848 kb
Host smart-7476fd24-866b-4d75-91b1-ccb7c030ed1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910736129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1910736129
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.822799673
Short name T224
Test name
Test status
Simulation time 3918010131 ps
CPU time 6.14 seconds
Started Jul 13 06:38:39 PM PDT 24
Finished Jul 13 06:38:48 PM PDT 24
Peak memory 191320 kb
Host smart-ffe6e2aa-64f9-43e9-a827-f9a7f27a2713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822799673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.822799673
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2927669026
Short name T22
Test name
Test status
Simulation time 624793312 ps
CPU time 1.07 seconds
Started Jul 13 06:38:39 PM PDT 24
Finished Jul 13 06:38:42 PM PDT 24
Peak memory 196668 kb
Host smart-02db7c00-1249-41f0-ae60-52ea10bf2155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927669026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2927669026
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_jump.593199240
Short name T44
Test name
Test status
Simulation time 640417294 ps
CPU time 0.72 seconds
Started Jul 13 06:38:38 PM PDT 24
Finished Jul 13 06:38:40 PM PDT 24
Peak memory 196632 kb
Host smart-a59c7fa6-7470-4aa9-b4bd-4be2738ed609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593199240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.593199240
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.3106994362
Short name T259
Test name
Test status
Simulation time 25235404411 ps
CPU time 37.87 seconds
Started Jul 13 06:38:39 PM PDT 24
Finished Jul 13 06:39:19 PM PDT 24
Peak memory 196792 kb
Host smart-ed75fd2a-6c99-4d87-bb81-a3532d952fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106994362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3106994362
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.4071234138
Short name T280
Test name
Test status
Simulation time 374588745 ps
CPU time 0.72 seconds
Started Jul 13 06:38:33 PM PDT 24
Finished Jul 13 06:38:34 PM PDT 24
Peak memory 191864 kb
Host smart-b134237a-a47c-4833-baf0-d67663cee4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071234138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.4071234138
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.109155502
Short name T203
Test name
Test status
Simulation time 6403085070 ps
CPU time 3.01 seconds
Started Jul 13 06:38:30 PM PDT 24
Finished Jul 13 06:38:35 PM PDT 24
Peak memory 191940 kb
Host smart-4200c98b-7abb-4021-aa76-92c26e7c3384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109155502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.109155502
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.3098661059
Short name T165
Test name
Test status
Simulation time 495817067 ps
CPU time 1.28 seconds
Started Jul 13 06:38:32 PM PDT 24
Finished Jul 13 06:38:34 PM PDT 24
Peak memory 196704 kb
Host smart-2efe7e5b-8ab5-4162-9efd-37f94c8b2cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098661059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.3098661059
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1178660202
Short name T191
Test name
Test status
Simulation time 495447957 ps
CPU time 1.01 seconds
Started Jul 13 06:38:40 PM PDT 24
Finished Jul 13 06:38:43 PM PDT 24
Peak memory 196656 kb
Host smart-55fa3207-a14e-44d3-aa9e-2043aa84f1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178660202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1178660202
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.1045567707
Short name T221
Test name
Test status
Simulation time 48606179379 ps
CPU time 70.46 seconds
Started Jul 13 06:38:38 PM PDT 24
Finished Jul 13 06:39:50 PM PDT 24
Peak memory 191920 kb
Host smart-98ec5e4f-f763-4095-bc2f-01021b457fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045567707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1045567707
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.174916358
Short name T255
Test name
Test status
Simulation time 422549783 ps
CPU time 1.19 seconds
Started Jul 13 06:38:39 PM PDT 24
Finished Jul 13 06:38:42 PM PDT 24
Peak memory 196632 kb
Host smart-a7498526-4183-4569-acd2-a341db15ffe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174916358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.174916358
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.3366532199
Short name T50
Test name
Test status
Simulation time 30937260121 ps
CPU time 46.47 seconds
Started Jul 13 06:38:37 PM PDT 24
Finished Jul 13 06:39:25 PM PDT 24
Peak memory 196924 kb
Host smart-f8e1a54a-890a-4ad2-955d-c3ca063e811e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366532199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.3366532199
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.3104632776
Short name T276
Test name
Test status
Simulation time 542845964 ps
CPU time 0.79 seconds
Started Jul 13 06:38:39 PM PDT 24
Finished Jul 13 06:38:42 PM PDT 24
Peak memory 196704 kb
Host smart-85e65e61-80c7-471b-bfbe-c199677f9e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104632776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.3104632776
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.3803427282
Short name T6
Test name
Test status
Simulation time 11254263947 ps
CPU time 3.81 seconds
Started Jul 13 06:38:43 PM PDT 24
Finished Jul 13 06:38:48 PM PDT 24
Peak memory 191876 kb
Host smart-20f21827-2560-4a85-9e42-5af5e3b4718e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803427282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3803427282
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.719041683
Short name T253
Test name
Test status
Simulation time 479237447 ps
CPU time 0.8 seconds
Started Jul 13 06:38:37 PM PDT 24
Finished Jul 13 06:38:39 PM PDT 24
Peak memory 191888 kb
Host smart-62674f1e-1979-4100-9bbb-32b4c2fd650b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719041683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.719041683
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.4110045558
Short name T229
Test name
Test status
Simulation time 24786561658 ps
CPU time 8.48 seconds
Started Jul 13 06:38:12 PM PDT 24
Finished Jul 13 06:38:24 PM PDT 24
Peak memory 196864 kb
Host smart-d0aadf13-2d7e-4c6f-89c4-dce6ea425501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110045558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.4110045558
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.611157850
Short name T222
Test name
Test status
Simulation time 416938318 ps
CPU time 0.73 seconds
Started Jul 13 06:38:12 PM PDT 24
Finished Jul 13 06:38:16 PM PDT 24
Peak memory 191796 kb
Host smart-8ae522d5-46ab-480f-ac46-32b75900eeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611157850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.611157850
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.2237830297
Short name T81
Test name
Test status
Simulation time 24963749360 ps
CPU time 35.95 seconds
Started Jul 13 06:38:10 PM PDT 24
Finished Jul 13 06:38:51 PM PDT 24
Peak memory 192236 kb
Host smart-679b0add-5513-4f4a-a3d8-862cede04366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237830297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.2237830297
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2011822739
Short name T247
Test name
Test status
Simulation time 459867530 ps
CPU time 1.29 seconds
Started Jul 13 06:38:12 PM PDT 24
Finished Jul 13 06:38:17 PM PDT 24
Peak memory 191772 kb
Host smart-d33280f8-07b2-42e7-a3ca-578cf2201ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011822739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2011822739
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.482252803
Short name T49
Test name
Test status
Simulation time 44724370672 ps
CPU time 4.84 seconds
Started Jul 13 06:38:10 PM PDT 24
Finished Jul 13 06:38:19 PM PDT 24
Peak memory 196840 kb
Host smart-db45ded5-cb7b-404a-967c-e891ae4c4b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482252803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.482252803
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.2558882545
Short name T206
Test name
Test status
Simulation time 544765340 ps
CPU time 0.98 seconds
Started Jul 13 06:38:07 PM PDT 24
Finished Jul 13 06:38:12 PM PDT 24
Peak memory 196668 kb
Host smart-307d3589-2ba1-43e4-b9ca-1f5aaa220d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558882545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.2558882545
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2851038156
Short name T283
Test name
Test status
Simulation time 27636092714 ps
CPU time 21.72 seconds
Started Jul 13 06:38:09 PM PDT 24
Finished Jul 13 06:38:35 PM PDT 24
Peak memory 196936 kb
Host smart-030f0e39-47f8-4e11-8e1f-4ccf7983e66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851038156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2851038156
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.4141647901
Short name T228
Test name
Test status
Simulation time 425593772 ps
CPU time 0.74 seconds
Started Jul 13 06:38:08 PM PDT 24
Finished Jul 13 06:38:13 PM PDT 24
Peak memory 191860 kb
Host smart-cdf2fbcd-f357-437b-bf66-fe895134deeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141647901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.4141647901
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.2115990142
Short name T257
Test name
Test status
Simulation time 4446204044 ps
CPU time 6.71 seconds
Started Jul 13 06:38:09 PM PDT 24
Finished Jul 13 06:38:20 PM PDT 24
Peak memory 196884 kb
Host smart-25b9a8e4-b473-4c22-b13b-64c034038fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115990142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2115990142
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.611518959
Short name T223
Test name
Test status
Simulation time 325930299 ps
CPU time 0.98 seconds
Started Jul 13 06:38:09 PM PDT 24
Finished Jul 13 06:38:14 PM PDT 24
Peak memory 191780 kb
Host smart-91bbb1ec-a39a-4403-afe2-34d79150b944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611518959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.611518959
Directory /workspace/9.aon_timer_smoke/latest
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