Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	357591	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4433778	1		T1	15		T2	14		T3	17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1177893	1		T1	1		T2	1		T3	1
values[0x0]	1693785	1		T1	9		T2	12		T3	13
values[0x1]	1919691	1		T1	9		T2	9		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	159081	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4632288	1		T1	15		T2	16		T3	17

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18532	1		T12	1055		T13	713		T17	615
valid_sources[0x01]	18245	1		T12	765		T13	653		T17	447
valid_sources[0x02]	18500	1		T12	713		T13	701		T17	753
valid_sources[0x03]	18185	1		T3	2		T12	729		T13	631
valid_sources[0x04]	18554	1		T12	791		T13	702		T17	712
valid_sources[0x05]	18438	1		T3	2		T12	771		T13	658
valid_sources[0x06]	18944	1		T12	723		T13	715		T17	557
valid_sources[0x07]	18039	1		T4	1		T12	719		T13	600
valid_sources[0x08]	18625	1		T2	1		T12	813		T13	634
valid_sources[0x09]	19394	1		T12	755		T13	687		T17	593
valid_sources[0x0a]	17844	1		T12	454		T13	666		T16	2
valid_sources[0x0b]	18989	1		T3	3		T12	817		T13	675
valid_sources[0x0c]	19334	1		T2	1		T12	911		T13	692
valid_sources[0x0d]	19427	1		T12	710		T13	675		T17	502
valid_sources[0x0e]	19253	1		T12	841		T13	680		T14	1
valid_sources[0x0f]	18390	1		T2	1		T3	3		T10	1
valid_sources[0x10]	19203	1		T7	1		T12	890		T13	699
valid_sources[0x11]	18070	1		T10	20		T12	697		T13	669
valid_sources[0x12]	17499	1		T12	922		T13	660		T15	1
valid_sources[0x13]	18110	1		T12	696		T13	640		T17	666
valid_sources[0x14]	18290	1		T12	688		T13	674		T17	540
valid_sources[0x15]	18840	1		T12	820		T13	672		T17	600
valid_sources[0x16]	18557	1		T12	751		T13	680		T17	631
valid_sources[0x17]	18556	1		T2	1		T7	2		T12	665
valid_sources[0x18]	18779	1		T6	1		T12	849		T13	689
valid_sources[0x19]	18822	1		T12	716		T13	706		T14	1
valid_sources[0x1a]	19306	1		T12	688		T13	671		T15	2
valid_sources[0x1b]	18851	1		T10	10		T12	759		T13	671
valid_sources[0x1c]	19052	1		T10	1		T12	672		T13	684
valid_sources[0x1d]	20295	1		T10	11		T12	988		T13	716
valid_sources[0x1e]	17709	1		T7	1		T9	1		T12	547
valid_sources[0x1f]	17705	1		T6	1		T12	631		T13	674
valid_sources[0x20]	19120	1		T12	729		T13	697		T17	543
valid_sources[0x21]	18801	1		T12	859		T13	668		T17	540
valid_sources[0x22]	17983	1		T12	702		T13	683		T17	606
valid_sources[0x23]	19253	1		T12	764		T13	642		T17	478
valid_sources[0x24]	18850	1		T10	5		T12	762		T13	727
valid_sources[0x25]	18691	1		T12	537		T13	737		T17	606
valid_sources[0x26]	17624	1		T10	3		T12	788		T13	663
valid_sources[0x27]	19135	1		T6	4		T12	694		T13	661
valid_sources[0x28]	18846	1		T12	732		T13	671		T17	582
valid_sources[0x29]	19883	1		T12	680		T13	673		T17	411
valid_sources[0x2a]	18234	1		T9	7		T12	594		T13	731
valid_sources[0x2b]	17358	1		T12	606		T13	633		T17	428
valid_sources[0x2c]	17766	1		T2	1		T9	3		T12	656
valid_sources[0x2d]	18566	1		T7	1		T12	694		T13	651
valid_sources[0x2e]	18781	1		T12	722		T13	665		T17	626
valid_sources[0x2f]	17416	1		T12	695		T13	664		T17	531
valid_sources[0x30]	18851	1		T12	806		T13	710		T17	486
valid_sources[0x31]	18435	1		T12	767		T13	665		T17	527
valid_sources[0x32]	18452	1		T3	1		T12	652		T13	722
valid_sources[0x33]	18445	1		T12	819		T13	687		T17	530
valid_sources[0x34]	18497	1		T12	748		T13	725		T17	455
valid_sources[0x35]	19356	1		T6	2		T12	573		T13	697
valid_sources[0x36]	18446	1		T2	1		T3	1		T12	607
valid_sources[0x37]	18618	1		T12	964		T13	682		T17	517
valid_sources[0x38]	19148	1		T10	4		T12	680		T13	632
valid_sources[0x39]	19647	1		T12	625		T13	642		T17	543
valid_sources[0x3a]	19200	1		T12	752		T13	704		T17	438
valid_sources[0x3b]	19125	1		T2	1		T12	764		T13	659
valid_sources[0x3c]	19093	1		T12	742		T13	668		T17	553
valid_sources[0x3d]	19758	1		T6	1		T12	699		T13	632
valid_sources[0x3e]	18007	1		T10	9		T12	550		T13	682
valid_sources[0x3f]	18121	1		T4	1		T12	821		T13	660
valid_sources[0x40]	19394	1		T12	782		T13	623		T17	611
valid_sources[0x41]	18956	1		T2	1		T4	1		T12	628
valid_sources[0x42]	18905	1		T12	622		T13	674		T17	588
valid_sources[0x43]	19093	1		T4	1		T12	729		T13	670
valid_sources[0x44]	18603	1		T12	643		T13	665		T17	517
valid_sources[0x45]	18954	1		T10	2		T12	742		T13	621
valid_sources[0x46]	17485	1		T12	711		T13	685		T17	503
valid_sources[0x47]	17808	1		T12	588		T13	708		T17	691
valid_sources[0x48]	19361	1		T12	953		T13	706		T17	545
valid_sources[0x49]	19001	1		T12	809		T13	698		T24	3
valid_sources[0x4a]	19056	1		T2	1		T7	2		T12	747
valid_sources[0x4b]	18196	1		T12	750		T13	643		T17	512
valid_sources[0x4c]	18566	1		T12	665		T13	638		T17	622
valid_sources[0x4d]	17343	1		T12	548		T13	703		T24	2
valid_sources[0x4e]	18399	1		T12	575		T13	715		T17	697
valid_sources[0x4f]	17812	1		T12	760		T13	687		T17	539
valid_sources[0x50]	18744	1		T12	660		T13	639		T17	456
valid_sources[0x51]	18462	1		T10	4		T12	672		T13	642
valid_sources[0x52]	17957	1		T12	700		T13	719		T17	567
valid_sources[0x53]	17896	1		T12	726		T13	681		T14	1
valid_sources[0x54]	19722	1		T12	802		T13	728		T17	625
valid_sources[0x55]	18444	1		T12	843		T13	647		T17	475
valid_sources[0x56]	19589	1		T12	820		T13	646		T17	597
valid_sources[0x57]	20366	1		T12	693		T13	670		T17	503
valid_sources[0x58]	19083	1		T12	706		T13	671		T17	471
valid_sources[0x59]	18898	1		T10	6		T12	712		T13	698
valid_sources[0x5a]	18573	1		T12	478		T13	680		T17	594
valid_sources[0x5b]	18836	1		T12	694		T13	672		T17	636
valid_sources[0x5c]	18892	1		T12	647		T13	664		T17	506
valid_sources[0x5d]	18239	1		T12	586		T13	671		T15	1
valid_sources[0x5e]	19346	1		T12	803		T13	664		T17	571
valid_sources[0x5f]	18633	1		T12	718		T13	678		T17	521
valid_sources[0x60]	19358	1		T12	1030		T13	658		T17	635
valid_sources[0x61]	19678	1		T12	648		T13	695		T17	628
valid_sources[0x62]	18204	1		T12	750		T13	653		T17	695
valid_sources[0x63]	18467	1		T9	4		T12	981		T13	627
valid_sources[0x64]	18990	1		T12	738		T13	716		T17	659
valid_sources[0x65]	18116	1		T12	581		T13	689		T16	2
valid_sources[0x66]	18000	1		T2	1		T12	645		T13	710
valid_sources[0x67]	18035	1		T12	672		T13	693		T17	600
valid_sources[0x68]	19571	1		T12	639		T13	677		T17	582
valid_sources[0x69]	18559	1		T12	913		T13	647		T17	428
valid_sources[0x6a]	18576	1		T12	707		T13	612		T17	587
valid_sources[0x6b]	19705	1		T12	779		T13	703		T16	1
valid_sources[0x6c]	18706	1		T12	696		T13	721		T17	557
valid_sources[0x6d]	19199	1		T12	768		T13	644		T17	557
valid_sources[0x6e]	19232	1		T12	852		T13	740		T17	498
valid_sources[0x6f]	18869	1		T10	25		T12	647		T13	711
valid_sources[0x70]	18053	1		T12	735		T13	635		T17	569
valid_sources[0x71]	19162	1		T10	4		T12	636		T13	666
valid_sources[0x72]	19080	1		T7	1		T12	778		T13	669
valid_sources[0x73]	18421	1		T12	1004		T13	679		T16	1
valid_sources[0x74]	17905	1		T6	1		T12	822		T13	636
valid_sources[0x75]	18611	1		T10	1		T12	629		T13	699
valid_sources[0x76]	17834	1		T12	717		T13	646		T17	512
valid_sources[0x77]	17965	1		T12	752		T13	678		T15	1
valid_sources[0x78]	18526	1		T12	964		T13	757		T17	595
valid_sources[0x79]	19155	1		T4	1		T12	780		T13	623
valid_sources[0x7a]	19399	1		T12	545		T13	642		T17	464
valid_sources[0x7b]	19635	1		T5	22		T12	809		T13	662
valid_sources[0x7c]	18898	1		T7	1		T12	854		T13	704
valid_sources[0x7d]	17786	1		T12	699		T13	708		T17	521
valid_sources[0x7e]	17752	1		T12	709		T13	706		T15	1
valid_sources[0x7f]	18315	1		T12	892		T13	675		T17	652
valid_sources[0x80]	18829	1		T2	1		T6	1		T12	585

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1105792

1

T5

1

T7

1

T10

24

values[0x0]

all_enables

biggest_size

1664007

1

T1

8

T2

9

T3

11

values[0x1]

all_enables

biggest_size

1663979

1

T1

7

T2

5

T3

6