Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	737128020	5203383	0	0
wdog_bark_thold_rd_A	737128020	123844	0	0
wdog_bite_thold_rd_A	737128020	110096	0	0
wdog_ctrl_rd_A	737128020	109365	0	0
wdog_regwen_rd_A	737128020	125498	0	0
wkup_ctrl_rd_A	737128020	109654	0	0
wkup_thold_hi_rd_A	737128020	123904	0	0
wkup_thold_lo_rd_A	737128020	107485	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737128020	5203383	0	0
T12	102213	209271	0	0
T13	777093	186438	0	0
T14	384794	0	0	0
T15	936715	0	0	0
T16	15060	0	0	0
T17	489386	157473	0	0
T24	44508	0	0	0
T25	5934	0	0	0
T32	0	126929	0	0
T33	0	103474	0	0
T34	0	202161	0	0
T35	0	59862	0	0
T36	0	69458	0	0
T37	0	124092	0	0
T38	0	123739	0	0
T39	117044	0	0	0
T40	727866	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737128020	123844	0	0
T12	102213	10832	0	0
T13	777093	9698	0	0
T14	384794	0	0	0
T15	936715	0	0	0
T16	15060	0	0	0
T17	489386	0	0	0
T24	44508	0	0	0
T25	5934	0	0	0
T33	0	10579	0	0
T34	0	19587	0	0
T38	0	12683	0	0
T39	117044	0	0	0
T40	727866	0	0	0
T72	0	5627	0	0
T73	0	8633	0	0
T74	0	3022	0	0
T75	0	11307	0	0
T76	0	9109	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737128020	110096	0	0
T12	102213	9291	0	0
T13	777093	8514	0	0
T14	384794	0	0	0
T15	936715	0	0	0
T16	15060	0	0	0
T17	489386	0	0	0
T24	44508	0	0	0
T25	5934	0	0	0
T33	0	9769	0	0
T34	0	18026	0	0
T38	0	11491	0	0
T39	117044	0	0	0
T40	727866	0	0	0
T72	0	4711	0	0
T73	0	7305	0	0
T74	0	2528	0	0
T75	0	9868	0	0
T76	0	7732	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737128020	109365	0	0
T12	102213	9780	0	0
T13	777093	8680	0	0
T14	384794	0	0	0
T15	936715	0	0	0
T16	15060	0	0	0
T17	489386	0	0	0
T24	44508	0	0	0
T25	5934	0	0	0
T33	0	9925	0	0
T34	0	17409	0	0
T38	0	11087	0	0
T39	117044	0	0	0
T40	727866	0	0	0
T72	0	4719	0	0
T73	0	7329	0	0
T74	0	2591	0	0
T75	0	9365	0	0
T76	0	8074	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737128020	125498	0	0
T12	102213	11062	0	0
T13	777093	9947	0	0
T14	384794	0	0	0
T15	936715	0	0	0
T16	15060	0	0	0
T17	489386	0	0	0
T24	44508	0	0	0
T25	5934	0	0	0
T33	0	10678	0	0
T34	0	20422	0	0
T38	0	12435	0	0
T39	117044	0	0	0
T40	727866	0	0	0
T72	0	5545	0	0
T73	0	8347	0	0
T74	0	2943	0	0
T75	0	11524	0	0
T76	0	9325	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737128020	109654	0	0
T12	102213	9335	0	0
T13	777093	8668	0	0
T14	384794	0	0	0
T15	936715	0	0	0
T16	15060	0	0	0
T17	489386	0	0	0
T24	44508	0	0	0
T25	5934	0	0	0
T33	0	9209	0	0
T34	0	18080	0	0
T38	0	11095	0	0
T39	117044	0	0	0
T40	727866	0	0	0
T72	0	4661	0	0
T73	0	7242	0	0
T74	0	2403	0	0
T75	0	9814	0	0
T76	0	8285	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737128020	123904	0	0
T12	102213	10735	0	0
T13	777093	9911	0	0
T14	384794	0	0	0
T15	936715	0	0	0
T16	15060	0	0	0
T17	489386	0	0	0
T24	44508	0	0	0
T25	5934	0	0	0
T33	0	10991	0	0
T34	0	20139	0	0
T38	0	12405	0	0
T39	117044	0	0	0
T40	727866	0	0	0
T72	0	5412	0	0
T73	0	7969	0	0
T74	0	2984	0	0
T75	0	10829	0	0
T76	0	9098	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	737128020	107485	0	0
T12	102213	9012	0	0
T13	777093	8755	0	0
T14	384794	0	0	0
T15	936715	0	0	0
T16	15060	0	0	0
T17	489386	0	0	0
T24	44508	0	0	0
T25	5934	0	0	0
T33	0	9333	0	0
T34	0	17701	0	0
T38	0	10804	0	0
T39	117044	0	0	0
T40	727866	0	0	0
T72	0	4446	0	0
T73	0	7206	0	0
T74	0	2503	0	0
T75	0	9748	0	0
T76	0	7334	0	0