Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	296492	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	3566267	1		T1	281		T2	129973		T3	14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	950766	1		T1	24		T2	34375		T3	1
values[0x0]	1364789	1		T1	184		T2	49608		T3	10
values[0x1]	1547204	1		T1	172		T2	56666		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	133900	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	3728859	1		T1	302		T2	136098		T3	16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14128	1		T1	3		T2	548		T4	65
valid_sources[0x01]	15584	1		T1	2		T2	526		T4	6
valid_sources[0x02]	14652	1		T2	518		T4	145		T9	343
valid_sources[0x03]	14659	1		T1	3		T2	419		T9	354
valid_sources[0x04]	14635	1		T1	6		T2	544		T4	619
valid_sources[0x05]	15187	1		T2	559		T9	329		T11	558
valid_sources[0x06]	15018	1		T2	772		T4	46		T9	430
valid_sources[0x07]	14602	1		T1	2		T2	478		T4	196
valid_sources[0x08]	15271	1		T2	626		T4	611		T9	410
valid_sources[0x09]	15906	1		T1	3		T2	560		T4	3
valid_sources[0x0a]	14557	1		T1	5		T2	806		T4	106
valid_sources[0x0b]	14613	1		T2	559		T4	5		T9	307
valid_sources[0x0c]	15309	1		T2	435		T4	209		T9	420
valid_sources[0x0d]	14837	1		T1	1		T2	489		T4	55
valid_sources[0x0e]	14435	1		T2	376		T9	381		T11	518
valid_sources[0x0f]	15064	1		T2	514		T9	353		T11	502
valid_sources[0x10]	16813	1		T1	1		T2	723		T4	159
valid_sources[0x11]	14501	1		T2	449		T9	337		T11	569
valid_sources[0x12]	15495	1		T2	406		T4	209		T9	375
valid_sources[0x13]	13998	1		T2	362		T9	333		T11	521
valid_sources[0x14]	14886	1		T2	605		T3	3		T4	195
valid_sources[0x15]	14767	1		T2	682		T4	246		T9	383
valid_sources[0x16]	16737	1		T2	424		T4	404		T9	354
valid_sources[0x17]	14749	1		T1	4		T2	602		T4	449
valid_sources[0x18]	15812	1		T2	597		T4	5		T9	369
valid_sources[0x19]	15122	1		T1	7		T2	586		T4	291
valid_sources[0x1a]	17544	1		T2	681		T4	174		T9	427
valid_sources[0x1b]	15201	1		T2	441		T3	1		T4	9
valid_sources[0x1c]	15501	1		T1	1		T2	816		T4	102
valid_sources[0x1d]	14056	1		T2	530		T9	374		T11	554
valid_sources[0x1e]	13877	1		T2	446		T4	130		T9	364
valid_sources[0x1f]	16025	1		T1	4		T2	493		T4	127
valid_sources[0x20]	15777	1		T1	3		T2	635		T4	342
valid_sources[0x21]	16464	1		T2	646		T4	392		T9	342
valid_sources[0x22]	15090	1		T2	571		T9	338		T11	516
valid_sources[0x23]	15689	1		T2	537		T4	155		T9	436
valid_sources[0x24]	15216	1		T1	2		T2	486		T4	273
valid_sources[0x25]	16095	1		T2	698		T4	156		T9	371
valid_sources[0x26]	14071	1		T2	569		T4	1		T9	314
valid_sources[0x27]	15273	1		T2	674		T4	158		T9	377
valid_sources[0x28]	14462	1		T1	5		T2	690		T4	178
valid_sources[0x29]	15073	1		T2	467		T9	355		T11	495
valid_sources[0x2a]	14001	1		T2	554		T4	181		T9	336
valid_sources[0x2b]	15879	1		T2	307		T4	690		T9	374
valid_sources[0x2c]	14677	1		T2	527		T4	112		T9	290
valid_sources[0x2d]	13986	1		T1	4		T2	314		T4	1
valid_sources[0x2e]	14061	1		T2	464		T4	447		T9	417
valid_sources[0x2f]	14977	1		T1	1		T2	656		T4	10
valid_sources[0x30]	16066	1		T2	436		T9	390		T11	520
valid_sources[0x31]	15864	1		T2	681		T4	373		T9	380
valid_sources[0x32]	14380	1		T1	3		T2	525		T4	225
valid_sources[0x33]	13884	1		T2	329		T3	1		T4	186
valid_sources[0x34]	14880	1		T2	493		T4	114		T9	396
valid_sources[0x35]	16388	1		T2	523		T4	6		T9	357
valid_sources[0x36]	14863	1		T1	3		T2	538		T4	204
valid_sources[0x37]	14395	1		T1	8		T2	669		T9	400
valid_sources[0x38]	14872	1		T2	568		T4	729		T9	353
valid_sources[0x39]	15766	1		T2	564		T3	1		T4	95
valid_sources[0x3a]	16144	1		T1	3		T2	420		T4	161
valid_sources[0x3b]	15436	1		T2	649		T4	656		T9	397
valid_sources[0x3c]	15771	1		T1	1		T2	410		T4	235
valid_sources[0x3d]	14107	1		T2	366		T4	140		T9	291
valid_sources[0x3e]	15097	1		T1	2		T2	697		T4	14
valid_sources[0x3f]	15190	1		T1	1		T2	414		T4	148
valid_sources[0x40]	15832	1		T1	11		T2	658		T9	238
valid_sources[0x41]	15399	1		T2	378		T4	56		T9	316
valid_sources[0x42]	14168	1		T2	386		T4	139		T9	248
valid_sources[0x43]	14640	1		T2	772		T4	198		T9	519
valid_sources[0x44]	15327	1		T2	370		T9	333		T11	565
valid_sources[0x45]	16017	1		T1	2		T2	411		T4	71
valid_sources[0x46]	14792	1		T2	498		T4	147		T9	338
valid_sources[0x47]	15266	1		T2	433		T9	454		T11	580
valid_sources[0x48]	15222	1		T2	425		T4	227		T9	463
valid_sources[0x49]	15844	1		T2	503		T4	73		T9	274
valid_sources[0x4a]	14763	1		T2	516		T4	295		T9	456
valid_sources[0x4b]	14986	1		T1	2		T2	501		T4	243
valid_sources[0x4c]	15584	1		T2	632		T4	246		T9	385
valid_sources[0x4d]	14633	1		T2	448		T9	363		T11	534
valid_sources[0x4e]	16646	1		T1	4		T2	625		T4	246
valid_sources[0x4f]	14728	1		T2	748		T9	363		T11	450
valid_sources[0x50]	15992	1		T2	614		T4	2		T7	290
valid_sources[0x51]	15626	1		T1	6		T2	505		T4	338
valid_sources[0x52]	14222	1		T2	505		T4	210		T9	305
valid_sources[0x53]	14675	1		T2	603		T4	641		T9	326
valid_sources[0x54]	14042	1		T1	2		T2	805		T4	4
valid_sources[0x55]	14274	1		T1	2		T2	557		T4	286
valid_sources[0x56]	15997	1		T1	8		T2	485		T4	65
valid_sources[0x57]	15883	1		T1	4		T2	724		T9	499
valid_sources[0x58]	16716	1		T2	436		T4	2		T9	366
valid_sources[0x59]	14554	1		T1	1		T2	507		T4	3
valid_sources[0x5a]	14891	1		T1	13		T2	450		T4	149
valid_sources[0x5b]	14861	1		T1	2		T2	591		T6	1
valid_sources[0x5c]	15059	1		T2	410		T3	1		T4	555
valid_sources[0x5d]	16131	1		T1	9		T2	732		T3	4
valid_sources[0x5e]	15591	1		T1	1		T2	545		T4	107
valid_sources[0x5f]	14480	1		T1	2		T2	379		T4	302
valid_sources[0x60]	15824	1		T1	4		T2	678		T4	4
valid_sources[0x61]	14888	1		T2	397		T4	1		T9	357
valid_sources[0x62]	14447	1		T2	561		T9	283		T11	574
valid_sources[0x63]	14963	1		T2	690		T4	91		T9	441
valid_sources[0x64]	15274	1		T2	471		T4	127		T9	355
valid_sources[0x65]	14093	1		T2	401		T4	54		T9	328
valid_sources[0x66]	15748	1		T2	416		T4	491		T9	389
valid_sources[0x67]	15713	1		T2	732		T4	269		T6	1
valid_sources[0x68]	14135	1		T1	9		T2	661		T4	1
valid_sources[0x69]	13825	1		T1	4		T2	677		T4	191
valid_sources[0x6a]	14936	1		T2	715		T4	153		T9	417
valid_sources[0x6b]	15260	1		T2	611		T9	372		T11	512
valid_sources[0x6c]	15410	1		T1	4		T2	319		T4	258
valid_sources[0x6d]	14968	1		T1	2		T2	613		T4	154
valid_sources[0x6e]	15901	1		T2	556		T4	457		T9	393
valid_sources[0x6f]	14763	1		T1	7		T2	416		T4	199
valid_sources[0x70]	15939	1		T2	583		T4	1		T9	404
valid_sources[0x71]	17375	1		T1	3		T2	722		T3	1
valid_sources[0x72]	15656	1		T1	3		T2	593		T4	70
valid_sources[0x73]	15779	1		T2	599		T4	3		T6	3
valid_sources[0x74]	14353	1		T1	1		T2	628		T9	453
valid_sources[0x75]	15838	1		T2	609		T4	153		T9	367
valid_sources[0x76]	15112	1		T2	621		T4	288		T9	345
valid_sources[0x77]	15618	1		T2	538		T4	370		T9	361
valid_sources[0x78]	14123	1		T2	598		T4	97		T9	337
valid_sources[0x79]	15049	1		T1	2		T2	489		T3	1
valid_sources[0x7a]	15230	1		T2	507		T4	4		T9	372
valid_sources[0x7b]	15455	1		T1	2		T2	487		T9	418
valid_sources[0x7c]	15117	1		T1	2		T2	657		T4	227
valid_sources[0x7d]	13819	1		T2	451		T4	189		T9	327
valid_sources[0x7e]	14790	1		T2	525		T9	344		T11	555
valid_sources[0x7f]	16425	1		T1	3		T2	494		T4	114
valid_sources[0x80]	14969	1		T2	444		T9	506		T11	595

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

889841

1

T1

12

T2

32417

T4

9116

values[0x0]

all_enables

biggest_size

1338973

1

T1

133

T2

48855

T3

8

values[0x1]

all_enables

biggest_size

1337453

1

T1

136

T2

48701

T3

6