Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	692968774	4248065	0	0
wdog_bark_thold_rd_A	692968774	106334	0	0
wdog_bite_thold_rd_A	692968774	92050	0	0
wdog_ctrl_rd_A	692968774	91989	0	0
wdog_regwen_rd_A	692968774	107006	0	0
wkup_ctrl_rd_A	692968774	93000	0	0
wkup_thold_hi_rd_A	692968774	106131	0	0
wkup_thold_lo_rd_A	692968774	94443	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692968774	4248065	0	0
T2	586369	158575	0	0
T3	54476	0	0	0
T4	198916	42075	0	0
T5	36725	0	0	0
T6	12941	0	0	0
T7	116107	0	0	0
T8	584635	0	0	0
T9	556862	113781	0	0
T10	15771	0	0	0
T11	575550	158938	0	0
T12	0	152783	0	0
T34	0	84092	0	0
T35	0	26267	0	0
T36	0	316481	0	0
T37	0	54410	0	0
T38	0	111460	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692968774	106334	0	0
T12	662977	15235	0	0
T13	334663	0	0	0
T14	898602	0	0	0
T34	369414	4728	0	0
T35	112241	2102	0	0
T39	32701	0	0	0
T40	331735	0	0	0
T52	0	4170	0	0
T81	0	3660	0	0
T84	57614	0	0	0
T85	0	12289	0	0
T86	0	2664	0	0
T87	0	21059	0	0
T88	0	4505	0	0
T89	0	4130	0	0
T90	34110	0	0	0
T91	452027	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692968774	92050	0	0
T12	662977	13175	0	0
T13	334663	0	0	0
T14	898602	0	0	0
T34	369414	3934	0	0
T35	112241	1916	0	0
T39	32701	0	0	0
T40	331735	0	0	0
T52	0	3651	0	0
T81	0	2986	0	0
T84	57614	0	0	0
T85	0	10752	0	0
T86	0	2227	0	0
T87	0	18455	0	0
T88	0	3809	0	0
T89	0	3280	0	0
T90	34110	0	0	0
T91	452027	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692968774	91989	0	0
T12	662977	13416	0	0
T13	334663	0	0	0
T14	898602	0	0	0
T34	369414	3973	0	0
T35	112241	1941	0	0
T39	32701	0	0	0
T40	331735	0	0	0
T52	0	3370	0	0
T81	0	3209	0	0
T84	57614	0	0	0
T85	0	10801	0	0
T86	0	2130	0	0
T87	0	17712	0	0
T88	0	4056	0	0
T89	0	3574	0	0
T90	34110	0	0	0
T91	452027	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692968774	107006	0	0
T12	662977	15304	0	0
T13	334663	0	0	0
T14	898602	0	0	0
T34	369414	5247	0	0
T35	112241	2526	0	0
T39	32701	0	0	0
T40	331735	0	0	0
T52	0	4193	0	0
T81	0	3316	0	0
T84	57614	0	0	0
T85	0	12393	0	0
T86	0	2346	0	0
T87	0	20887	0	0
T88	0	4856	0	0
T89	0	3655	0	0
T90	34110	0	0	0
T91	452027	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692968774	93000	0	0
T12	662977	13626	0	0
T13	334663	0	0	0
T14	898602	0	0	0
T34	369414	4189	0	0
T35	112241	2168	0	0
T39	32701	0	0	0
T40	331735	0	0	0
T52	0	3300	0	0
T81	0	3144	0	0
T84	57614	0	0	0
T85	0	10616	0	0
T86	0	2224	0	0
T87	0	18021	0	0
T88	0	4168	0	0
T89	0	3261	0	0
T90	34110	0	0	0
T91	452027	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692968774	106131	0	0
T12	662977	14841	0	0
T13	334663	0	0	0
T14	898602	0	0	0
T34	369414	4730	0	0
T35	112241	2332	0	0
T39	32701	0	0	0
T40	331735	0	0	0
T52	0	4170	0	0
T81	0	3789	0	0
T84	57614	0	0	0
T85	0	12129	0	0
T86	0	2514	0	0
T87	0	21001	0	0
T88	0	4517	0	0
T89	0	3965	0	0
T90	34110	0	0	0
T91	452027	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692968774	94443	0	0
T12	662977	13893	0	0
T13	334663	0	0	0
T14	898602	0	0	0
T34	369414	4290	0	0
T35	112241	2119	0	0
T39	32701	0	0	0
T40	331735	0	0	0
T52	0	3707	0	0
T81	0	3377	0	0
T84	57614	0	0	0
T85	0	10772	0	0
T86	0	2160	0	0
T87	0	18549	0	0
T88	0	4242	0	0
T89	0	3307	0	0
T90	34110	0	0	0
T91	452027	0	0	0