Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	444138	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	5527105	1		T1	12		T2	16		T3	146675

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1469064	1		T1	1		T2	1		T3	39218
values[0x0]	2109333	1		T1	5		T2	10		T3	55755
values[0x1]	2392846	1		T1	12		T2	11		T3	63398

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	195713	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	5775530	1		T1	13		T2	17		T3	153281

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23469	1		T3	605		T4	1042		T5	5
valid_sources[0x01]	24468	1		T3	638		T4	1001		T7	9
valid_sources[0x02]	23806	1		T1	3		T3	579		T4	1061
valid_sources[0x03]	22368	1		T3	585		T4	1042		T5	6
valid_sources[0x04]	24970	1		T3	591		T4	984		T5	1
valid_sources[0x05]	22038	1		T3	646		T4	995		T5	3
valid_sources[0x06]	22669	1		T3	585		T4	1003		T7	1
valid_sources[0x07]	23343	1		T3	631		T4	963		T33	3
valid_sources[0x08]	21901	1		T2	1		T3	604		T4	1020
valid_sources[0x09]	23355	1		T3	658		T4	1023		T15	2
valid_sources[0x0a]	21846	1		T3	651		T4	1005		T5	5
valid_sources[0x0b]	21982	1		T3	621		T4	1010		T5	2
valid_sources[0x0c]	22679	1		T3	641		T4	1070		T7	2
valid_sources[0x0d]	23120	1		T3	646		T4	922		T32	3
valid_sources[0x0e]	23672	1		T3	557		T4	981		T33	1
valid_sources[0x0f]	23549	1		T3	634		T4	1035		T11	2
valid_sources[0x10]	23895	1		T3	700		T4	995		T6	3
valid_sources[0x11]	24084	1		T3	648		T4	1001		T6	22
valid_sources[0x12]	24229	1		T3	613		T4	990		T6	10
valid_sources[0x13]	24743	1		T3	623		T4	1014		T6	1
valid_sources[0x14]	24158	1		T3	707		T4	1045		T15	2
valid_sources[0x15]	22617	1		T3	642		T4	1050		T5	3
valid_sources[0x16]	25422	1		T3	603		T4	959		T6	1
valid_sources[0x17]	23250	1		T3	566		T4	983		T6	1
valid_sources[0x18]	24060	1		T3	629		T4	1001		T5	18
valid_sources[0x19]	22786	1		T3	610		T4	1017		T32	3
valid_sources[0x1a]	21184	1		T3	644		T4	1060		T5	1
valid_sources[0x1b]	23126	1		T3	624		T4	977		T7	5
valid_sources[0x1c]	22548	1		T3	647		T4	991		T7	1
valid_sources[0x1d]	24151	1		T3	619		T4	1029		T6	1
valid_sources[0x1e]	24173	1		T3	647		T4	993		T5	2
valid_sources[0x1f]	23820	1		T3	601		T4	980		T6	2
valid_sources[0x20]	22255	1		T3	572		T4	1009		T32	1
valid_sources[0x21]	24249	1		T3	591		T4	1078		T5	2
valid_sources[0x22]	22445	1		T1	1		T3	663		T4	1020
valid_sources[0x23]	23155	1		T3	610		T4	1016		T33	2
valid_sources[0x24]	21839	1		T3	625		T4	1023		T6	1
valid_sources[0x25]	22049	1		T3	616		T4	986		T7	2
valid_sources[0x26]	24459	1		T3	630		T4	991		T5	2
valid_sources[0x27]	21862	1		T3	584		T4	964		T7	2
valid_sources[0x28]	22532	1		T3	624		T4	990		T6	3
valid_sources[0x29]	22502	1		T3	613		T4	1002		T32	2
valid_sources[0x2a]	23553	1		T3	628		T4	992		T6	1
valid_sources[0x2b]	23768	1		T3	624		T4	1046		T14	1
valid_sources[0x2c]	23442	1		T3	622		T4	1061		T6	1
valid_sources[0x2d]	24187	1		T3	624		T4	1068		T10	1
valid_sources[0x2e]	23307	1		T3	645		T4	1074		T32	3
valid_sources[0x2f]	23553	1		T3	599		T4	1014		T33	1
valid_sources[0x30]	23049	1		T3	590		T4	1029		T5	3
valid_sources[0x31]	22350	1		T3	641		T4	961		T6	7
valid_sources[0x32]	21438	1		T3	720		T4	1006		T32	1
valid_sources[0x33]	22150	1		T3	630		T4	1012		T5	11
valid_sources[0x34]	23282	1		T3	635		T4	956		T5	1
valid_sources[0x35]	23046	1		T3	632		T4	1056		T5	2
valid_sources[0x36]	22890	1		T3	661		T4	986		T5	7
valid_sources[0x37]	23045	1		T3	587		T4	1049		T5	2
valid_sources[0x38]	23639	1		T3	633		T4	985		T33	3
valid_sources[0x39]	23067	1		T3	592		T4	1042		T7	1
valid_sources[0x3a]	22387	1		T3	626		T4	1041		T13	284
valid_sources[0x3b]	22017	1		T3	603		T4	1025		T5	5
valid_sources[0x3c]	22355	1		T3	627		T4	1058		T32	1
valid_sources[0x3d]	26216	1		T1	1		T3	666		T4	988
valid_sources[0x3e]	23601	1		T3	599		T4	985		T32	3
valid_sources[0x3f]	21077	1		T3	637		T4	1019		T5	4
valid_sources[0x40]	24381	1		T3	631		T4	1028		T7	6
valid_sources[0x41]	24914	1		T3	618		T4	977		T5	2
valid_sources[0x42]	23744	1		T3	660		T4	971		T5	2
valid_sources[0x43]	22762	1		T3	700		T4	1057		T17	1209
valid_sources[0x44]	22022	1		T3	607		T4	979		T5	3
valid_sources[0x45]	22313	1		T3	589		T4	983		T32	3
valid_sources[0x46]	23913	1		T3	585		T4	974		T16	3
valid_sources[0x47]	24134	1		T3	644		T4	1037		T33	1
valid_sources[0x48]	24586	1		T3	580		T4	1031		T5	2
valid_sources[0x49]	22050	1		T3	631		T4	1002		T32	7
valid_sources[0x4a]	22941	1		T3	554		T4	1044		T32	1
valid_sources[0x4b]	24249	1		T3	669		T4	987		T7	1
valid_sources[0x4c]	23557	1		T3	621		T4	980		T5	10
valid_sources[0x4d]	22520	1		T3	576		T4	1038		T32	4
valid_sources[0x4e]	22898	1		T3	597		T4	1009		T32	1
valid_sources[0x4f]	22054	1		T3	597		T4	999		T7	3
valid_sources[0x50]	21933	1		T2	1		T3	607		T4	967
valid_sources[0x51]	25445	1		T3	603		T4	1021		T5	5
valid_sources[0x52]	23321	1		T3	622		T4	989		T7	2
valid_sources[0x53]	23867	1		T3	624		T4	991		T16	3
valid_sources[0x54]	23876	1		T2	3		T3	626		T4	984
valid_sources[0x55]	23216	1		T3	591		T4	972		T5	2
valid_sources[0x56]	23058	1		T3	618		T4	1061		T6	1
valid_sources[0x57]	24655	1		T3	593		T4	1006		T6	3
valid_sources[0x58]	23251	1		T1	4		T3	627		T4	960
valid_sources[0x59]	22349	1		T3	609		T4	1009		T6	3
valid_sources[0x5a]	21856	1		T3	636		T4	1004		T6	14
valid_sources[0x5b]	22325	1		T3	594		T4	956		T7	1
valid_sources[0x5c]	22805	1		T3	673		T4	1037		T7	4
valid_sources[0x5d]	24354	1		T3	659		T4	976		T7	2
valid_sources[0x5e]	22464	1		T3	552		T4	932		T6	12
valid_sources[0x5f]	22283	1		T3	626		T4	1022		T33	2
valid_sources[0x60]	22039	1		T3	589		T4	965		T7	2
valid_sources[0x61]	24360	1		T3	567		T4	1003		T33	3
valid_sources[0x62]	24041	1		T3	576		T4	1006		T5	9
valid_sources[0x63]	26111	1		T3	625		T4	1066		T7	1
valid_sources[0x64]	25359	1		T3	597		T4	1036		T32	4
valid_sources[0x65]	22354	1		T3	590		T4	1003		T6	4
valid_sources[0x66]	24060	1		T3	599		T4	988		T33	3
valid_sources[0x67]	23169	1		T3	582		T4	1009		T14	1
valid_sources[0x68]	24053	1		T3	600		T4	1037		T5	3
valid_sources[0x69]	21991	1		T3	590		T4	1018		T5	2
valid_sources[0x6a]	23020	1		T3	603		T4	1052		T32	3
valid_sources[0x6b]	22460	1		T3	598		T4	1030		T6	8
valid_sources[0x6c]	24052	1		T3	677		T4	1053		T5	5
valid_sources[0x6d]	23331	1		T3	653		T4	1018		T7	3
valid_sources[0x6e]	23782	1		T3	635		T4	1001		T38	1
valid_sources[0x6f]	22396	1		T3	595		T4	1002		T7	1
valid_sources[0x70]	22173	1		T3	602		T4	1013		T32	2
valid_sources[0x71]	22960	1		T3	676		T4	973		T5	4
valid_sources[0x72]	22883	1		T3	605		T4	984		T6	1
valid_sources[0x73]	22165	1		T3	601		T4	978		T6	3
valid_sources[0x74]	22920	1		T3	644		T4	997		T5	2
valid_sources[0x75]	24561	1		T3	585		T4	954		T14	1
valid_sources[0x76]	22338	1		T1	1		T3	578		T4	998
valid_sources[0x77]	24314	1		T3	582		T4	1079		T5	5
valid_sources[0x78]	22149	1		T3	593		T4	1015		T5	6
valid_sources[0x79]	24662	1		T3	632		T4	941		T5	7
valid_sources[0x7a]	22762	1		T2	2		T3	601		T4	1018
valid_sources[0x7b]	23584	1		T3	609		T4	1046		T6	4
valid_sources[0x7c]	24675	1		T3	674		T4	1000		T5	10
valid_sources[0x7d]	24639	1		T3	579		T4	976		T32	5
valid_sources[0x7e]	24676	1		T3	645		T4	1012		T16	8
valid_sources[0x7f]	23950	1		T3	589		T4	989		T6	2
valid_sources[0x80]	24596	1		T3	673		T4	1048		T5	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1380293

1

T1

1

T2

1

T3

36857

values[0x0]

all_enables

biggest_size

2073609

1

T1

3

T2

7

T3

54916

values[0x1]

all_enables

biggest_size

2073203

1

T1

8

T2

8

T3

54902