Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	818537715	6567028	0	0
wdog_bark_thold_rd_A	818537715	138316	0	0
wdog_bite_thold_rd_A	818537715	120663	0	0
wdog_ctrl_rd_A	818537715	121667	0	0
wdog_regwen_rd_A	818537715	137558	0	0
wkup_ctrl_rd_A	818537715	121114	0	0
wkup_thold_hi_rd_A	818537715	138144	0	0
wkup_thold_lo_rd_A	818537715	121603	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	818537715	6567028	0	0
T3	492890	181665	0	0
T4	805533	299639	0	0
T5	102624	0	0	0
T6	118919	0	0	0
T7	267461	0	0	0
T8	52681	0	0	0
T9	19784	0	0	0
T10	42000	0	0	0
T11	454275	0	0	0
T12	8538	0	0	0
T17	0	342700	0	0
T42	0	34860	0	0
T43	0	20346	0	0
T44	0	88591	0	0
T45	0	43595	0	0
T46	0	172148	0	0
T47	0	188117	0	0
T48	0	96889	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	818537715	138316	0	0
T30	0	7295	0	0
T43	934933	1823	0	0
T44	339847	0	0	0
T45	162896	0	0	0
T80	0	27464	0	0
T85	0	3672	0	0
T86	0	7982	0	0
T87	0	4563	0	0
T88	0	16563	0	0
T89	0	10571	0	0
T90	0	9760	0	0
T91	0	13553	0	0
T92	244631	0	0	0
T93	119892	0	0	0
T94	13117	0	0	0
T95	14447	0	0	0
T96	169934	0	0	0
T97	54657	0	0	0
T98	943344	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	818537715	120663	0	0
T30	0	6199	0	0
T43	934933	1612	0	0
T44	339847	0	0	0
T45	162896	0	0	0
T80	0	24245	0	0
T85	0	2933	0	0
T86	0	6610	0	0
T87	0	4213	0	0
T88	0	14533	0	0
T89	0	9507	0	0
T90	0	8423	0	0
T91	0	11613	0	0
T92	244631	0	0	0
T93	119892	0	0	0
T94	13117	0	0	0
T95	14447	0	0	0
T96	169934	0	0	0
T97	54657	0	0	0
T98	943344	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	818537715	121667	0	0
T30	0	6373	0	0
T43	934933	1567	0	0
T44	339847	0	0	0
T45	162896	0	0	0
T80	0	24900	0	0
T85	0	3109	0	0
T86	0	6886	0	0
T87	0	4037	0	0
T88	0	14139	0	0
T89	0	8844	0	0
T90	0	8496	0	0
T91	0	11819	0	0
T92	244631	0	0	0
T93	119892	0	0	0
T94	13117	0	0	0
T95	14447	0	0	0
T96	169934	0	0	0
T97	54657	0	0	0
T98	943344	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	818537715	137558	0	0
T30	0	7317	0	0
T43	934933	1765	0	0
T44	339847	0	0	0
T45	162896	0	0	0
T80	0	28138	0	0
T85	0	3591	0	0
T86	0	7801	0	0
T87	0	4533	0	0
T88	0	16590	0	0
T89	0	10220	0	0
T90	0	9678	0	0
T91	0	12986	0	0
T92	244631	0	0	0
T93	119892	0	0	0
T94	13117	0	0	0
T95	14447	0	0	0
T96	169934	0	0	0
T97	54657	0	0	0
T98	943344	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	818537715	121114	0	0
T30	0	6515	0	0
T43	934933	1556	0	0
T44	339847	0	0	0
T45	162896	0	0	0
T80	0	24344	0	0
T85	0	2930	0	0
T86	0	6893	0	0
T87	0	4164	0	0
T88	0	14552	0	0
T89	0	9119	0	0
T90	0	8308	0	0
T91	0	11501	0	0
T92	244631	0	0	0
T93	119892	0	0	0
T94	13117	0	0	0
T95	14447	0	0	0
T96	169934	0	0	0
T97	54657	0	0	0
T98	943344	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	818537715	138144	0	0
T30	0	7275	0	0
T43	934933	1572	0	0
T44	339847	0	0	0
T45	162896	0	0	0
T80	0	27607	0	0
T85	0	3276	0	0
T86	0	7645	0	0
T87	0	4742	0	0
T88	0	16538	0	0
T89	0	10913	0	0
T90	0	9237	0	0
T91	0	13162	0	0
T92	244631	0	0	0
T93	119892	0	0	0
T94	13117	0	0	0
T95	14447	0	0	0
T96	169934	0	0	0
T97	54657	0	0	0
T98	943344	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	818537715	121603	0	0
T30	0	6304	0	0
T43	934933	1594	0	0
T44	339847	0	0	0
T45	162896	0	0	0
T80	0	24426	0	0
T85	0	3077	0	0
T86	0	6573	0	0
T87	0	4194	0	0
T88	0	14301	0	0
T89	0	9253	0	0
T90	0	8393	0	0
T91	0	12212	0	0
T92	244631	0	0	0
T93	119892	0	0	0
T94	13117	0	0	0
T95	14447	0	0	0
T96	169934	0	0	0
T97	54657	0	0	0
T98	943344	0	0	0