Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	33010	1		T1	413		T2	12		T3	1113
bark[1]	280	1		T43	21		T23	30		T27	14
bark[2]	232	1		T22	26		T136	56		T88	21
bark[3]	344	1		T11	14		T181	40		T25	14
bark[4]	359	1		T32	21		T108	47		T147	21
bark[5]	378	1		T30	21		T90	28		T92	21
bark[6]	1059	1		T14	21		T32	21		T108	26
bark[7]	125	1		T162	14		T112	48		T155	21
bark[8]	1018	1		T13	21		T14	339		T30	238
bark[9]	426	1		T10	14		T14	165		T52	14
bark[10]	418	1		T86	29		T91	144		T99	39
bark[11]	439	1		T32	31		T42	68		T136	137
bark[12]	605	1		T13	21		T91	7		T109	14
bark[13]	1363	1		T7	14		T30	26		T158	14
bark[14]	555	1		T47	21		T86	286		T23	21
bark[15]	372	1		T14	21		T91	21		T109	30
bark[16]	255	1		T13	21		T42	14		T156	14
bark[17]	363	1		T14	21		T47	21		T48	21
bark[18]	454	1		T49	21		T44	41		T186	14
bark[19]	392	1		T14	21		T30	137		T48	21
bark[20]	271	1		T11	42		T48	35		T113	14
bark[21]	951	1		T46	14		T136	21		T157	5
bark[22]	657	1		T41	7		T48	21		T137	14
bark[23]	1284	1		T41	241		T185	14		T134	40
bark[24]	866	1		T3	66		T11	21		T32	21
bark[25]	580	1		T3	21		T48	21		T42	26
bark[26]	533	1		T86	150		T106	21		T154	241
bark[27]	414	1		T32	30		T43	21		T90	7
bark[28]	483	1		T42	21		T108	21		T148	14
bark[29]	456	1		T50	14		T42	5		T28	14
bark[30]	220	1		T134	21		T105	35		T122	21
bark[31]	535	1		T8	91		T32	21		T42	21
bark_0	4658	1		T1	58		T2	7		T3	93

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	32527	1		T1	377		T2	11		T3	1106
bite[1]	378	1		T9	13		T11	21		T13	42
bite[2]	368	1		T156	13		T88	21		T99	21
bite[3]	322	1		T25	13		T109	52		T105	72
bite[4]	1101	1		T41	240		T49	89		T52	13
bite[5]	1885	1		T8	65		T14	21		T32	21
bite[6]	859	1		T108	47		T88	21		T106	21
bite[7]	751	1		T1	31		T14	21		T48	21
bite[8]	80	1		T41	6		T91	6		T88	26
bite[9]	266	1		T32	30		T113	13		T44	4
bite[10]	187	1		T32	21		T48	34		T115	21
bite[11]	246	1		T3	21		T30	21		T147	21
bite[12]	87	1		T11	13		T186	13		T187	13
bite[13]	277	1		T48	21		T42	13		T137	13
bite[14]	846	1		T8	26		T14	224		T30	136
bite[15]	370	1		T11	42		T14	68		T32	21
bite[16]	1283	1		T14	44		T43	121		T86	255
bite[17]	593	1		T48	21		T86	21		T90	6
bite[18]	413	1		T14	164		T148	13		T103	22
bite[19]	450	1		T47	21		T27	13		T89	21
bite[20]	692	1		T13	21		T49	21		T134	40
bite[21]	464	1		T127	21		T134	53		T109	13
bite[22]	496	1		T42	47		T108	26		T136	21
bite[23]	380	1		T10	13		T46	13		T30	25
bite[24]	154	1		T32	21		T50	13		T134	21
bite[25]	129	1		T42	21		T147	13		T167	13
bite[26]	470	1		T86	288		T90	27		T128	21
bite[27]	354	1		T7	13		T86	264		T146	13
bite[28]	407	1		T3	65		T14	21		T32	30
bite[29]	520	1		T47	21		T43	21		T149	21
bite[30]	314	1		T43	21		T45	21		T99	42
bite[31]	1542	1		T14	21		T30	237		T108	82
bite_0	5144	1		T1	63		T2	8		T3	101

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	46191	1		T1	471		T2	19		T3	970
auto[1]	8164	1		T3	323		T11	61		T29	7

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	1780	1		T1	77		T3	61		T13	9
prescale[1]	1424	1		T30	24		T31	124		T43	45
prescale[2]	1184	1		T1	28		T2	9		T3	138
prescale[3]	681	1		T1	63		T13	46		T14	51
prescale[4]	617	1		T3	2		T8	19		T14	19
prescale[5]	991	1		T5	9		T30	19		T47	19
prescale[6]	817	1		T14	14		T31	19		T42	2
prescale[7]	912	1		T8	19		T42	100		T43	19
prescale[8]	1066	1		T1	2		T3	36		T11	42
prescale[9]	677	1		T30	9		T31	2		T43	70
prescale[10]	803	1		T11	24		T41	2		T32	19
prescale[11]	1773	1		T1	41		T3	82		T11	41
prescale[12]	1187	1		T3	40		T8	19		T14	172
prescale[13]	855	1		T1	28		T14	2		T30	21
prescale[14]	370	1		T1	19		T3	40		T30	4
prescale[15]	847	1		T8	9		T11	44		T13	28
prescale[16]	790	1		T3	2		T8	88		T48	49
prescale[17]	1001	1		T3	66		T14	2		T30	81
prescale[18]	607	1		T3	68		T31	2		T47	19
prescale[19]	838	1		T14	2		T30	142		T31	2
prescale[20]	677	1		T3	57		T30	45		T43	45
prescale[21]	1044	1		T11	19		T49	49		T108	44
prescale[22]	1188	1		T3	28		T8	19		T30	40
prescale[23]	1036	1		T30	71		T47	19		T42	90
prescale[24]	733	1		T3	2		T13	71		T31	19
prescale[25]	966	1		T3	2		T30	113		T42	40
prescale[26]	426	1		T3	19		T6	9		T14	9
prescale[27]	1348	1		T3	49		T30	49		T31	132
prescale[28]	869	1		T1	36		T3	85		T8	19
prescale[29]	385	1		T1	2		T3	60		T14	2
prescale[30]	416	1		T31	2		T91	4		T136	2
prescale[31]	1342	1		T3	222		T30	28		T47	19
prescale_0	24705	1		T1	175		T2	10		T3	234

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	41866	1		T1	363		T2	19		T3	1105
auto[1]	12489	1		T1	108		T3	188		T6	10

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	54355	1		T1	471		T2	19		T3	1293

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	31733	1		T1	304		T2	14		T3	697
wkup[1]	325	1		T41	21		T43	21		T147	21
wkup[2]	355	1		T3	21		T32	21		T43	26
wkup[3]	290	1		T52	15		T43	21		T86	26
wkup[4]	472	1		T3	42		T8	26		T13	21
wkup[5]	193	1		T44	8		T170	21		T145	40
wkup[6]	237	1		T30	21		T31	21		T43	51
wkup[7]	135	1		T30	15		T43	21		T86	21
wkup[8]	255	1		T3	15		T42	21		T108	21
wkup[9]	207	1		T14	21		T31	21		T49	21
wkup[10]	171	1		T13	21		T109	15		T88	42
wkup[11]	315	1		T11	21		T42	21		T45	21
wkup[12]	298	1		T41	8		T47	21		T27	15
wkup[13]	266	1		T3	30		T14	21		T43	30
wkup[14]	341	1		T3	21		T42	21		T86	31
wkup[15]	244	1		T3	21		T11	21		T14	21
wkup[16]	306	1		T32	21		T45	21		T86	21
wkup[17]	173	1		T90	8		T186	15		T109	30
wkup[18]	349	1		T14	21		T43	30		T86	21
wkup[19]	477	1		T13	35		T14	21		T32	35
wkup[20]	248	1		T134	21		T44	21		T147	21
wkup[21]	356	1		T48	15		T108	21		T43	42
wkup[22]	288	1		T42	21		T108	21		T43	30
wkup[23]	394	1		T14	21		T43	26		T44	21
wkup[24]	254	1		T3	21		T86	21		T20	15
wkup[25]	204	1		T48	21		T42	21		T108	21
wkup[26]	426	1		T3	21		T14	21		T41	30
wkup[27]	372	1		T3	73		T43	42		T147	21
wkup[28]	208	1		T43	21		T44	21		T86	21
wkup[29]	292	1		T32	21		T42	49		T86	30
wkup[30]	343	1		T14	21		T30	26		T43	59
wkup[31]	194	1		T14	21		T42	6		T86	21
wkup[32]	482	1		T3	42		T49	21		T148	15
wkup[33]	200	1		T14	21		T90	8		T28	15
wkup[34]	290	1		T30	21		T113	15		T44	21
wkup[35]	188	1		T86	42		T91	21		T109	21
wkup[36]	258	1		T1	21		T47	21		T174	15
wkup[37]	304	1		T32	21		T147	21		T86	42
wkup[38]	197	1		T3	21		T30	35		T42	21
wkup[39]	238	1		T3	21		T8	26		T42	29
wkup[40]	264	1		T43	21		T181	21		T136	30
wkup[41]	253	1		T30	21		T42	31		T43	21
wkup[42]	343	1		T14	26		T31	21		T41	21
wkup[43]	466	1		T1	20		T44	6		T86	21
wkup[44]	277	1		T1	21		T86	21		T23	21
wkup[45]	263	1		T11	21		T30	21		T32	30
wkup[46]	510	1		T10	15		T14	21		T91	21
wkup[47]	487	1		T3	21		T7	15		T30	31
wkup[48]	252	1		T1	31		T30	30		T136	56
wkup[49]	282	1		T14	21		T44	31		T86	42
wkup[50]	253	1		T3	26		T47	21		T49	21
wkup[51]	430	1		T14	21		T30	42		T41	21
wkup[52]	324	1		T1	26		T108	26		T86	21
wkup[53]	424	1		T3	30		T11	21		T30	21
wkup[54]	245	1		T3	30		T46	15		T14	8
wkup[55]	223	1		T3	21		T14	21		T30	21
wkup[56]	201	1		T3	21		T30	21		T185	15
wkup[57]	385	1		T30	44		T41	30		T47	21
wkup[58]	405	1		T30	21		T42	26		T43	21
wkup[59]	373	1		T14	26		T30	21		T31	30
wkup[60]	267	1		T30	21		T42	21		T108	42
wkup[61]	237	1		T48	26		T86	30		T91	21
wkup[62]	267	1		T42	8		T86	21		T136	21
wkup[63]	396	1		T3	21		T9	15		T11	15
wkup_0	3650	1		T1	48		T2	5		T3	77