---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	3820059	0	0	422
tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	3820059	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertsKnown_A	0	0	728687124	728268001	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	728687124	70	0	0
tb.dut.IntrWdogKnown_A	0	0	728687124	728268001	0	0
tb.dut.IntrWkupKnown_A	0	0	728687124	728268001	0	0
tb.dut.RstReqKnown_A	0	0	3766977	3708183	0	0
tb.dut.TlOAReadyKnown_A	0	0	728687124	728268001	0	0
tb.dut.TlODValidKnown_A	0	0	728687124	728268001	0	0
tb.dut.WkupReqKnown_A	0	0	3766977	3708183	0	0
tb.dut.aon_timer_csr_assert.TlulOOBAddrErr_A	0	0	743124653	5982113	0	0
tb.dut.aon_timer_csr_assert.wdog_bark_thold_rd_A	0	0	743124653	112649	0	0
tb.dut.aon_timer_csr_assert.wdog_bite_thold_rd_A	0	0	743124653	98222	0	0
tb.dut.aon_timer_csr_assert.wdog_ctrl_rd_A	0	0	743124653	97026	0	0
tb.dut.aon_timer_csr_assert.wdog_regwen_rd_A	0	0	743124653	113317	0	0
tb.dut.aon_timer_csr_assert.wkup_ctrl_rd_A	0	0	743124653	98164	0	0
tb.dut.aon_timer_csr_assert.wkup_thold_hi_rd_A	0	0	743124653	112297	0	0
tb.dut.aon_timer_csr_assert.wkup_thold_lo_rd_A	0	0	743124653	97810	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	743124653	34500816	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	743124653	742631875	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	743124653	742631875	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	743124653	27472765	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	743124653	742631875	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	743124653	742631875	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[205].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[207].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[211].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[212].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[213].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[214].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[215].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[216].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[217].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[218].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[219].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[21].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[220].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[221].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[222].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[223].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[224].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[225].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[226].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[227].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[228].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[229].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[22].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[231].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[232].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[233].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[234].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[235].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[236].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[237].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[238].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[23].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[241].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
tb.dut.tlul_assert_device.gen_assert_final[242].noOutstandingReqsAtEndOfSim_A	0	0	422	422	0	0
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tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	743124653	4119941	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	743124915	1952710	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	743124915	19583	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	743124653	4660698	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	743124915	34500816	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	743124915	27472765	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	743124915	34500816	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	743124915	27472765	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	743124915	27472765	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	743124915	27472765	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	743124653	2426731	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	743124653	1631251	0	0
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tb.dut.u_intr_hw.IntrTKind_A	0	0	247	247	0	0
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tb.dut.u_lc_sync_escalate_en.OutputsKnown_A	0	0	3766977	3708183	0	0
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tb.dut.u_reg.en2addrHit	0	0	743124653	438951	0	0
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tb.dut.u_reg.u_wdog_bite_thold_cdc.BusySrcReqChk_A	0	0	743124653	2471097	0	0
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tb.dut.u_reg.u_wdog_bite_thold_cdc.SrcBusyKnown_A	0	0	743124653	742631875	0	0
tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	743124653	3524	0	0
tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	3820059	3524	0	0
tb.dut.u_reg.u_wdog_bite_thold_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	3820059	3323	0	0
tb.dut.u_reg.u_wdog_bite_thold_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	743124653	3549	0	0
tb.dut.u_reg.u_wdog_count_cdc.BusySrcReqChk_A	0	0	743124653	4872403	0	0
tb.dut.u_reg.u_wdog_count_cdc.DstReqKnown_A	0	0	3820059	3724830	0	0
tb.dut.u_reg.u_wdog_count_cdc.SrcAckBusyChk_A	0	0	743124653	6322	0	0
tb.dut.u_reg.u_wdog_count_cdc.SrcBusyKnown_A	0	0	743124653	742631875	0	0
tb.dut.u_reg.u_wdog_count_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	3820059	436	0	422
tb.dut.u_reg.u_wdog_count_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	3820059	498	0	0
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tb.dut.u_reg.u_wdog_count_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	3820059	6137	0	0
tb.dut.u_reg.u_wdog_count_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	743124653	6381	0	0
tb.dut.u_reg.u_wdog_ctrl_cdc.BusySrcReqChk_A	0	0	743124653	3817772	0	0
tb.dut.u_reg.u_wdog_ctrl_cdc.DstReqKnown_A	0	0	3820059	3724830	0	0
tb.dut.u_reg.u_wdog_ctrl_cdc.SrcAckBusyChk_A	0	0	743124653	5187	0	0
tb.dut.u_reg.u_wdog_ctrl_cdc.SrcBusyKnown_A	0	0	743124653	742631875	0	0
tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	743124653	5187	0	0
tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	3820059	5187	0	0
tb.dut.u_reg.u_wdog_ctrl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	3820059	4997	0	0
tb.dut.u_reg.u_wdog_ctrl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	743124653	5229	0	0
tb.dut.u_reg.u_wkup_cause_cdc.BusySrcReqChk_A	0	0	743124653	2261883	0	0
tb.dut.u_reg.u_wkup_cause_cdc.DstReqKnown_A	0	0	3820059	3724830	0	0
tb.dut.u_reg.u_wkup_cause_cdc.SrcAckBusyChk_A	0	0	743124653	2815	0	0
tb.dut.u_reg.u_wkup_cause_cdc.SrcBusyKnown_A	0	0	743124653	742631875	0	0
tb.dut.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	3820059	1358	0	422
tb.dut.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	3820059	1442	0	0
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tb.dut.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	3820059	2492	0	0
tb.dut.u_reg.u_wkup_cause_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	3820059	2642	0	0
tb.dut.u_reg.u_wkup_cause_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	743124653	2855	0	0
tb.dut.u_reg.u_wkup_count_hi_cdc.BusySrcReqChk_A	0	0	743124653	4735187	0	0
tb.dut.u_reg.u_wkup_count_hi_cdc.DstReqKnown_A	0	0	3820059	3724830	0	0
tb.dut.u_reg.u_wkup_count_hi_cdc.SrcAckBusyChk_A	0	0	743124653	6338	0	0
tb.dut.u_reg.u_wkup_count_hi_cdc.SrcBusyKnown_A	0	0	743124653	742631875	0	0
tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	743124653	6338	0	0
tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	3820059	4368	0	0
tb.dut.u_reg.u_wkup_count_hi_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	3820059	6148	0	0
tb.dut.u_reg.u_wkup_count_hi_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	743124653	6384	0	0
tb.dut.u_reg.u_wkup_count_lo_cdc.BusySrcReqChk_A	0	0	743124653	5206283	0	0
tb.dut.u_reg.u_wkup_count_lo_cdc.DstReqKnown_A	0	0	3820059	3724830	0	0
tb.dut.u_reg.u_wkup_count_lo_cdc.SrcAckBusyChk_A	0	0	743124653	6299	0	0
tb.dut.u_reg.u_wkup_count_lo_cdc.SrcBusyKnown_A	0	0	743124653	742631875	0	0
tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	3820059	3260	0	422
tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	3820059	3380	0	0
tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	743124653	9689	0	0
tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	3820059	4968	0	0
tb.dut.u_reg.u_wkup_count_lo_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	3820059	6135	0	0
tb.dut.u_reg.u_wkup_count_lo_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	743124653	6375	0	0
tb.dut.u_reg.u_wkup_ctrl_cdc.BusySrcReqChk_A	0	0	743124653	4880504	0	0
tb.dut.u_reg.u_wkup_ctrl_cdc.DstReqKnown_A	0	0	3820059	3724830	0	0
tb.dut.u_reg.u_wkup_ctrl_cdc.SrcAckBusyChk_A	0	0	743124653	6798	0	0
tb.dut.u_reg.u_wkup_ctrl_cdc.SrcBusyKnown_A	0	0	743124653	742631875	0	0
tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	743124653	6798	0	0
tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	3820059	6798	0	0
tb.dut.u_reg.u_wkup_ctrl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	3820059	6590	0	0
tb.dut.u_reg.u_wkup_ctrl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	743124653	6837	0	0
tb.dut.u_reg.u_wkup_thold_hi_cdc.BusySrcReqChk_A	0	0	743124653	2476960	0	0
tb.dut.u_reg.u_wkup_thold_hi_cdc.DstReqKnown_A	0	0	3820059	3724830	0	0
tb.dut.u_reg.u_wkup_thold_hi_cdc.SrcAckBusyChk_A	0	0	743124653	3499	0	0
tb.dut.u_reg.u_wkup_thold_hi_cdc.SrcBusyKnown_A	0	0	743124653	742631875	0	0
tb.dut.u_reg.u_wkup_thold_hi_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	743124653	3499	0	0
tb.dut.u_reg.u_wkup_thold_hi_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	3820059	3499	0	0
tb.dut.u_reg.u_wkup_thold_hi_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	3820059	3301	0	0
tb.dut.u_reg.u_wkup_thold_hi_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	743124653	3526	0	0
tb.dut.u_reg.u_wkup_thold_lo_cdc.BusySrcReqChk_A	0	0	743124653	2493582	0	0
tb.dut.u_reg.u_wkup_thold_lo_cdc.DstReqKnown_A	0	0	3820059	3724830	0	0
tb.dut.u_reg.u_wkup_thold_lo_cdc.SrcAckBusyChk_A	0	0	743124653	3514	0	0
tb.dut.u_reg.u_wkup_thold_lo_cdc.SrcBusyKnown_A	0	0	743124653	742631875	0	0
tb.dut.u_reg.u_wkup_thold_lo_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	743124653	3514	0	0
tb.dut.u_reg.u_wkup_thold_lo_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	3820059	3514	0	0
tb.dut.u_reg.u_wkup_thold_lo_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	3820059	3314	0	0
tb.dut.u_reg.u_wkup_thold_lo_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	743124653	3539	0	0
tb.dut.u_reg.wePulse	0	0	743124653	344378	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_lc_sync_escalate_en.gen_flops.OutputDelay_A	0	0	3766977	3705331	0	736
tb.dut.u_reg.u_wdog_count_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	3820059	436	0	422
tb.dut.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	3820059	1358	0	422
tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	3820059	0	0	422
tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	3820059	3260	0	422

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	743124915	237909	237909	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	743124915	742	742	7
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	743124915	1863	1863	7
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	743124915	1119	1119	7
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	743124915	1768	1768	7
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	743124915	909	909	7
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	743124915	1147	1147	7
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	743124915	1347	1347	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	743124915	2177	2177	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	743124915	15039	15039	301

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	743124915	237909	237909	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	743124915	742	742	7
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	743124915	1863	1863	7
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	743124915	1119	1119	7
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	743124915	1768	1768	7
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	743124915	909	909	7
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	743124915	1147	1147	7
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	743124915	1347	1347	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	743124915	2177	2177	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	743124915	15039	15039	301