Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.09 99.33 93.67 100.00 98.40 99.51 49.64


Total test records in report: 422
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T34 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3383483877 Jul 17 07:04:31 PM PDT 24 Jul 17 07:04:35 PM PDT 24 482518568 ps
T285 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2217878685 Jul 17 07:04:50 PM PDT 24 Jul 17 07:04:54 PM PDT 24 308951487 ps
T39 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1297108720 Jul 17 07:04:24 PM PDT 24 Jul 17 07:04:26 PM PDT 24 539474304 ps
T286 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2921413248 Jul 17 07:04:55 PM PDT 24 Jul 17 07:04:57 PM PDT 24 471379537 ps
T287 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2154730883 Jul 17 07:04:31 PM PDT 24 Jul 17 07:04:35 PM PDT 24 610956322 ps
T288 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3937921609 Jul 17 07:04:45 PM PDT 24 Jul 17 07:04:48 PM PDT 24 340538772 ps
T35 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2823954889 Jul 17 07:04:32 PM PDT 24 Jul 17 07:04:36 PM PDT 24 1317763146 ps
T289 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2287819681 Jul 17 07:04:45 PM PDT 24 Jul 17 07:04:47 PM PDT 24 530290305 ps
T40 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.4030221002 Jul 17 07:04:27 PM PDT 24 Jul 17 07:04:32 PM PDT 24 738979078 ps
T290 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2552896617 Jul 17 07:03:57 PM PDT 24 Jul 17 07:04:01 PM PDT 24 461224616 ps
T56 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.514571318 Jul 17 07:07:52 PM PDT 24 Jul 17 07:08:03 PM PDT 24 544945066 ps
T195 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3277167782 Jul 17 07:04:27 PM PDT 24 Jul 17 07:04:30 PM PDT 24 553138908 ps
T80 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1432007588 Jul 17 07:04:32 PM PDT 24 Jul 17 07:04:36 PM PDT 24 1372088143 ps
T291 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2879144178 Jul 17 07:04:32 PM PDT 24 Jul 17 07:04:36 PM PDT 24 322555603 ps
T57 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3272800170 Jul 17 07:04:45 PM PDT 24 Jul 17 07:04:49 PM PDT 24 491046181 ps
T292 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2760697765 Jul 17 07:04:07 PM PDT 24 Jul 17 07:04:11 PM PDT 24 281724478 ps
T81 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.4158852882 Jul 17 07:04:46 PM PDT 24 Jul 17 07:04:52 PM PDT 24 3222941635 ps
T58 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.4104911124 Jul 17 07:04:26 PM PDT 24 Jul 17 07:04:29 PM PDT 24 467635975 ps
T293 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.200956407 Jul 17 07:04:29 PM PDT 24 Jul 17 07:04:33 PM PDT 24 508453724 ps
T294 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1132186230 Jul 17 07:04:46 PM PDT 24 Jul 17 07:04:51 PM PDT 24 598766563 ps
T295 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.136332421 Jul 17 07:04:47 PM PDT 24 Jul 17 07:04:53 PM PDT 24 1104800841 ps
T82 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.869774372 Jul 17 07:04:32 PM PDT 24 Jul 17 07:04:37 PM PDT 24 2334869148 ps
T65 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1206498367 Jul 17 07:04:28 PM PDT 24 Jul 17 07:04:49 PM PDT 24 13515831351 ps
T296 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.267736221 Jul 17 07:04:29 PM PDT 24 Jul 17 07:04:32 PM PDT 24 318210279 ps
T83 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1943340062 Jul 17 07:04:47 PM PDT 24 Jul 17 07:04:55 PM PDT 24 1787995781 ps
T84 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2876392812 Jul 17 07:04:35 PM PDT 24 Jul 17 07:04:40 PM PDT 24 1178535914 ps
T297 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2624238400 Jul 17 07:04:30 PM PDT 24 Jul 17 07:04:35 PM PDT 24 298694379 ps
T298 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3816549989 Jul 17 07:04:55 PM PDT 24 Jul 17 07:04:58 PM PDT 24 404257660 ps
T299 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.4078646314 Jul 17 07:04:29 PM PDT 24 Jul 17 07:04:34 PM PDT 24 519504851 ps
T300 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3084722404 Jul 17 07:04:49 PM PDT 24 Jul 17 07:04:53 PM PDT 24 425092684 ps
T301 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.39988004 Jul 17 07:04:28 PM PDT 24 Jul 17 07:04:31 PM PDT 24 571390509 ps
T302 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.230510470 Jul 17 07:04:55 PM PDT 24 Jul 17 07:04:57 PM PDT 24 461684589 ps
T303 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3455179252 Jul 17 07:04:34 PM PDT 24 Jul 17 07:04:38 PM PDT 24 326451149 ps
T304 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.428297499 Jul 17 07:04:58 PM PDT 24 Jul 17 07:05:00 PM PDT 24 486608044 ps
T36 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1146606456 Jul 17 07:04:34 PM PDT 24 Jul 17 07:04:46 PM PDT 24 4524245319 ps
T305 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.4074963572 Jul 17 07:04:46 PM PDT 24 Jul 17 07:04:50 PM PDT 24 287665442 ps
T306 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3536177607 Jul 17 07:04:24 PM PDT 24 Jul 17 07:04:27 PM PDT 24 636197042 ps
T85 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1012228548 Jul 17 07:04:35 PM PDT 24 Jul 17 07:04:39 PM PDT 24 1421962188 ps
T37 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2818436344 Jul 17 07:04:25 PM PDT 24 Jul 17 07:04:32 PM PDT 24 4301376540 ps
T38 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3246177047 Jul 17 07:04:30 PM PDT 24 Jul 17 07:04:46 PM PDT 24 8293657001 ps
T307 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1576003347 Jul 17 07:04:48 PM PDT 24 Jul 17 07:04:53 PM PDT 24 474651810 ps
T308 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2138753480 Jul 17 07:04:49 PM PDT 24 Jul 17 07:04:54 PM PDT 24 285523645 ps
T309 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3018317687 Jul 17 07:04:45 PM PDT 24 Jul 17 07:04:47 PM PDT 24 452403872 ps
T310 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.4071674386 Jul 17 07:04:27 PM PDT 24 Jul 17 07:04:32 PM PDT 24 1077540828 ps
T311 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2687041190 Jul 17 07:04:24 PM PDT 24 Jul 17 07:04:25 PM PDT 24 368543528 ps
T312 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3334961396 Jul 17 07:04:52 PM PDT 24 Jul 17 07:04:55 PM PDT 24 296753340 ps
T313 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.996071257 Jul 17 07:04:26 PM PDT 24 Jul 17 07:04:31 PM PDT 24 1375337765 ps
T314 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.4290828760 Jul 17 07:04:55 PM PDT 24 Jul 17 07:04:57 PM PDT 24 314749361 ps
T59 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.365825113 Jul 17 07:04:45 PM PDT 24 Jul 17 07:04:48 PM PDT 24 509214173 ps
T190 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3901565882 Jul 17 07:04:33 PM PDT 24 Jul 17 07:04:38 PM PDT 24 4403455566 ps
T66 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3554636662 Jul 17 07:04:31 PM PDT 24 Jul 17 07:04:42 PM PDT 24 12804631975 ps
T315 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3230141646 Jul 17 07:04:51 PM PDT 24 Jul 17 07:05:00 PM PDT 24 4647565639 ps
T316 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1114863343 Jul 17 07:04:23 PM PDT 24 Jul 17 07:04:24 PM PDT 24 554763462 ps
T193 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1675819539 Jul 17 07:04:33 PM PDT 24 Jul 17 07:04:50 PM PDT 24 8144509615 ps
T60 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.479857455 Jul 17 07:04:27 PM PDT 24 Jul 17 07:04:35 PM PDT 24 4372712972 ps
T317 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3707520831 Jul 17 07:04:24 PM PDT 24 Jul 17 07:04:27 PM PDT 24 2240349972 ps
T318 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1780479924 Jul 17 07:04:48 PM PDT 24 Jul 17 07:05:06 PM PDT 24 8314706078 ps
T319 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.968341102 Jul 17 07:04:46 PM PDT 24 Jul 17 07:04:49 PM PDT 24 428062918 ps
T320 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.4250044852 Jul 17 07:04:45 PM PDT 24 Jul 17 07:04:47 PM PDT 24 1423184926 ps
T321 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2574739550 Jul 17 07:04:27 PM PDT 24 Jul 17 07:04:32 PM PDT 24 1514611200 ps
T322 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3718956609 Jul 17 07:04:49 PM PDT 24 Jul 17 07:04:53 PM PDT 24 399661303 ps
T323 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.175240615 Jul 17 07:04:49 PM PDT 24 Jul 17 07:04:54 PM PDT 24 387067464 ps
T324 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1865200007 Jul 17 07:04:34 PM PDT 24 Jul 17 07:04:39 PM PDT 24 4114155484 ps
T325 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1926934102 Jul 17 07:04:48 PM PDT 24 Jul 17 07:04:52 PM PDT 24 498059895 ps
T326 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3088370143 Jul 17 07:04:35 PM PDT 24 Jul 17 07:04:39 PM PDT 24 365160886 ps
T327 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1369114265 Jul 17 07:04:50 PM PDT 24 Jul 17 07:04:54 PM PDT 24 340726585 ps
T328 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3550013672 Jul 17 07:04:47 PM PDT 24 Jul 17 07:04:51 PM PDT 24 429374604 ps
T329 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3931209004 Jul 17 07:04:28 PM PDT 24 Jul 17 07:04:32 PM PDT 24 332706375 ps
T330 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1202666630 Jul 17 07:04:45 PM PDT 24 Jul 17 07:04:48 PM PDT 24 900449934 ps
T331 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1969183779 Jul 17 07:04:46 PM PDT 24 Jul 17 07:04:50 PM PDT 24 416833556 ps
T67 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3704222699 Jul 17 07:04:35 PM PDT 24 Jul 17 07:04:39 PM PDT 24 488358008 ps
T332 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2860120477 Jul 17 07:04:26 PM PDT 24 Jul 17 07:04:28 PM PDT 24 433609940 ps
T333 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3746648970 Jul 17 07:04:35 PM PDT 24 Jul 17 07:04:39 PM PDT 24 485996741 ps
T334 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1398506964 Jul 17 07:04:25 PM PDT 24 Jul 17 07:04:28 PM PDT 24 635537460 ps
T335 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.769916852 Jul 17 07:04:28 PM PDT 24 Jul 17 07:04:31 PM PDT 24 402183944 ps
T336 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.148534147 Jul 17 07:04:48 PM PDT 24 Jul 17 07:04:53 PM PDT 24 363274019 ps
T194 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3064261120 Jul 17 07:04:46 PM PDT 24 Jul 17 07:04:57 PM PDT 24 8213320587 ps
T191 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.493552811 Jul 17 07:04:48 PM PDT 24 Jul 17 07:05:06 PM PDT 24 8545326881 ps
T61 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1802722543 Jul 17 07:04:27 PM PDT 24 Jul 17 07:04:31 PM PDT 24 531623627 ps
T337 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2055398201 Jul 17 07:04:46 PM PDT 24 Jul 17 07:04:57 PM PDT 24 4180304548 ps
T338 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1272821834 Jul 17 07:04:30 PM PDT 24 Jul 17 07:04:34 PM PDT 24 471858902 ps
T339 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2299338517 Jul 17 07:04:50 PM PDT 24 Jul 17 07:04:55 PM PDT 24 326963725 ps
T340 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.4027929541 Jul 17 07:04:36 PM PDT 24 Jul 17 07:04:39 PM PDT 24 599187987 ps
T192 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.768398124 Jul 17 07:04:25 PM PDT 24 Jul 17 07:04:39 PM PDT 24 8381452044 ps
T341 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.445145133 Jul 17 07:04:45 PM PDT 24 Jul 17 07:04:47 PM PDT 24 452633101 ps
T342 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1598657769 Jul 17 07:04:47 PM PDT 24 Jul 17 07:04:52 PM PDT 24 439703673 ps
T343 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.839922223 Jul 17 07:04:25 PM PDT 24 Jul 17 07:04:28 PM PDT 24 1421363756 ps
T68 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2583669654 Jul 17 07:04:32 PM PDT 24 Jul 17 07:04:37 PM PDT 24 493801955 ps
T344 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.312084449 Jul 17 07:04:31 PM PDT 24 Jul 17 07:04:35 PM PDT 24 436943933 ps
T69 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1258762187 Jul 17 07:04:48 PM PDT 24 Jul 17 07:04:53 PM PDT 24 441753810 ps
T345 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3103027457 Jul 17 07:04:36 PM PDT 24 Jul 17 07:04:39 PM PDT 24 503788633 ps
T346 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.312671222 Jul 17 07:04:47 PM PDT 24 Jul 17 07:04:52 PM PDT 24 1326266505 ps
T347 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1822505535 Jul 17 07:04:24 PM PDT 24 Jul 17 07:04:26 PM PDT 24 498157457 ps
T348 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.4271368854 Jul 17 07:04:30 PM PDT 24 Jul 17 07:04:34 PM PDT 24 4354669378 ps
T349 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1007346639 Jul 17 07:04:23 PM PDT 24 Jul 17 07:04:26 PM PDT 24 494795423 ps
T350 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1968120031 Jul 17 07:04:51 PM PDT 24 Jul 17 07:04:56 PM PDT 24 648691195 ps
T62 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1288393490 Jul 17 07:04:29 PM PDT 24 Jul 17 07:04:36 PM PDT 24 4681735831 ps
T351 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2417451723 Jul 17 07:04:30 PM PDT 24 Jul 17 07:04:34 PM PDT 24 504478527 ps
T352 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1552146320 Jul 17 07:04:58 PM PDT 24 Jul 17 07:05:00 PM PDT 24 438376333 ps
T353 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1479012904 Jul 17 07:04:26 PM PDT 24 Jul 17 07:04:29 PM PDT 24 343204349 ps
T354 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3230256856 Jul 17 07:04:48 PM PDT 24 Jul 17 07:04:54 PM PDT 24 4680308438 ps
T355 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.863141267 Jul 17 07:04:35 PM PDT 24 Jul 17 07:04:42 PM PDT 24 1154322976 ps
T356 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2072543888 Jul 17 07:04:33 PM PDT 24 Jul 17 07:04:37 PM PDT 24 401350495 ps
T357 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1201525764 Jul 17 07:04:28 PM PDT 24 Jul 17 07:04:31 PM PDT 24 480918395 ps
T358 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1058006925 Jul 17 07:04:24 PM PDT 24 Jul 17 07:04:28 PM PDT 24 4254229251 ps
T359 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3954825543 Jul 17 07:03:56 PM PDT 24 Jul 17 07:03:59 PM PDT 24 471131140 ps
T63 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1261603298 Jul 17 07:04:34 PM PDT 24 Jul 17 07:04:37 PM PDT 24 354118160 ps
T360 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.408485537 Jul 17 07:04:49 PM PDT 24 Jul 17 07:04:54 PM PDT 24 315164622 ps
T361 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3115125308 Jul 17 07:04:26 PM PDT 24 Jul 17 07:04:28 PM PDT 24 424197032 ps
T362 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3249392303 Jul 17 07:04:28 PM PDT 24 Jul 17 07:04:34 PM PDT 24 1139583790 ps
T363 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2416654413 Jul 17 07:04:27 PM PDT 24 Jul 17 07:04:30 PM PDT 24 622745524 ps
T364 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3706432771 Jul 17 07:04:32 PM PDT 24 Jul 17 07:04:36 PM PDT 24 506585016 ps
T365 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1272250408 Jul 17 07:04:31 PM PDT 24 Jul 17 07:04:35 PM PDT 24 1006772942 ps
T366 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.892630802 Jul 17 07:04:30 PM PDT 24 Jul 17 07:04:34 PM PDT 24 396346968 ps
T367 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.713368512 Jul 17 07:04:28 PM PDT 24 Jul 17 07:04:33 PM PDT 24 554916150 ps
T368 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.915077194 Jul 17 07:04:48 PM PDT 24 Jul 17 07:04:52 PM PDT 24 327710948 ps
T369 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2648786203 Jul 17 07:04:32 PM PDT 24 Jul 17 07:04:36 PM PDT 24 682902008 ps
T370 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1085922748 Jul 17 07:04:33 PM PDT 24 Jul 17 07:04:38 PM PDT 24 739335118 ps
T371 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3650808448 Jul 17 07:04:24 PM PDT 24 Jul 17 07:04:26 PM PDT 24 5006277784 ps
T372 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3018898464 Jul 17 07:04:49 PM PDT 24 Jul 17 07:04:54 PM PDT 24 386875432 ps
T373 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.841737018 Jul 17 07:04:48 PM PDT 24 Jul 17 07:04:57 PM PDT 24 2578568674 ps
T374 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.607182516 Jul 17 07:04:55 PM PDT 24 Jul 17 07:04:58 PM PDT 24 419975121 ps
T375 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1433115586 Jul 17 07:04:35 PM PDT 24 Jul 17 07:04:40 PM PDT 24 1548671951 ps
T64 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.182107891 Jul 17 07:04:45 PM PDT 24 Jul 17 07:04:49 PM PDT 24 534894652 ps
T376 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3857237267 Jul 17 07:04:36 PM PDT 24 Jul 17 07:04:39 PM PDT 24 596403136 ps
T377 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3767202983 Jul 17 07:04:28 PM PDT 24 Jul 17 07:04:32 PM PDT 24 440819030 ps
T378 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2442857742 Jul 17 07:04:34 PM PDT 24 Jul 17 07:04:38 PM PDT 24 449722679 ps
T379 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2179067928 Jul 17 07:04:07 PM PDT 24 Jul 17 07:04:25 PM PDT 24 8297893130 ps
T380 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3337845242 Jul 17 07:04:36 PM PDT 24 Jul 17 07:04:40 PM PDT 24 487138650 ps
T381 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2579878407 Jul 17 07:04:26 PM PDT 24 Jul 17 07:04:29 PM PDT 24 497599414 ps
T382 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3072673761 Jul 17 07:04:35 PM PDT 24 Jul 17 07:04:44 PM PDT 24 4060388073 ps
T383 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3100505030 Jul 17 07:04:09 PM PDT 24 Jul 17 07:04:14 PM PDT 24 357413594 ps
T384 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.199620634 Jul 17 07:04:36 PM PDT 24 Jul 17 07:04:39 PM PDT 24 322888063 ps
T385 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2726668167 Jul 17 07:04:34 PM PDT 24 Jul 17 07:04:38 PM PDT 24 1299196490 ps
T386 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2477066010 Jul 17 07:04:31 PM PDT 24 Jul 17 07:04:35 PM PDT 24 434758764 ps
T387 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3136275651 Jul 17 07:04:33 PM PDT 24 Jul 17 07:04:40 PM PDT 24 8440438074 ps
T388 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2363558177 Jul 17 07:04:35 PM PDT 24 Jul 17 07:04:38 PM PDT 24 293980643 ps
T389 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2038500977 Jul 17 07:04:28 PM PDT 24 Jul 17 07:04:32 PM PDT 24 1255713761 ps
T390 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1714152609 Jul 17 07:04:35 PM PDT 24 Jul 17 07:04:39 PM PDT 24 480013094 ps
T391 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2309285694 Jul 17 07:04:46 PM PDT 24 Jul 17 07:04:50 PM PDT 24 461609575 ps
T392 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2751274998 Jul 17 07:04:47 PM PDT 24 Jul 17 07:04:51 PM PDT 24 427109944 ps
T393 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2155294644 Jul 17 07:04:28 PM PDT 24 Jul 17 07:04:31 PM PDT 24 439920437 ps
T394 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3325700735 Jul 17 07:04:25 PM PDT 24 Jul 17 07:04:28 PM PDT 24 1995712121 ps
T395 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3656380888 Jul 17 07:04:23 PM PDT 24 Jul 17 07:04:24 PM PDT 24 317595785 ps
T396 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3023691195 Jul 17 07:04:34 PM PDT 24 Jul 17 07:04:39 PM PDT 24 1376964739 ps
T397 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.946943370 Jul 17 07:04:50 PM PDT 24 Jul 17 07:04:56 PM PDT 24 491015592 ps
T398 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1009204375 Jul 17 07:04:44 PM PDT 24 Jul 17 07:04:45 PM PDT 24 539567300 ps
T399 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.4085791440 Jul 17 07:04:34 PM PDT 24 Jul 17 07:04:39 PM PDT 24 719909872 ps
T400 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.4121879635 Jul 17 07:04:30 PM PDT 24 Jul 17 07:04:34 PM PDT 24 493759456 ps
T401 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3011912553 Jul 17 07:04:46 PM PDT 24 Jul 17 07:04:51 PM PDT 24 521237395 ps
T402 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2935367362 Jul 17 07:04:58 PM PDT 24 Jul 17 07:04:59 PM PDT 24 324401493 ps
T403 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2331072551 Jul 17 07:04:48 PM PDT 24 Jul 17 07:04:52 PM PDT 24 482080634 ps
T404 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.290198922 Jul 17 07:04:36 PM PDT 24 Jul 17 07:04:39 PM PDT 24 304912025 ps
T405 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2074401785 Jul 17 07:04:45 PM PDT 24 Jul 17 07:04:48 PM PDT 24 686163488 ps
T406 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3845205583 Jul 17 07:04:32 PM PDT 24 Jul 17 07:04:37 PM PDT 24 451842390 ps
T407 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2563274795 Jul 17 07:04:31 PM PDT 24 Jul 17 07:04:34 PM PDT 24 569610088 ps
T408 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.786605842 Jul 17 07:04:52 PM PDT 24 Jul 17 07:04:56 PM PDT 24 477020266 ps
T409 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2848456894 Jul 17 07:04:46 PM PDT 24 Jul 17 07:04:50 PM PDT 24 340027105 ps
T410 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.4218886306 Jul 17 07:04:45 PM PDT 24 Jul 17 07:04:49 PM PDT 24 384401974 ps
T411 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3750872580 Jul 17 07:04:48 PM PDT 24 Jul 17 07:04:52 PM PDT 24 532572861 ps
T412 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2513589832 Jul 17 07:04:29 PM PDT 24 Jul 17 07:04:34 PM PDT 24 8590535828 ps
T413 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1259427031 Jul 17 07:04:27 PM PDT 24 Jul 17 07:04:33 PM PDT 24 768721644 ps
T414 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2431658930 Jul 17 07:04:44 PM PDT 24 Jul 17 07:04:48 PM PDT 24 427350863 ps
T415 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.968191289 Jul 17 07:04:28 PM PDT 24 Jul 17 07:04:33 PM PDT 24 534920449 ps
T416 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1784169874 Jul 17 07:04:47 PM PDT 24 Jul 17 07:04:51 PM PDT 24 501702930 ps
T417 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2696589300 Jul 17 07:04:27 PM PDT 24 Jul 17 07:04:31 PM PDT 24 521103772 ps
T418 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3777360314 Jul 17 07:04:46 PM PDT 24 Jul 17 07:04:51 PM PDT 24 538138939 ps
T419 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.723313118 Jul 17 07:04:33 PM PDT 24 Jul 17 07:04:38 PM PDT 24 1027366151 ps
T420 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.4100178671 Jul 17 07:04:28 PM PDT 24 Jul 17 07:04:32 PM PDT 24 584152882 ps
T70 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.313936145 Jul 17 07:04:28 PM PDT 24 Jul 17 07:04:37 PM PDT 24 10562570607 ps
T421 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2939329859 Jul 17 07:04:45 PM PDT 24 Jul 17 07:04:47 PM PDT 24 705429327 ps
T422 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1561292794 Jul 17 07:04:29 PM PDT 24 Jul 17 07:04:33 PM PDT 24 484683678 ps

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.3005116602
Short name T1
Test name
Test status
Simulation time 70602910369 ps
CPU time 136.44 seconds
Started Jul 17 07:03:39 PM PDT 24
Finished Jul 17 07:06:00 PM PDT 24
Peak memory 206924 kb
Host smart-a0f35dbb-73b9-476d-b186-254e41b3b566
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005116602 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.3005116602
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.4029127421
Short name T11
Test name
Test status
Simulation time 163218619427 ps
CPU time 67.82 seconds
Started Jul 17 07:04:06 PM PDT 24
Finished Jul 17 07:05:17 PM PDT 24
Peak memory 198316 kb
Host smart-f1c462f0-d637-4e5a-af88-edda68104286
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029127421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.4029127421
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.1505689691
Short name T30
Test name
Test status
Simulation time 662753707581 ps
CPU time 1424.89 seconds
Started Jul 17 07:03:38 PM PDT 24
Finished Jul 17 07:27:28 PM PDT 24
Peak memory 215412 kb
Host smart-5458246c-976d-4bd3-9fa3-abb378cf5e7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505689691 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.1505689691
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.526491572
Short name T19
Test name
Test status
Simulation time 4232746750 ps
CPU time 3.65 seconds
Started Jul 17 07:03:13 PM PDT 24
Finished Jul 17 07:03:19 PM PDT 24
Peak memory 215384 kb
Host smart-87b2511d-fdf8-4e77-b0e8-9b3831330144
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526491572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.526491572
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.1360803091
Short name T86
Test name
Test status
Simulation time 885702425604 ps
CPU time 731.92 seconds
Started Jul 17 07:03:57 PM PDT 24
Finished Jul 17 07:16:11 PM PDT 24
Peak memory 214016 kb
Host smart-0bd75272-62ca-4bbe-890b-d868da4f1904
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360803091 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.1360803091
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.3329001875
Short name T91
Test name
Test status
Simulation time 793218807770 ps
CPU time 371.46 seconds
Started Jul 17 07:03:38 PM PDT 24
Finished Jul 17 07:09:54 PM PDT 24
Peak memory 210636 kb
Host smart-98d45507-050a-429d-941a-3e3136923883
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329001875 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.3329001875
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1297108720
Short name T39
Test name
Test status
Simulation time 539474304 ps
CPU time 0.81 seconds
Started Jul 17 07:04:24 PM PDT 24
Finished Jul 17 07:04:26 PM PDT 24
Peak memory 194100 kb
Host smart-b2aad6f0-2cfd-40e1-9b4c-58534d577be6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297108720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.1297108720
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.3255449035
Short name T14
Test name
Test status
Simulation time 77838494341 ps
CPU time 274.4 seconds
Started Jul 17 07:03:39 PM PDT 24
Finished Jul 17 07:08:18 PM PDT 24
Peak memory 200992 kb
Host smart-3c67ff17-df7a-47f8-85b1-74ed878a2002
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255449035 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.3255449035
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1008522152
Short name T55
Test name
Test status
Simulation time 68786875577 ps
CPU time 737.26 seconds
Started Jul 17 07:03:38 PM PDT 24
Finished Jul 17 07:16:00 PM PDT 24
Peak memory 214576 kb
Host smart-9f973ead-a6ec-45c5-a162-23b9840bb376
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008522152 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1008522152
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.1625037253
Short name T43
Test name
Test status
Simulation time 343334563782 ps
CPU time 183.89 seconds
Started Jul 17 07:03:15 PM PDT 24
Finished Jul 17 07:06:23 PM PDT 24
Peak memory 199988 kb
Host smart-0aecc3a6-2141-4b65-9479-2bec40c62e96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625037253 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.1625037253
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.874494390
Short name T103
Test name
Test status
Simulation time 78801230022 ps
CPU time 125.61 seconds
Started Jul 17 07:03:56 PM PDT 24
Finished Jul 17 07:06:04 PM PDT 24
Peak memory 198284 kb
Host smart-985c89c1-c6c9-4f2e-8fe2-bd31fbaf2068
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874494390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_a
ll.874494390
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1346154426
Short name T116
Test name
Test status
Simulation time 162321028110 ps
CPU time 727.1 seconds
Started Jul 17 07:03:40 PM PDT 24
Finished Jul 17 07:15:52 PM PDT 24
Peak memory 206468 kb
Host smart-f8d51ac5-39a6-4235-a013-84abcd5f6c44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346154426 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.1346154426
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.409463128
Short name T105
Test name
Test status
Simulation time 129525795339 ps
CPU time 504.36 seconds
Started Jul 17 07:03:37 PM PDT 24
Finished Jul 17 07:12:06 PM PDT 24
Peak memory 204260 kb
Host smart-e3632c5a-4646-4448-af54-542626247a23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409463128 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.409463128
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.1051092096
Short name T54
Test name
Test status
Simulation time 237331820875 ps
CPU time 655.82 seconds
Started Jul 17 07:04:07 PM PDT 24
Finished Jul 17 07:15:06 PM PDT 24
Peak memory 214956 kb
Host smart-1236ef12-f943-47d3-a375-c9f05a7dbf1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051092096 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.1051092096
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.1087344267
Short name T42
Test name
Test status
Simulation time 290070661043 ps
CPU time 553.82 seconds
Started Jul 17 07:04:08 PM PDT 24
Finished Jul 17 07:13:25 PM PDT 24
Peak memory 213280 kb
Host smart-ab58eae3-c11b-4aee-9293-e2f7548f03f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087344267 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.1087344267
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.2814125331
Short name T145
Test name
Test status
Simulation time 324991029379 ps
CPU time 575.83 seconds
Started Jul 17 07:04:05 PM PDT 24
Finished Jul 17 07:13:44 PM PDT 24
Peak memory 205160 kb
Host smart-3957b338-b707-4ea5-94a3-7668b51565c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814125331 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.2814125331
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1906764324
Short name T88
Test name
Test status
Simulation time 148876073512 ps
CPU time 343.34 seconds
Started Jul 17 07:04:02 PM PDT 24
Finished Jul 17 07:09:49 PM PDT 24
Peak memory 210876 kb
Host smart-b4f5fa18-f207-438e-bac8-4383048d8873
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906764324 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.1906764324
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.857572113
Short name T3
Test name
Test status
Simulation time 529790552468 ps
CPU time 1254.48 seconds
Started Jul 17 07:04:07 PM PDT 24
Finished Jul 17 07:25:05 PM PDT 24
Peak memory 214896 kb
Host smart-3f5d5300-2b4f-4a87-b18f-4cffb8d7786b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857572113 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.857572113
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3637295547
Short name T32
Test name
Test status
Simulation time 17863000726 ps
CPU time 26.65 seconds
Started Jul 17 07:03:34 PM PDT 24
Finished Jul 17 07:04:04 PM PDT 24
Peak memory 192984 kb
Host smart-1cc0ed20-80d6-44c8-bfa0-6f5c986cdddc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637295547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3637295547
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.715165441
Short name T111
Test name
Test status
Simulation time 63617250234 ps
CPU time 50.73 seconds
Started Jul 17 07:03:58 PM PDT 24
Finished Jul 17 07:04:51 PM PDT 24
Peak memory 198220 kb
Host smart-fdd04932-b9e4-47cb-8db6-032fb974b639
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715165441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.715165441
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3787760980
Short name T122
Test name
Test status
Simulation time 105333466548 ps
CPU time 143.8 seconds
Started Jul 17 07:03:37 PM PDT 24
Finished Jul 17 07:06:06 PM PDT 24
Peak memory 192832 kb
Host smart-ba7e0eb7-ec63-4b48-b76f-7a9a0199c4b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787760980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3787760980
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.2306438607
Short name T101
Test name
Test status
Simulation time 145727545088 ps
CPU time 395.19 seconds
Started Jul 17 07:04:00 PM PDT 24
Finished Jul 17 07:10:38 PM PDT 24
Peak memory 211228 kb
Host smart-e18deaad-28c9-43f9-a29b-889b9a7f9f77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306438607 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.2306438607
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.25882622
Short name T139
Test name
Test status
Simulation time 395619739508 ps
CPU time 100.55 seconds
Started Jul 17 07:03:18 PM PDT 24
Finished Jul 17 07:05:04 PM PDT 24
Peak memory 184708 kb
Host smart-5dc3e6fc-6ff5-49b6-ac87-6f7dd0399f19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25882622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all
.25882622
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.1724991116
Short name T114
Test name
Test status
Simulation time 157607392095 ps
CPU time 209.31 seconds
Started Jul 17 07:03:39 PM PDT 24
Finished Jul 17 07:07:13 PM PDT 24
Peak memory 208640 kb
Host smart-228e7baa-efae-47b8-b0d2-b615fcb7d2d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724991116 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.1724991116
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.1020046465
Short name T72
Test name
Test status
Simulation time 323344865683 ps
CPU time 601.15 seconds
Started Jul 17 07:03:57 PM PDT 24
Finished Jul 17 07:14:01 PM PDT 24
Peak memory 205888 kb
Host smart-49c4fd8d-9d9c-4b72-baa1-79f7d75d3e8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020046465 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.1020046465
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.922515793
Short name T95
Test name
Test status
Simulation time 118086582407 ps
CPU time 255.78 seconds
Started Jul 17 07:04:09 PM PDT 24
Finished Jul 17 07:08:28 PM PDT 24
Peak memory 209396 kb
Host smart-0ec80bbb-3c74-4017-987e-a5f368089a36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922515793 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.922515793
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3669139509
Short name T45
Test name
Test status
Simulation time 54701288611 ps
CPU time 582.78 seconds
Started Jul 17 07:03:36 PM PDT 24
Finished Jul 17 07:13:23 PM PDT 24
Peak memory 214348 kb
Host smart-e8555895-432f-4cbb-9427-b7dcf78c5cc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669139509 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3669139509
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3246177047
Short name T38
Test name
Test status
Simulation time 8293657001 ps
CPU time 12.78 seconds
Started Jul 17 07:04:30 PM PDT 24
Finished Jul 17 07:04:46 PM PDT 24
Peak memory 198520 kb
Host smart-24fad79b-98d7-43e0-8bf9-5964efe740ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246177047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.3246177047
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.638749705
Short name T89
Test name
Test status
Simulation time 320646442582 ps
CPU time 449.81 seconds
Started Jul 17 07:03:34 PM PDT 24
Finished Jul 17 07:11:06 PM PDT 24
Peak memory 206828 kb
Host smart-177281ab-8af4-44e0-aa48-7b21b06ad02f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638749705 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.638749705
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.541488600
Short name T121
Test name
Test status
Simulation time 15324489671 ps
CPU time 23.3 seconds
Started Jul 17 07:03:57 PM PDT 24
Finished Jul 17 07:04:23 PM PDT 24
Peak memory 198296 kb
Host smart-74c01ff4-bfba-4598-bb86-d6613a1edeb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541488600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_a
ll.541488600
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.4107717481
Short name T108
Test name
Test status
Simulation time 407211848441 ps
CPU time 575.01 seconds
Started Jul 17 07:03:33 PM PDT 24
Finished Jul 17 07:13:10 PM PDT 24
Peak memory 193044 kb
Host smart-29b98357-3ece-4127-8c73-a90eb0af5ca4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107717481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.4107717481
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.3263570345
Short name T136
Test name
Test status
Simulation time 238776666299 ps
CPU time 794.42 seconds
Started Jul 17 07:03:39 PM PDT 24
Finished Jul 17 07:16:58 PM PDT 24
Peak memory 214928 kb
Host smart-116ca798-1220-4782-926b-4f6bfffbea37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263570345 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.3263570345
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1558455861
Short name T107
Test name
Test status
Simulation time 28205153853 ps
CPU time 43.72 seconds
Started Jul 17 07:03:57 PM PDT 24
Finished Jul 17 07:04:43 PM PDT 24
Peak memory 198404 kb
Host smart-73ec2c9b-af2a-4b18-9e06-61008300e54a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558455861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1558455861
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.350778032
Short name T74
Test name
Test status
Simulation time 456102168894 ps
CPU time 701.47 seconds
Started Jul 17 07:03:55 PM PDT 24
Finished Jul 17 07:15:39 PM PDT 24
Peak memory 205996 kb
Host smart-f69051f9-ae70-44ec-bc3b-a83cfbcf245d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350778032 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.350778032
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.2546252953
Short name T123
Test name
Test status
Simulation time 160909426437 ps
CPU time 435.84 seconds
Started Jul 17 07:03:37 PM PDT 24
Finished Jul 17 07:10:58 PM PDT 24
Peak memory 203624 kb
Host smart-c24573b3-817d-4339-aa41-611300f9c2db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546252953 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.2546252953
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.3855139045
Short name T53
Test name
Test status
Simulation time 265842208367 ps
CPU time 1129.9 seconds
Started Jul 17 07:03:45 PM PDT 24
Finished Jul 17 07:22:36 PM PDT 24
Peak memory 215008 kb
Host smart-915bee9c-a2d6-435f-be21-71e49d4fe01e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855139045 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.3855139045
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2846156275
Short name T109
Test name
Test status
Simulation time 154262060607 ps
CPU time 50.97 seconds
Started Jul 17 07:03:38 PM PDT 24
Finished Jul 17 07:04:34 PM PDT 24
Peak memory 191996 kb
Host smart-5321cd6b-72ad-4caf-9e5a-f169a2df5d03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846156275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2846156275
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.3952857211
Short name T48
Test name
Test status
Simulation time 148093073693 ps
CPU time 33.87 seconds
Started Jul 17 07:04:01 PM PDT 24
Finished Jul 17 07:04:37 PM PDT 24
Peak memory 193088 kb
Host smart-5e7052b3-3f0a-4f6e-8178-d989735c46c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952857211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.3952857211
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.1252417543
Short name T94
Test name
Test status
Simulation time 55616824818 ps
CPU time 43.98 seconds
Started Jul 17 07:04:00 PM PDT 24
Finished Jul 17 07:04:46 PM PDT 24
Peak memory 191984 kb
Host smart-d3b4c0c9-7d9d-421c-b91a-4c65a3ea2484
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252417543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.1252417543
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.218531495
Short name T99
Test name
Test status
Simulation time 118707674984 ps
CPU time 157.9 seconds
Started Jul 17 07:03:34 PM PDT 24
Finished Jul 17 07:06:14 PM PDT 24
Peak memory 198512 kb
Host smart-88b7b57e-6095-478f-a84a-124dbd427602
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218531495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_al
l.218531495
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.483861223
Short name T128
Test name
Test status
Simulation time 375076629641 ps
CPU time 122.06 seconds
Started Jul 17 07:03:38 PM PDT 24
Finished Jul 17 07:05:45 PM PDT 24
Peak memory 184480 kb
Host smart-0aa93233-22e1-47ae-a794-4a2ea51e79de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483861223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_a
ll.483861223
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.3842231367
Short name T143
Test name
Test status
Simulation time 77597690441 ps
CPU time 111.01 seconds
Started Jul 17 07:03:57 PM PDT 24
Finished Jul 17 07:05:51 PM PDT 24
Peak memory 193092 kb
Host smart-d4680086-d0a9-4d8c-b1dc-7dfb07bd1014
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842231367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.3842231367
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.1295594293
Short name T87
Test name
Test status
Simulation time 99797742671 ps
CPU time 176.75 seconds
Started Jul 17 07:03:58 PM PDT 24
Finished Jul 17 07:06:57 PM PDT 24
Peak memory 200140 kb
Host smart-40e1c4ad-b5f1-43b0-81a5-b93577f78fd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295594293 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.1295594293
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.1976542919
Short name T96
Test name
Test status
Simulation time 57792843227 ps
CPU time 47.27 seconds
Started Jul 17 07:03:58 PM PDT 24
Finished Jul 17 07:04:48 PM PDT 24
Peak memory 191932 kb
Host smart-a4e64349-b801-4026-ac4e-d15da4a8e79f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976542919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.1976542919
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.1021218048
Short name T132
Test name
Test status
Simulation time 200050995510 ps
CPU time 20.13 seconds
Started Jul 17 07:03:56 PM PDT 24
Finished Jul 17 07:04:18 PM PDT 24
Peak memory 192952 kb
Host smart-cb0abef5-6e60-4896-88b5-e1c962883bf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021218048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.1021218048
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.3532054791
Short name T161
Test name
Test status
Simulation time 53543223405 ps
CPU time 105.27 seconds
Started Jul 17 07:03:35 PM PDT 24
Finished Jul 17 07:05:23 PM PDT 24
Peak memory 206800 kb
Host smart-2e8baf8f-2dce-483f-87ae-684d8e435d64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532054791 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.3532054791
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.4193964207
Short name T112
Test name
Test status
Simulation time 225893107718 ps
CPU time 178.44 seconds
Started Jul 17 07:03:59 PM PDT 24
Finished Jul 17 07:07:00 PM PDT 24
Peak memory 198208 kb
Host smart-2293c313-5b06-435a-929f-3347fd99bb54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193964207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.4193964207
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.4013724008
Short name T125
Test name
Test status
Simulation time 92005278408 ps
CPU time 22.66 seconds
Started Jul 17 07:04:09 PM PDT 24
Finished Jul 17 07:04:34 PM PDT 24
Peak memory 198312 kb
Host smart-cd964f34-b053-4473-a3e2-e26043ca82dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013724008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.4013724008
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.293461138
Short name T47
Test name
Test status
Simulation time 293306918268 ps
CPU time 201.76 seconds
Started Jul 17 07:04:09 PM PDT 24
Finished Jul 17 07:07:34 PM PDT 24
Peak memory 193200 kb
Host smart-d0a46f19-8b09-4931-9852-9adb9bde5bd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293461138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_a
ll.293461138
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2424043111
Short name T133
Test name
Test status
Simulation time 78092273532 ps
CPU time 110.45 seconds
Started Jul 17 07:03:32 PM PDT 24
Finished Jul 17 07:05:24 PM PDT 24
Peak memory 193148 kb
Host smart-c3df03be-cf02-461e-9aba-cca67e6a066e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424043111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2424043111
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.316656998
Short name T44
Test name
Test status
Simulation time 92915707096 ps
CPU time 944.19 seconds
Started Jul 17 07:03:54 PM PDT 24
Finished Jul 17 07:19:39 PM PDT 24
Peak memory 210224 kb
Host smart-0a6045e7-8337-4492-8ae9-e1b9a4073c09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316656998 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.316656998
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.1404149921
Short name T126
Test name
Test status
Simulation time 302450303687 ps
CPU time 220.85 seconds
Started Jul 17 07:03:55 PM PDT 24
Finished Jul 17 07:07:38 PM PDT 24
Peak memory 193088 kb
Host smart-a6633ddd-2314-4e95-8752-9f6c04bc6883
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404149921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.1404149921
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.2975921618
Short name T71
Test name
Test status
Simulation time 82391261882 ps
CPU time 33.62 seconds
Started Jul 17 07:04:09 PM PDT 24
Finished Jul 17 07:04:45 PM PDT 24
Peak memory 198312 kb
Host smart-d81588d8-d1b5-4121-aaaf-7683798c5b8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975921618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.2975921618
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.916510082
Short name T98
Test name
Test status
Simulation time 250110674538 ps
CPU time 353.14 seconds
Started Jul 17 07:03:33 PM PDT 24
Finished Jul 17 07:09:28 PM PDT 24
Peak memory 198352 kb
Host smart-614083f9-46a7-4ff9-b4f1-21810362ed11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916510082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.916510082
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.77552232
Short name T157
Test name
Test status
Simulation time 28254835430 ps
CPU time 238.37 seconds
Started Jul 17 07:03:40 PM PDT 24
Finished Jul 17 07:07:43 PM PDT 24
Peak memory 198680 kb
Host smart-957a15ae-3147-4ed9-aced-777780f16430
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77552232 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.77552232
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.2035930097
Short name T142
Test name
Test status
Simulation time 23511798422 ps
CPU time 189.38 seconds
Started Jul 17 07:03:39 PM PDT 24
Finished Jul 17 07:06:53 PM PDT 24
Peak memory 198716 kb
Host smart-e6ef0c19-3c41-43cb-ab99-778fd4df3132
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035930097 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.2035930097
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.4175071380
Short name T147
Test name
Test status
Simulation time 262643294180 ps
CPU time 128.98 seconds
Started Jul 17 07:03:39 PM PDT 24
Finished Jul 17 07:05:53 PM PDT 24
Peak memory 193012 kb
Host smart-6a533c48-c4d2-4bc7-b55c-b9ea298e3919
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175071380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.4175071380
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.554274880
Short name T13
Test name
Test status
Simulation time 203475181514 ps
CPU time 41.34 seconds
Started Jul 17 07:03:58 PM PDT 24
Finished Jul 17 07:04:41 PM PDT 24
Peak memory 192000 kb
Host smart-350e91f7-f0e0-4673-acf1-1ffc3f78b0cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554274880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a
ll.554274880
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.2774508514
Short name T160
Test name
Test status
Simulation time 52873585723 ps
CPU time 211.61 seconds
Started Jul 17 07:03:57 PM PDT 24
Finished Jul 17 07:07:31 PM PDT 24
Peak memory 206820 kb
Host smart-e72d08e1-43e2-42a8-a930-b8fabad64e38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774508514 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.2774508514
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.1803442494
Short name T104
Test name
Test status
Simulation time 187362376216 ps
CPU time 52.65 seconds
Started Jul 17 07:04:08 PM PDT 24
Finished Jul 17 07:05:04 PM PDT 24
Peak memory 193152 kb
Host smart-d93ea669-c799-41e8-a4fc-a86d067d2be8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803442494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.1803442494
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.1192463928
Short name T119
Test name
Test status
Simulation time 762345484452 ps
CPU time 449.27 seconds
Started Jul 17 07:03:38 PM PDT 24
Finished Jul 17 07:11:12 PM PDT 24
Peak memory 214420 kb
Host smart-04d4b950-7b1a-4a11-88dc-d513f93b0b43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192463928 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.1192463928
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.2325662500
Short name T134
Test name
Test status
Simulation time 339511753807 ps
CPU time 454.92 seconds
Started Jul 17 07:03:37 PM PDT 24
Finished Jul 17 07:11:16 PM PDT 24
Peak memory 198468 kb
Host smart-19eb8b2b-ca4c-4870-8912-078ff5ce3abe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325662500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.2325662500
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3172801667
Short name T92
Test name
Test status
Simulation time 156754910687 ps
CPU time 55.31 seconds
Started Jul 17 07:03:39 PM PDT 24
Finished Jul 17 07:04:40 PM PDT 24
Peak memory 192044 kb
Host smart-8ee9d045-c1cb-46e2-89ac-95b08730378a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172801667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3172801667
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_jump.441278822
Short name T25
Test name
Test status
Simulation time 519792763 ps
CPU time 1.37 seconds
Started Jul 17 07:03:33 PM PDT 24
Finished Jul 17 07:03:36 PM PDT 24
Peak memory 196756 kb
Host smart-6388f54e-a495-4dca-b13f-4c120eb21f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441278822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.441278822
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.1167555360
Short name T138
Test name
Test status
Simulation time 67048694053 ps
CPU time 47.37 seconds
Started Jul 17 07:03:36 PM PDT 24
Finished Jul 17 07:04:28 PM PDT 24
Peak memory 191976 kb
Host smart-c7eb38c5-da31-43ee-9de7-73d47c97a524
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167555360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.1167555360
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.2305248978
Short name T168
Test name
Test status
Simulation time 3415158102 ps
CPU time 22.63 seconds
Started Jul 17 07:03:54 PM PDT 24
Finished Jul 17 07:04:18 PM PDT 24
Peak memory 206852 kb
Host smart-7173ad47-23db-46e7-b902-69b5f25be990
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305248978 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.2305248978
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.2357278508
Short name T140
Test name
Test status
Simulation time 693551870 ps
CPU time 0.62 seconds
Started Jul 17 07:04:05 PM PDT 24
Finished Jul 17 07:04:08 PM PDT 24
Peak memory 196708 kb
Host smart-521dd6fd-1f9c-4d78-a93a-f6b13ce7e538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357278508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2357278508
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.2072536167
Short name T177
Test name
Test status
Simulation time 82750488849 ps
CPU time 420.04 seconds
Started Jul 17 07:04:01 PM PDT 24
Finished Jul 17 07:11:03 PM PDT 24
Peak memory 211160 kb
Host smart-bae6e2f5-2db6-485c-b9f7-6b721c203f7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072536167 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.2072536167
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.2539867989
Short name T100
Test name
Test status
Simulation time 401385902 ps
CPU time 1.18 seconds
Started Jul 17 07:03:57 PM PDT 24
Finished Jul 17 07:04:01 PM PDT 24
Peak memory 196708 kb
Host smart-9eae2ae7-42d8-44d0-814c-108929a0d271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539867989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.2539867989
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.935478490
Short name T102
Test name
Test status
Simulation time 78545657294 ps
CPU time 30.77 seconds
Started Jul 17 07:03:34 PM PDT 24
Finished Jul 17 07:04:06 PM PDT 24
Peak memory 198404 kb
Host smart-50fda41d-f1ca-42e9-a572-b344b8cf965e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935478490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_al
l.935478490
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.200956407
Short name T293
Test name
Test status
Simulation time 508453724 ps
CPU time 0.77 seconds
Started Jul 17 07:04:29 PM PDT 24
Finished Jul 17 07:04:33 PM PDT 24
Peak memory 195800 kb
Host smart-28615e8e-4601-4f5d-8c23-b97886c5e442
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200956407 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.200956407
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.2512333189
Short name T117
Test name
Test status
Simulation time 532427325 ps
CPU time 0.81 seconds
Started Jul 17 07:03:57 PM PDT 24
Finished Jul 17 07:04:00 PM PDT 24
Peak memory 196840 kb
Host smart-679b9efa-b28e-42bd-bd40-d5950a295efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512333189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.2512333189
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.3090554239
Short name T149
Test name
Test status
Simulation time 123165855064 ps
CPU time 164.78 seconds
Started Jul 17 07:03:34 PM PDT 24
Finished Jul 17 07:06:22 PM PDT 24
Peak memory 192896 kb
Host smart-ae514c24-59d7-41e3-ab47-f28fc92061d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090554239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.3090554239
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_jump.28784544
Short name T129
Test name
Test status
Simulation time 456099206 ps
CPU time 0.75 seconds
Started Jul 17 07:04:09 PM PDT 24
Finished Jul 17 07:04:13 PM PDT 24
Peak memory 196820 kb
Host smart-a6ebab86-0bee-4151-9173-362ebf89729f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28784544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.28784544
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.184734230
Short name T151
Test name
Test status
Simulation time 388039283 ps
CPU time 0.85 seconds
Started Jul 17 07:04:01 PM PDT 24
Finished Jul 17 07:04:04 PM PDT 24
Peak memory 196652 kb
Host smart-349b3e8c-ef5d-42c5-bd58-270c8652c8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184734230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.184734230
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.3833434530
Short name T172
Test name
Test status
Simulation time 39933198552 ps
CPU time 148.66 seconds
Started Jul 17 07:04:09 PM PDT 24
Finished Jul 17 07:06:41 PM PDT 24
Peak memory 198624 kb
Host smart-1c520016-494d-412a-af52-a132f116f0e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833434530 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.3833434530
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.3771951261
Short name T110
Test name
Test status
Simulation time 74830813730 ps
CPU time 38.77 seconds
Started Jul 17 07:03:35 PM PDT 24
Finished Jul 17 07:04:18 PM PDT 24
Peak memory 198280 kb
Host smart-46684cbd-a07d-4447-8bfb-5ae9e8459e82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771951261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.3771951261
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.2372975244
Short name T78
Test name
Test status
Simulation time 395939278088 ps
CPU time 534.93 seconds
Started Jul 17 07:03:38 PM PDT 24
Finished Jul 17 07:12:37 PM PDT 24
Peak memory 198332 kb
Host smart-79302f35-4422-4ccc-833a-828365f4f592
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372975244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.2372975244
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3824535600
Short name T178
Test name
Test status
Simulation time 94042325935 ps
CPU time 24.77 seconds
Started Jul 17 07:03:58 PM PDT 24
Finished Jul 17 07:04:25 PM PDT 24
Peak memory 198196 kb
Host smart-0960baac-d56a-4d77-b98a-474464ae1c1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824535600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3824535600
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_jump.3444334156
Short name T141
Test name
Test status
Simulation time 475060222 ps
CPU time 0.78 seconds
Started Jul 17 07:04:08 PM PDT 24
Finished Jul 17 07:04:12 PM PDT 24
Peak memory 196840 kb
Host smart-6cba6fba-cad5-4800-8f35-850f7035e035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444334156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.3444334156
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.21884210
Short name T93
Test name
Test status
Simulation time 580683975 ps
CPU time 0.96 seconds
Started Jul 17 07:03:40 PM PDT 24
Finished Jul 17 07:03:45 PM PDT 24
Peak memory 196756 kb
Host smart-13755f3b-7eac-45ac-bc7a-126f5e2634bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21884210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.21884210
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.792651849
Short name T118
Test name
Test status
Simulation time 527912415 ps
CPU time 0.76 seconds
Started Jul 17 07:03:18 PM PDT 24
Finished Jul 17 07:03:24 PM PDT 24
Peak memory 196736 kb
Host smart-e12f4e5a-a27c-407d-812b-32ba3052d89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792651849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.792651849
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.653322812
Short name T146
Test name
Test status
Simulation time 363611332 ps
CPU time 1.11 seconds
Started Jul 17 07:03:39 PM PDT 24
Finished Jul 17 07:03:45 PM PDT 24
Peak memory 196732 kb
Host smart-cf7775b4-a91f-4590-a1e6-69223f211cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653322812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.653322812
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.524319690
Short name T144
Test name
Test status
Simulation time 441997808 ps
CPU time 0.65 seconds
Started Jul 17 07:03:40 PM PDT 24
Finished Jul 17 07:03:45 PM PDT 24
Peak memory 196736 kb
Host smart-53b7316a-cc9f-4653-9fdc-4b912996db8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524319690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.524319690
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1584163006
Short name T155
Test name
Test status
Simulation time 5920804807 ps
CPU time 2.85 seconds
Started Jul 17 07:03:40 PM PDT 24
Finished Jul 17 07:03:47 PM PDT 24
Peak memory 193032 kb
Host smart-04d720cf-a658-4258-9413-ba479563f043
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584163006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1584163006
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.3723470677
Short name T184
Test name
Test status
Simulation time 30178943387 ps
CPU time 107.17 seconds
Started Jul 17 07:03:57 PM PDT 24
Finished Jul 17 07:05:47 PM PDT 24
Peak memory 206864 kb
Host smart-9ca87c03-a088-4858-aa80-1ded91e044b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723470677 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.3723470677
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3286220721
Short name T120
Test name
Test status
Simulation time 485714847730 ps
CPU time 365.75 seconds
Started Jul 17 07:04:01 PM PDT 24
Finished Jul 17 07:10:09 PM PDT 24
Peak memory 193084 kb
Host smart-174968d6-1632-4afa-8105-b1416a18339f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286220721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3286220721
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.4221135262
Short name T41
Test name
Test status
Simulation time 8198151178 ps
CPU time 57.76 seconds
Started Jul 17 07:04:06 PM PDT 24
Finished Jul 17 07:05:08 PM PDT 24
Peak memory 198628 kb
Host smart-d9cf1fba-90eb-4ad7-9584-2bc7615d1216
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221135262 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.4221135262
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.444958918
Short name T97
Test name
Test status
Simulation time 554632346 ps
CPU time 1.3 seconds
Started Jul 17 07:03:40 PM PDT 24
Finished Jul 17 07:03:46 PM PDT 24
Peak memory 196772 kb
Host smart-8413bb0a-97e7-45f6-90c2-c58c4fedc7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444958918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.444958918
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.3384413304
Short name T180
Test name
Test status
Simulation time 155600839426 ps
CPU time 62.79 seconds
Started Jul 17 07:04:03 PM PDT 24
Finished Jul 17 07:05:10 PM PDT 24
Peak memory 193080 kb
Host smart-dd71d6c4-d74a-45f7-a2be-080c4b625792
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384413304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.3384413304
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.404757673
Short name T115
Test name
Test status
Simulation time 40332854330 ps
CPU time 59.83 seconds
Started Jul 17 07:04:07 PM PDT 24
Finished Jul 17 07:05:11 PM PDT 24
Peak memory 191904 kb
Host smart-3203c7eb-775c-4aec-b31c-5eab3b2ed070
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404757673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_a
ll.404757673
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3256969282
Short name T135
Test name
Test status
Simulation time 489704639 ps
CPU time 0.73 seconds
Started Jul 17 07:03:55 PM PDT 24
Finished Jul 17 07:03:58 PM PDT 24
Peak memory 196720 kb
Host smart-ddfdfec4-c827-44ed-a822-b2d30be19ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256969282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3256969282
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.4098831768
Short name T127
Test name
Test status
Simulation time 146425216195 ps
CPU time 210.42 seconds
Started Jul 17 07:03:55 PM PDT 24
Finished Jul 17 07:07:28 PM PDT 24
Peak memory 191972 kb
Host smart-ecee6148-1600-4d68-b187-35ad1d357efb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098831768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.4098831768
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.1841587655
Short name T170
Test name
Test status
Simulation time 53163839397 ps
CPU time 117.99 seconds
Started Jul 17 07:04:03 PM PDT 24
Finished Jul 17 07:06:05 PM PDT 24
Peak memory 206860 kb
Host smart-41d18df8-dd60-40cd-a8f8-5f7c55788123
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841587655 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.1841587655
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.3581238954
Short name T179
Test name
Test status
Simulation time 11247878801 ps
CPU time 14.67 seconds
Started Jul 17 07:04:01 PM PDT 24
Finished Jul 17 07:04:18 PM PDT 24
Peak memory 198300 kb
Host smart-84018e01-1ea4-43fd-80a5-65d638861d39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581238954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.3581238954
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.2222319693
Short name T23
Test name
Test status
Simulation time 137373846786 ps
CPU time 344.72 seconds
Started Jul 17 07:04:02 PM PDT 24
Finished Jul 17 07:09:50 PM PDT 24
Peak memory 206964 kb
Host smart-4d61eade-35c9-4d12-8f9b-2272f39846fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222319693 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.2222319693
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.4082626880
Short name T148
Test name
Test status
Simulation time 477810723 ps
CPU time 0.8 seconds
Started Jul 17 07:04:08 PM PDT 24
Finished Jul 17 07:04:12 PM PDT 24
Peak memory 196740 kb
Host smart-68000994-2d0b-4c98-8c97-db1bc98a9bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082626880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.4082626880
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1959814238
Short name T150
Test name
Test status
Simulation time 568979501 ps
CPU time 1.34 seconds
Started Jul 17 07:03:39 PM PDT 24
Finished Jul 17 07:03:46 PM PDT 24
Peak memory 196764 kb
Host smart-2bb6a40c-03db-4d17-b412-78e62a635fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959814238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1959814238
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1124330582
Short name T173
Test name
Test status
Simulation time 99275158465 ps
CPU time 152.18 seconds
Started Jul 17 07:03:34 PM PDT 24
Finished Jul 17 07:06:09 PM PDT 24
Peak memory 191908 kb
Host smart-3824c750-9aec-4c18-928c-0c8e5aed0e53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124330582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1124330582
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.2206590220
Short name T130
Test name
Test status
Simulation time 509584061 ps
CPU time 1.32 seconds
Started Jul 17 07:03:38 PM PDT 24
Finished Jul 17 07:03:44 PM PDT 24
Peak memory 196660 kb
Host smart-f7ea649f-bf86-433b-b21c-bec8328610e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206590220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2206590220
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.3369946649
Short name T49
Test name
Test status
Simulation time 198744561262 ps
CPU time 289.68 seconds
Started Jul 17 07:03:38 PM PDT 24
Finished Jul 17 07:08:32 PM PDT 24
Peak memory 198348 kb
Host smart-46e7f1b2-f4e8-4d39-ade1-3f2a3aaf42f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369946649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.3369946649
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.1506670264
Short name T124
Test name
Test status
Simulation time 121280673415 ps
CPU time 229.36 seconds
Started Jul 17 07:03:37 PM PDT 24
Finished Jul 17 07:07:31 PM PDT 24
Peak memory 200004 kb
Host smart-738a4ac3-251d-4783-aeac-b602fa895f69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506670264 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.1506670264
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.2382159506
Short name T131
Test name
Test status
Simulation time 549684759 ps
CPU time 0.78 seconds
Started Jul 17 07:03:56 PM PDT 24
Finished Jul 17 07:04:00 PM PDT 24
Peak memory 196784 kb
Host smart-385f3808-c6a4-4552-b085-6c844ef42e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382159506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2382159506
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.2802324123
Short name T20
Test name
Test status
Simulation time 525863388 ps
CPU time 0.86 seconds
Started Jul 17 07:04:06 PM PDT 24
Finished Jul 17 07:04:11 PM PDT 24
Peak memory 196676 kb
Host smart-90ebf9ba-3430-4e4a-9a90-0b784f8d28b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802324123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.2802324123
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.3136333007
Short name T27
Test name
Test status
Simulation time 499893601 ps
CPU time 1.23 seconds
Started Jul 17 07:04:03 PM PDT 24
Finished Jul 17 07:04:07 PM PDT 24
Peak memory 196772 kb
Host smart-8116bba2-c563-4b7d-9425-eeaec90da69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136333007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.3136333007
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.4129246119
Short name T137
Test name
Test status
Simulation time 433353414 ps
CPU time 1.06 seconds
Started Jul 17 07:04:02 PM PDT 24
Finished Jul 17 07:04:07 PM PDT 24
Peak memory 196792 kb
Host smart-70bc4026-a09c-4630-9cf0-47cbf31e7e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129246119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.4129246119
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.476717774
Short name T90
Test name
Test status
Simulation time 26257152969 ps
CPU time 137.51 seconds
Started Jul 17 07:04:06 PM PDT 24
Finished Jul 17 07:06:27 PM PDT 24
Peak memory 206896 kb
Host smart-11b49d7d-1557-4dd8-a7b0-63aedc732a46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476717774 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.476717774
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.2015997511
Short name T176
Test name
Test status
Simulation time 594446484 ps
CPU time 1.58 seconds
Started Jul 17 07:04:04 PM PDT 24
Finished Jul 17 07:04:09 PM PDT 24
Peak memory 196708 kb
Host smart-ac3d65c6-0316-4a28-95cf-4ed326938022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015997511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2015997511
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3260745197
Short name T181
Test name
Test status
Simulation time 64337971594 ps
CPU time 49.32 seconds
Started Jul 17 07:04:06 PM PDT 24
Finished Jul 17 07:04:58 PM PDT 24
Peak memory 192912 kb
Host smart-2d6b1563-4ac8-4982-9bf6-1a5222a632c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260745197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3260745197
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3782029191
Short name T31
Test name
Test status
Simulation time 399181566559 ps
CPU time 278.78 seconds
Started Jul 17 07:03:34 PM PDT 24
Finished Jul 17 07:08:16 PM PDT 24
Peak memory 209500 kb
Host smart-f1bfa54f-d136-4f3f-9d66-3f0d6bb81b78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782029191 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.3782029191
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.1953582616
Short name T187
Test name
Test status
Simulation time 472136278 ps
CPU time 0.78 seconds
Started Jul 17 07:03:38 PM PDT 24
Finished Jul 17 07:03:44 PM PDT 24
Peak memory 196696 kb
Host smart-d785039b-63f0-4b26-b786-94bedc279f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953582616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1953582616
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.4039299613
Short name T73
Test name
Test status
Simulation time 414336095 ps
CPU time 1.08 seconds
Started Jul 17 07:03:37 PM PDT 24
Finished Jul 17 07:03:42 PM PDT 24
Peak memory 196716 kb
Host smart-9179c499-6a16-47ef-974f-14998ea73c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039299613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.4039299613
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.2272778392
Short name T152
Test name
Test status
Simulation time 476698031 ps
CPU time 1.21 seconds
Started Jul 17 07:03:40 PM PDT 24
Finished Jul 17 07:03:46 PM PDT 24
Peak memory 196748 kb
Host smart-dba88d49-8ed6-4d04-979c-e6c0879f87fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272778392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2272778392
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3166591891
Short name T7
Test name
Test status
Simulation time 460152951 ps
CPU time 0.76 seconds
Started Jul 17 07:03:37 PM PDT 24
Finished Jul 17 07:03:42 PM PDT 24
Peak memory 196720 kb
Host smart-391d28be-41ce-461a-8c67-f1084aa832e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166591891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3166591891
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1672881750
Short name T163
Test name
Test status
Simulation time 369856400 ps
CPU time 0.76 seconds
Started Jul 17 07:03:55 PM PDT 24
Finished Jul 17 07:03:58 PM PDT 24
Peak memory 196684 kb
Host smart-477921e3-0863-49b3-88e7-824ef52f0e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672881750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1672881750
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2487783243
Short name T50
Test name
Test status
Simulation time 378402275 ps
CPU time 0.68 seconds
Started Jul 17 07:03:54 PM PDT 24
Finished Jul 17 07:03:56 PM PDT 24
Peak memory 196700 kb
Host smart-ec2086dc-7f90-4b96-bfcd-7d7d25200c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487783243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2487783243
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.2349320635
Short name T52
Test name
Test status
Simulation time 492918888 ps
CPU time 0.87 seconds
Started Jul 17 07:03:53 PM PDT 24
Finished Jul 17 07:03:54 PM PDT 24
Peak memory 196780 kb
Host smart-3fc147fe-24b5-4972-a95a-831187f1f34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349320635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2349320635
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.4137022036
Short name T165
Test name
Test status
Simulation time 579189281 ps
CPU time 1.3 seconds
Started Jul 17 07:03:56 PM PDT 24
Finished Jul 17 07:04:01 PM PDT 24
Peak memory 196672 kb
Host smart-ed294bb4-e9d3-46d6-85ed-1616471d2733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137022036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.4137022036
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.4114192839
Short name T185
Test name
Test status
Simulation time 419948386 ps
CPU time 0.76 seconds
Started Jul 17 07:03:56 PM PDT 24
Finished Jul 17 07:03:59 PM PDT 24
Peak memory 196792 kb
Host smart-38d9624b-d12a-4fa8-a47b-b3e72b7820e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114192839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.4114192839
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1016928470
Short name T28
Test name
Test status
Simulation time 555648130 ps
CPU time 0.86 seconds
Started Jul 17 07:04:09 PM PDT 24
Finished Jul 17 07:04:13 PM PDT 24
Peak memory 196788 kb
Host smart-c0788cac-2442-4493-8d57-fdd4a5dd02ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016928470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1016928470
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3823481768
Short name T106
Test name
Test status
Simulation time 120299108733 ps
CPU time 319.44 seconds
Started Jul 17 07:04:08 PM PDT 24
Finished Jul 17 07:09:31 PM PDT 24
Peak memory 201496 kb
Host smart-a7886212-1585-4adb-8687-9758a18bc816
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823481768 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.3823481768
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.1127824355
Short name T167
Test name
Test status
Simulation time 371826466 ps
CPU time 0.85 seconds
Started Jul 17 07:04:10 PM PDT 24
Finished Jul 17 07:04:14 PM PDT 24
Peak memory 196700 kb
Host smart-e971fa1d-6d28-4bfd-a28a-7a8534bf6c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127824355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1127824355
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2917443363
Short name T156
Test name
Test status
Simulation time 516549616 ps
CPU time 0.75 seconds
Started Jul 17 07:03:36 PM PDT 24
Finished Jul 17 07:03:41 PM PDT 24
Peak memory 196640 kb
Host smart-b2a4b653-88aa-498c-89f4-91f9a199943a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917443363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2917443363
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3718161527
Short name T162
Test name
Test status
Simulation time 348659378 ps
CPU time 1.07 seconds
Started Jul 17 07:03:39 PM PDT 24
Finished Jul 17 07:03:45 PM PDT 24
Peak memory 196680 kb
Host smart-3c7c7f24-fea5-4046-82f9-fe5fc33b7e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718161527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3718161527
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2688116837
Short name T8
Test name
Test status
Simulation time 255256613399 ps
CPU time 99.14 seconds
Started Jul 17 07:03:40 PM PDT 24
Finished Jul 17 07:05:24 PM PDT 24
Peak memory 198336 kb
Host smart-88e092f1-879f-43b7-b971-89c0d3b6bb1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688116837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2688116837
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.997090406
Short name T183
Test name
Test status
Simulation time 291950281615 ps
CPU time 99.06 seconds
Started Jul 17 07:03:33 PM PDT 24
Finished Jul 17 07:05:13 PM PDT 24
Peak memory 191968 kb
Host smart-bc3c6346-cd35-4eba-8ecb-7193be22c837
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997090406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.997090406
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3136275651
Short name T387
Test name
Test status
Simulation time 8440438074 ps
CPU time 4.05 seconds
Started Jul 17 07:04:33 PM PDT 24
Finished Jul 17 07:04:40 PM PDT 24
Peak memory 198388 kb
Host smart-3aadc8be-7644-43ee-831c-964a5f8569ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136275651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3136275651
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.3376232838
Short name T153
Test name
Test status
Simulation time 159617621445 ps
CPU time 61.23 seconds
Started Jul 17 07:03:23 PM PDT 24
Finished Jul 17 07:04:27 PM PDT 24
Peak memory 191964 kb
Host smart-658dc4d3-7a40-4ca9-8e37-fb2f5a95c0db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376232838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.3376232838
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.3418391615
Short name T166
Test name
Test status
Simulation time 437759278 ps
CPU time 0.68 seconds
Started Jul 17 07:03:35 PM PDT 24
Finished Jul 17 07:03:38 PM PDT 24
Peak memory 196708 kb
Host smart-ac8a396d-6e0f-4923-a20f-1ce01e65efb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418391615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.3418391615
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.407563437
Short name T113
Test name
Test status
Simulation time 571363250 ps
CPU time 1.05 seconds
Started Jul 17 07:03:39 PM PDT 24
Finished Jul 17 07:03:44 PM PDT 24
Peak memory 196800 kb
Host smart-db3fc74c-0e17-4344-b4fe-6072b6f3bf82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407563437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.407563437
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3046457541
Short name T159
Test name
Test status
Simulation time 417073617 ps
CPU time 0.72 seconds
Started Jul 17 07:03:36 PM PDT 24
Finished Jul 17 07:03:40 PM PDT 24
Peak memory 196948 kb
Host smart-b98320f7-0aa7-4c29-9a36-bdcee4c24b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046457541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3046457541
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.450791435
Short name T169
Test name
Test status
Simulation time 500177866 ps
CPU time 1.2 seconds
Started Jul 17 07:03:55 PM PDT 24
Finished Jul 17 07:03:59 PM PDT 24
Peak memory 196696 kb
Host smart-4f2abdf4-7120-4d6c-8049-d43ffc0dd5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450791435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.450791435
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.3574161289
Short name T186
Test name
Test status
Simulation time 412311610 ps
CPU time 1.18 seconds
Started Jul 17 07:03:34 PM PDT 24
Finished Jul 17 07:03:37 PM PDT 24
Peak memory 196708 kb
Host smart-4d997919-fde3-4db1-9f2a-c3c263a9da72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574161289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.3574161289
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.3089515923
Short name T158
Test name
Test status
Simulation time 561867885 ps
CPU time 0.86 seconds
Started Jul 17 07:04:00 PM PDT 24
Finished Jul 17 07:04:04 PM PDT 24
Peak memory 196692 kb
Host smart-08c52bc3-7aec-49c5-b14a-6d443d469bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089515923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3089515923
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.3606239186
Short name T171
Test name
Test status
Simulation time 391396308 ps
CPU time 0.85 seconds
Started Jul 17 07:04:01 PM PDT 24
Finished Jul 17 07:04:05 PM PDT 24
Peak memory 196696 kb
Host smart-ececf97a-c535-4caa-80fb-52f566501633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606239186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3606239186
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.805659666
Short name T46
Test name
Test status
Simulation time 409964162 ps
CPU time 0.76 seconds
Started Jul 17 07:04:01 PM PDT 24
Finished Jul 17 07:04:05 PM PDT 24
Peak memory 196688 kb
Host smart-70f5689d-bda7-40d3-ad9c-1e7d409cdc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805659666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.805659666
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3536177607
Short name T306
Test name
Test status
Simulation time 636197042 ps
CPU time 1.6 seconds
Started Jul 17 07:04:24 PM PDT 24
Finished Jul 17 07:04:27 PM PDT 24
Peak memory 193300 kb
Host smart-46d1ab70-614e-447e-9882-76ec73339b56
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536177607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.3536177607
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.313936145
Short name T70
Test name
Test status
Simulation time 10562570607 ps
CPU time 5.44 seconds
Started Jul 17 07:04:28 PM PDT 24
Finished Jul 17 07:04:37 PM PDT 24
Peak memory 196464 kb
Host smart-0d684705-9870-46c1-8e0b-83a8d572c4ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313936145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bi
t_bash.313936145
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.4030221002
Short name T40
Test name
Test status
Simulation time 738979078 ps
CPU time 1.58 seconds
Started Jul 17 07:04:27 PM PDT 24
Finished Jul 17 07:04:32 PM PDT 24
Peak memory 192460 kb
Host smart-9dbd5a32-ddef-44ec-9bd4-1840a8594dc6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030221002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.4030221002
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3706432771
Short name T364
Test name
Test status
Simulation time 506585016 ps
CPU time 0.76 seconds
Started Jul 17 07:04:32 PM PDT 24
Finished Jul 17 07:04:36 PM PDT 24
Peak memory 195792 kb
Host smart-c3d37a81-3272-4787-ad90-375a9b19c5c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706432771 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.3706432771
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1822505535
Short name T347
Test name
Test status
Simulation time 498157457 ps
CPU time 1.28 seconds
Started Jul 17 07:04:24 PM PDT 24
Finished Jul 17 07:04:26 PM PDT 24
Peak memory 193260 kb
Host smart-121e32c1-7534-47e9-b9fd-1e7655612891
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822505535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1822505535
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3954825543
Short name T359
Test name
Test status
Simulation time 471131140 ps
CPU time 0.91 seconds
Started Jul 17 07:03:56 PM PDT 24
Finished Jul 17 07:03:59 PM PDT 24
Peak memory 183912 kb
Host smart-f306c8f4-c4b3-4120-9119-9b96650acd30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954825543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3954825543
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2760697765
Short name T292
Test name
Test status
Simulation time 281724478 ps
CPU time 0.77 seconds
Started Jul 17 07:04:07 PM PDT 24
Finished Jul 17 07:04:11 PM PDT 24
Peak memory 183808 kb
Host smart-424db799-282c-49b8-9b14-48721f47c1a8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760697765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2760697765
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2552896617
Short name T290
Test name
Test status
Simulation time 461224616 ps
CPU time 1.14 seconds
Started Jul 17 07:03:57 PM PDT 24
Finished Jul 17 07:04:01 PM PDT 24
Peak memory 183784 kb
Host smart-6ae8985e-ffa4-417b-afd0-0683bb23b7f6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552896617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2552896617
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2823954889
Short name T35
Test name
Test status
Simulation time 1317763146 ps
CPU time 2.1 seconds
Started Jul 17 07:04:32 PM PDT 24
Finished Jul 17 07:04:36 PM PDT 24
Peak memory 183880 kb
Host smart-52180743-c866-41fb-9a27-d7991a992cf7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823954889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.2823954889
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3100505030
Short name T383
Test name
Test status
Simulation time 357413594 ps
CPU time 1.87 seconds
Started Jul 17 07:04:09 PM PDT 24
Finished Jul 17 07:04:14 PM PDT 24
Peak memory 198800 kb
Host smart-5a40846b-9cc9-460c-87c5-02bab0573b96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100505030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3100505030
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2179067928
Short name T379
Test name
Test status
Simulation time 8297893130 ps
CPU time 13.74 seconds
Started Jul 17 07:04:07 PM PDT 24
Finished Jul 17 07:04:25 PM PDT 24
Peak memory 198292 kb
Host smart-ef974baa-4afd-407e-849b-9ba417bf05e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179067928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2179067928
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2583669654
Short name T68
Test name
Test status
Simulation time 493801955 ps
CPU time 1.55 seconds
Started Jul 17 07:04:32 PM PDT 24
Finished Jul 17 07:04:37 PM PDT 24
Peak memory 194764 kb
Host smart-20676fb7-42f5-4e32-afc1-944326712a88
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583669654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.2583669654
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1288393490
Short name T62
Test name
Test status
Simulation time 4681735831 ps
CPU time 4.2 seconds
Started Jul 17 07:04:29 PM PDT 24
Finished Jul 17 07:04:36 PM PDT 24
Peak memory 192332 kb
Host smart-1e1067b1-2443-4bf6-84b1-8b2e9769ef29
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288393490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1288393490
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.4071674386
Short name T310
Test name
Test status
Simulation time 1077540828 ps
CPU time 1.97 seconds
Started Jul 17 07:04:27 PM PDT 24
Finished Jul 17 07:04:32 PM PDT 24
Peak memory 193404 kb
Host smart-5e30d103-f16b-43a0-b0dc-0fb1c4a59b77
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071674386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.4071674386
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.769916852
Short name T335
Test name
Test status
Simulation time 402183944 ps
CPU time 0.72 seconds
Started Jul 17 07:04:28 PM PDT 24
Finished Jul 17 07:04:31 PM PDT 24
Peak memory 193168 kb
Host smart-78923393-d0d1-467b-9374-0e25df4b7311
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769916852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.769916852
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1561292794
Short name T422
Test name
Test status
Simulation time 484683678 ps
CPU time 0.76 seconds
Started Jul 17 07:04:29 PM PDT 24
Finished Jul 17 07:04:33 PM PDT 24
Peak memory 193132 kb
Host smart-5d18d9db-f0ef-4c9a-b1e2-6f9a09ec1042
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561292794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1561292794
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3656380888
Short name T395
Test name
Test status
Simulation time 317595785 ps
CPU time 0.82 seconds
Started Jul 17 07:04:23 PM PDT 24
Finished Jul 17 07:04:24 PM PDT 24
Peak memory 183808 kb
Host smart-dfb212fb-44c8-4205-b123-4945798524c4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656380888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3656380888
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.267736221
Short name T296
Test name
Test status
Simulation time 318210279 ps
CPU time 0.58 seconds
Started Jul 17 07:04:29 PM PDT 24
Finished Jul 17 07:04:32 PM PDT 24
Peak memory 183776 kb
Host smart-2ae262df-6409-4524-a387-274a71803878
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267736221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa
lk.267736221
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2574739550
Short name T321
Test name
Test status
Simulation time 1514611200 ps
CPU time 2.19 seconds
Started Jul 17 07:04:27 PM PDT 24
Finished Jul 17 07:04:32 PM PDT 24
Peak memory 194000 kb
Host smart-e585f063-f258-4b84-9746-4f9cc681f01d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574739550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2574739550
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1259427031
Short name T413
Test name
Test status
Simulation time 768721644 ps
CPU time 2.37 seconds
Started Jul 17 07:04:27 PM PDT 24
Finished Jul 17 07:04:33 PM PDT 24
Peak memory 198760 kb
Host smart-cae00446-9657-4001-b70b-225d53a94b6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259427031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1259427031
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3650808448
Short name T371
Test name
Test status
Simulation time 5006277784 ps
CPU time 1.22 seconds
Started Jul 17 07:04:24 PM PDT 24
Finished Jul 17 07:04:26 PM PDT 24
Peak memory 196496 kb
Host smart-e839ac8c-b3bf-4bf5-999b-f48aa801bef0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650808448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.3650808448
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3857237267
Short name T376
Test name
Test status
Simulation time 596403136 ps
CPU time 0.83 seconds
Started Jul 17 07:04:36 PM PDT 24
Finished Jul 17 07:04:39 PM PDT 24
Peak memory 196040 kb
Host smart-23c810aa-2ba0-4fcb-bfa2-df83132d4628
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857237267 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3857237267
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3103027457
Short name T345
Test name
Test status
Simulation time 503788633 ps
CPU time 0.79 seconds
Started Jul 17 07:04:36 PM PDT 24
Finished Jul 17 07:04:39 PM PDT 24
Peak memory 193460 kb
Host smart-0d916909-38f6-441f-9d0f-ee9d244fd522
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103027457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3103027457
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.199620634
Short name T384
Test name
Test status
Simulation time 322888063 ps
CPU time 0.97 seconds
Started Jul 17 07:04:36 PM PDT 24
Finished Jul 17 07:04:39 PM PDT 24
Peak memory 193072 kb
Host smart-0e01444a-fd1c-4806-8c45-a5656bb0dfcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199620634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.199620634
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2876392812
Short name T84
Test name
Test status
Simulation time 1178535914 ps
CPU time 1.89 seconds
Started Jul 17 07:04:35 PM PDT 24
Finished Jul 17 07:04:40 PM PDT 24
Peak memory 194136 kb
Host smart-c0ece6b0-6317-42f0-9b08-fbea85aef256
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876392812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.2876392812
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3746648970
Short name T333
Test name
Test status
Simulation time 485996741 ps
CPU time 1.58 seconds
Started Jul 17 07:04:35 PM PDT 24
Finished Jul 17 07:04:39 PM PDT 24
Peak memory 198700 kb
Host smart-1b911554-972e-47a6-ab3e-18ede3821080
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746648970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.3746648970
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3072673761
Short name T382
Test name
Test status
Simulation time 4060388073 ps
CPU time 6.54 seconds
Started Jul 17 07:04:35 PM PDT 24
Finished Jul 17 07:04:44 PM PDT 24
Peak memory 198156 kb
Host smart-0cd50641-0ef4-43e1-9674-1fd19ecd4f7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072673761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3072673761
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.892630802
Short name T366
Test name
Test status
Simulation time 396346968 ps
CPU time 0.98 seconds
Started Jul 17 07:04:30 PM PDT 24
Finished Jul 17 07:04:34 PM PDT 24
Peak memory 198548 kb
Host smart-76dd387a-9744-44ff-8342-4a51953e334d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892630802 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.892630802
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2563274795
Short name T407
Test name
Test status
Simulation time 569610088 ps
CPU time 0.67 seconds
Started Jul 17 07:04:31 PM PDT 24
Finished Jul 17 07:04:34 PM PDT 24
Peak memory 193072 kb
Host smart-9a9e72a4-74ea-4455-bd5f-7e9784207b39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563274795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2563274795
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2072543888
Short name T356
Test name
Test status
Simulation time 401350495 ps
CPU time 0.64 seconds
Started Jul 17 07:04:33 PM PDT 24
Finished Jul 17 07:04:37 PM PDT 24
Peak memory 183796 kb
Host smart-66ec061d-8e63-40b7-8421-d03ebe9ba7dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072543888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2072543888
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3023691195
Short name T396
Test name
Test status
Simulation time 1376964739 ps
CPU time 1.63 seconds
Started Jul 17 07:04:34 PM PDT 24
Finished Jul 17 07:04:39 PM PDT 24
Peak memory 183896 kb
Host smart-56f4d7d1-2c04-4a01-8b75-a7caf871ab59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023691195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.3023691195
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1085922748
Short name T370
Test name
Test status
Simulation time 739335118 ps
CPU time 1.78 seconds
Started Jul 17 07:04:33 PM PDT 24
Finished Jul 17 07:04:38 PM PDT 24
Peak memory 198724 kb
Host smart-09e7d4f4-f803-4c30-9458-5b4f8f31d4b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085922748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1085922748
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3337845242
Short name T380
Test name
Test status
Simulation time 487138650 ps
CPU time 1.34 seconds
Started Jul 17 07:04:36 PM PDT 24
Finished Jul 17 07:04:40 PM PDT 24
Peak memory 195568 kb
Host smart-907d86c5-9f2c-472d-a66c-b558918bab37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337845242 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.3337845242
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3704222699
Short name T67
Test name
Test status
Simulation time 488358008 ps
CPU time 1.3 seconds
Started Jul 17 07:04:35 PM PDT 24
Finished Jul 17 07:04:39 PM PDT 24
Peak memory 192160 kb
Host smart-ee91c9d9-4f8b-487b-8b3f-995b890ec9f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704222699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3704222699
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2363558177
Short name T388
Test name
Test status
Simulation time 293980643 ps
CPU time 0.64 seconds
Started Jul 17 07:04:35 PM PDT 24
Finished Jul 17 07:04:38 PM PDT 24
Peak memory 183860 kb
Host smart-f36bcef6-2e8a-4d2e-8e55-42e382054753
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363558177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2363558177
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.869774372
Short name T82
Test name
Test status
Simulation time 2334869148 ps
CPU time 1.4 seconds
Started Jul 17 07:04:32 PM PDT 24
Finished Jul 17 07:04:37 PM PDT 24
Peak memory 194180 kb
Host smart-efe9f630-e4fb-4fbe-acdb-8248252cc43f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869774372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon
_timer_same_csr_outstanding.869774372
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.4085791440
Short name T399
Test name
Test status
Simulation time 719909872 ps
CPU time 1.97 seconds
Started Jul 17 07:04:34 PM PDT 24
Finished Jul 17 07:04:39 PM PDT 24
Peak memory 198640 kb
Host smart-990943bb-d23f-41cb-a1e1-eac875a06d30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085791440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.4085791440
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3901565882
Short name T190
Test name
Test status
Simulation time 4403455566 ps
CPU time 2.28 seconds
Started Jul 17 07:04:33 PM PDT 24
Finished Jul 17 07:04:38 PM PDT 24
Peak memory 196836 kb
Host smart-c239c6f6-c0e3-4608-9e94-4d5a9a45d7c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901565882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.3901565882
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3277167782
Short name T195
Test name
Test status
Simulation time 553138908 ps
CPU time 0.9 seconds
Started Jul 17 07:04:27 PM PDT 24
Finished Jul 17 07:04:30 PM PDT 24
Peak memory 197352 kb
Host smart-75191a03-440e-4d51-bfc5-e7388910dc61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277167782 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3277167782
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1802722543
Short name T61
Test name
Test status
Simulation time 531623627 ps
CPU time 0.97 seconds
Started Jul 17 07:04:27 PM PDT 24
Finished Jul 17 07:04:31 PM PDT 24
Peak memory 192848 kb
Host smart-59f2cc7b-3d3b-48a2-9f4d-ae7b658c7a98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802722543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1802722543
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3931209004
Short name T329
Test name
Test status
Simulation time 332706375 ps
CPU time 0.91 seconds
Started Jul 17 07:04:28 PM PDT 24
Finished Jul 17 07:04:32 PM PDT 24
Peak memory 183924 kb
Host smart-33b0884c-e8df-437d-b4d3-de254f25c145
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931209004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3931209004
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3325700735
Short name T394
Test name
Test status
Simulation time 1995712121 ps
CPU time 2.26 seconds
Started Jul 17 07:04:25 PM PDT 24
Finished Jul 17 07:04:28 PM PDT 24
Peak memory 195184 kb
Host smart-78179254-af05-4c2f-abcd-84af466af543
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325700735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3325700735
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2154730883
Short name T287
Test name
Test status
Simulation time 610956322 ps
CPU time 1.66 seconds
Started Jul 17 07:04:31 PM PDT 24
Finished Jul 17 07:04:35 PM PDT 24
Peak memory 198688 kb
Host smart-44b24054-7349-4ec8-90e6-5e218142b70c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154730883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2154730883
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2818436344
Short name T37
Test name
Test status
Simulation time 4301376540 ps
CPU time 5.14 seconds
Started Jul 17 07:04:25 PM PDT 24
Finished Jul 17 07:04:32 PM PDT 24
Peak memory 197952 kb
Host smart-e47fbc12-74bc-45d3-aedc-cfc0477deb97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818436344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.2818436344
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3777360314
Short name T418
Test name
Test status
Simulation time 538138939 ps
CPU time 1.43 seconds
Started Jul 17 07:04:46 PM PDT 24
Finished Jul 17 07:04:51 PM PDT 24
Peak memory 196488 kb
Host smart-687c52ca-567e-4f8d-b8f8-855694985413
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777360314 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3777360314
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.365825113
Short name T59
Test name
Test status
Simulation time 509214173 ps
CPU time 0.71 seconds
Started Jul 17 07:04:45 PM PDT 24
Finished Jul 17 07:04:48 PM PDT 24
Peak memory 192156 kb
Host smart-29a3a3a0-a255-4e18-b086-ae141421c208
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365825113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.365825113
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2287819681
Short name T289
Test name
Test status
Simulation time 530290305 ps
CPU time 0.62 seconds
Started Jul 17 07:04:45 PM PDT 24
Finished Jul 17 07:04:47 PM PDT 24
Peak memory 193068 kb
Host smart-883ecf7a-cd28-444b-b8e9-5b45a4d8a4ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287819681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2287819681
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1202666630
Short name T330
Test name
Test status
Simulation time 900449934 ps
CPU time 1.86 seconds
Started Jul 17 07:04:45 PM PDT 24
Finished Jul 17 07:04:48 PM PDT 24
Peak memory 193748 kb
Host smart-d9be5d34-78f8-48fc-bf7c-ca2571b61e10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202666630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.1202666630
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3845205583
Short name T406
Test name
Test status
Simulation time 451842390 ps
CPU time 1.98 seconds
Started Jul 17 07:04:32 PM PDT 24
Finished Jul 17 07:04:37 PM PDT 24
Peak memory 198716 kb
Host smart-5ba11a1f-447c-496c-8e60-252785eed24c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845205583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.3845205583
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1780479924
Short name T318
Test name
Test status
Simulation time 8314706078 ps
CPU time 14.1 seconds
Started Jul 17 07:04:48 PM PDT 24
Finished Jul 17 07:05:06 PM PDT 24
Peak memory 198356 kb
Host smart-33ae03f7-97ad-4d8a-a30e-5e63c5aa186a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780479924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.1780479924
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3718956609
Short name T322
Test name
Test status
Simulation time 399661303 ps
CPU time 0.81 seconds
Started Jul 17 07:04:49 PM PDT 24
Finished Jul 17 07:04:53 PM PDT 24
Peak memory 196084 kb
Host smart-573cf66b-519d-427e-a9b0-f83853f6414e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718956609 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.3718956609
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.182107891
Short name T64
Test name
Test status
Simulation time 534894652 ps
CPU time 0.92 seconds
Started Jul 17 07:04:45 PM PDT 24
Finished Jul 17 07:04:49 PM PDT 24
Peak memory 193384 kb
Host smart-04d337b5-b581-4cab-bee1-0ecf0e5b6f8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182107891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.182107891
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1009204375
Short name T398
Test name
Test status
Simulation time 539567300 ps
CPU time 0.72 seconds
Started Jul 17 07:04:44 PM PDT 24
Finished Jul 17 07:04:45 PM PDT 24
Peak memory 193132 kb
Host smart-e90b2bc0-fb37-4942-8ab7-7883530fab6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009204375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.1009204375
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1943340062
Short name T83
Test name
Test status
Simulation time 1787995781 ps
CPU time 4.37 seconds
Started Jul 17 07:04:47 PM PDT 24
Finished Jul 17 07:04:55 PM PDT 24
Peak memory 193868 kb
Host smart-b28b2009-ccb7-44bf-aa2b-f957da00efa3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943340062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1943340062
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2939329859
Short name T421
Test name
Test status
Simulation time 705429327 ps
CPU time 1.41 seconds
Started Jul 17 07:04:45 PM PDT 24
Finished Jul 17 07:04:47 PM PDT 24
Peak memory 198936 kb
Host smart-81d8c2c4-7aa7-4837-9467-bce8b4995173
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939329859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2939329859
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3064261120
Short name T194
Test name
Test status
Simulation time 8213320587 ps
CPU time 7.81 seconds
Started Jul 17 07:04:46 PM PDT 24
Finished Jul 17 07:04:57 PM PDT 24
Peak memory 198420 kb
Host smart-927fa3d5-d291-46c1-9689-360d5b098394
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064261120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.3064261120
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1969183779
Short name T331
Test name
Test status
Simulation time 416833556 ps
CPU time 0.73 seconds
Started Jul 17 07:04:46 PM PDT 24
Finished Jul 17 07:04:50 PM PDT 24
Peak memory 196700 kb
Host smart-8c4e2e5d-566b-441d-943f-b7957aeb2909
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969183779 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1969183779
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1258762187
Short name T69
Test name
Test status
Simulation time 441753810 ps
CPU time 0.72 seconds
Started Jul 17 07:04:48 PM PDT 24
Finished Jul 17 07:04:53 PM PDT 24
Peak memory 193200 kb
Host smart-4e1ce8c6-e3ba-4848-aa84-d50598cd0b1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258762187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1258762187
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.4074963572
Short name T305
Test name
Test status
Simulation time 287665442 ps
CPU time 0.99 seconds
Started Jul 17 07:04:46 PM PDT 24
Finished Jul 17 07:04:50 PM PDT 24
Peak memory 193084 kb
Host smart-d9bbfaf6-a096-471b-b62f-170c89bcacc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074963572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.4074963572
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.4158852882
Short name T81
Test name
Test status
Simulation time 3222941635 ps
CPU time 4 seconds
Started Jul 17 07:04:46 PM PDT 24
Finished Jul 17 07:04:52 PM PDT 24
Peak memory 195484 kb
Host smart-6241feef-1bf9-4340-88aa-4e618c293cfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158852882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.4158852882
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2431658930
Short name T414
Test name
Test status
Simulation time 427350863 ps
CPU time 2.39 seconds
Started Jul 17 07:04:44 PM PDT 24
Finished Jul 17 07:04:48 PM PDT 24
Peak memory 198716 kb
Host smart-e44cd0c8-211b-492a-9fad-783cd2debfe4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431658930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2431658930
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3230141646
Short name T315
Test name
Test status
Simulation time 4647565639 ps
CPU time 5.93 seconds
Started Jul 17 07:04:51 PM PDT 24
Finished Jul 17 07:05:00 PM PDT 24
Peak memory 197788 kb
Host smart-a3d8f53c-d398-41ad-8971-30d1d9ad8a65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230141646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.3230141646
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1132186230
Short name T294
Test name
Test status
Simulation time 598766563 ps
CPU time 1.06 seconds
Started Jul 17 07:04:46 PM PDT 24
Finished Jul 17 07:04:51 PM PDT 24
Peak memory 196720 kb
Host smart-93731211-7678-48aa-930f-b492e0557c41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132186230 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.1132186230
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3272800170
Short name T57
Test name
Test status
Simulation time 491046181 ps
CPU time 1.33 seconds
Started Jul 17 07:04:45 PM PDT 24
Finished Jul 17 07:04:49 PM PDT 24
Peak memory 194128 kb
Host smart-2fbc697d-5538-433a-a21d-6e91302d40b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272800170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3272800170
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2309285694
Short name T391
Test name
Test status
Simulation time 461609575 ps
CPU time 0.67 seconds
Started Jul 17 07:04:46 PM PDT 24
Finished Jul 17 07:04:50 PM PDT 24
Peak memory 183868 kb
Host smart-e086ae36-eccd-4708-be8c-8765d3c63c1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309285694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2309285694
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.841737018
Short name T373
Test name
Test status
Simulation time 2578568674 ps
CPU time 5.41 seconds
Started Jul 17 07:04:48 PM PDT 24
Finished Jul 17 07:04:57 PM PDT 24
Peak memory 194088 kb
Host smart-35f986f0-0cc5-4059-9204-b398b70de517
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841737018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon
_timer_same_csr_outstanding.841737018
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.4218886306
Short name T410
Test name
Test status
Simulation time 384401974 ps
CPU time 1.96 seconds
Started Jul 17 07:04:45 PM PDT 24
Finished Jul 17 07:04:49 PM PDT 24
Peak memory 198760 kb
Host smart-58698afc-8bf0-43ee-a185-535ac00c7285
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218886306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.4218886306
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.493552811
Short name T191
Test name
Test status
Simulation time 8545326881 ps
CPU time 14.54 seconds
Started Jul 17 07:04:48 PM PDT 24
Finished Jul 17 07:05:06 PM PDT 24
Peak memory 198308 kb
Host smart-847eb8d0-ac32-404b-a360-df00ba348bad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493552811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.493552811
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1926934102
Short name T325
Test name
Test status
Simulation time 498059895 ps
CPU time 0.82 seconds
Started Jul 17 07:04:48 PM PDT 24
Finished Jul 17 07:04:52 PM PDT 24
Peak memory 196200 kb
Host smart-9153e99e-e979-4900-b568-c41167473e68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926934102 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1926934102
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2074401785
Short name T405
Test name
Test status
Simulation time 686163488 ps
CPU time 0.62 seconds
Started Jul 17 07:04:45 PM PDT 24
Finished Jul 17 07:04:48 PM PDT 24
Peak memory 193112 kb
Host smart-d42d9fc3-6680-4fb5-96a5-a4f4da76097c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074401785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2074401785
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.148534147
Short name T336
Test name
Test status
Simulation time 363274019 ps
CPU time 0.97 seconds
Started Jul 17 07:04:48 PM PDT 24
Finished Jul 17 07:04:53 PM PDT 24
Peak memory 183872 kb
Host smart-c03c52c1-3261-4a2a-b6c0-aed061152f19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148534147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.148534147
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.312671222
Short name T346
Test name
Test status
Simulation time 1326266505 ps
CPU time 1.49 seconds
Started Jul 17 07:04:47 PM PDT 24
Finished Jul 17 07:04:52 PM PDT 24
Peak memory 193824 kb
Host smart-69a1bb75-1922-4f61-983e-2fdb229e7ae8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312671222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon
_timer_same_csr_outstanding.312671222
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1968120031
Short name T350
Test name
Test status
Simulation time 648691195 ps
CPU time 2.16 seconds
Started Jul 17 07:04:51 PM PDT 24
Finished Jul 17 07:04:56 PM PDT 24
Peak memory 198696 kb
Host smart-c1be5b2b-7d1f-4f28-ac22-ec19331b37cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968120031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1968120031
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2055398201
Short name T337
Test name
Test status
Simulation time 4180304548 ps
CPU time 7.19 seconds
Started Jul 17 07:04:46 PM PDT 24
Finished Jul 17 07:04:57 PM PDT 24
Peak memory 198076 kb
Host smart-dd73dfc7-ec62-4b22-b3fd-80b5f1526e79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055398201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.2055398201
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.946943370
Short name T397
Test name
Test status
Simulation time 491015592 ps
CPU time 1.52 seconds
Started Jul 17 07:04:50 PM PDT 24
Finished Jul 17 07:04:56 PM PDT 24
Peak memory 196224 kb
Host smart-a5f73d0a-d38f-4992-8d81-344e9ab44832
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946943370 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.946943370
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.445145133
Short name T341
Test name
Test status
Simulation time 452633101 ps
CPU time 0.6 seconds
Started Jul 17 07:04:45 PM PDT 24
Finished Jul 17 07:04:47 PM PDT 24
Peak memory 193412 kb
Host smart-5ac9733c-8b76-4c16-9295-857aecc62009
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445145133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.445145133
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1784169874
Short name T416
Test name
Test status
Simulation time 501702930 ps
CPU time 1.2 seconds
Started Jul 17 07:04:47 PM PDT 24
Finished Jul 17 07:04:51 PM PDT 24
Peak memory 193084 kb
Host smart-fe6d2c67-c44f-4eb6-9e9e-aef6f374f011
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784169874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.1784169874
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.4250044852
Short name T320
Test name
Test status
Simulation time 1423184926 ps
CPU time 0.9 seconds
Started Jul 17 07:04:45 PM PDT 24
Finished Jul 17 07:04:47 PM PDT 24
Peak memory 183900 kb
Host smart-568b9724-1509-43e4-a87c-5451b010df91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250044852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.4250044852
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.136332421
Short name T295
Test name
Test status
Simulation time 1104800841 ps
CPU time 1.97 seconds
Started Jul 17 07:04:47 PM PDT 24
Finished Jul 17 07:04:53 PM PDT 24
Peak memory 198764 kb
Host smart-685b7444-c6a2-4775-8eae-a06cb5ec8801
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136332421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.136332421
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3230256856
Short name T354
Test name
Test status
Simulation time 4680308438 ps
CPU time 2.68 seconds
Started Jul 17 07:04:48 PM PDT 24
Finished Jul 17 07:04:54 PM PDT 24
Peak memory 197904 kb
Host smart-2c9bc782-de02-4a61-8a0f-42a906f57640
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230256856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.3230256856
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3383483877
Short name T34
Test name
Test status
Simulation time 482518568 ps
CPU time 1.1 seconds
Started Jul 17 07:04:31 PM PDT 24
Finished Jul 17 07:04:35 PM PDT 24
Peak memory 194708 kb
Host smart-2027e56f-ea46-4827-9fd1-0912c7d2a3c5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383483877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.3383483877
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1206498367
Short name T65
Test name
Test status
Simulation time 13515831351 ps
CPU time 18.23 seconds
Started Jul 17 07:04:28 PM PDT 24
Finished Jul 17 07:04:49 PM PDT 24
Peak memory 192348 kb
Host smart-da02a061-988e-4603-88e4-d8e3358732d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206498367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1206498367
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.839922223
Short name T343
Test name
Test status
Simulation time 1421363756 ps
CPU time 1.5 seconds
Started Jul 17 07:04:25 PM PDT 24
Finished Jul 17 07:04:28 PM PDT 24
Peak memory 192940 kb
Host smart-86896487-2715-4d01-b7c4-9b709401f3fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839922223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw
_reset.839922223
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2416654413
Short name T363
Test name
Test status
Simulation time 622745524 ps
CPU time 0.9 seconds
Started Jul 17 07:04:27 PM PDT 24
Finished Jul 17 07:04:30 PM PDT 24
Peak memory 196656 kb
Host smart-021af112-f4e0-4205-a713-a6a08fd06790
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416654413 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.2416654413
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.447818896
Short name T33
Test name
Test status
Simulation time 551319246 ps
CPU time 0.81 seconds
Started Jul 17 07:04:29 PM PDT 24
Finished Jul 17 07:04:33 PM PDT 24
Peak memory 193320 kb
Host smart-ae17fa72-0616-438e-91ae-5921b66c8bd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447818896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.447818896
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3455179252
Short name T303
Test name
Test status
Simulation time 326451149 ps
CPU time 0.95 seconds
Started Jul 17 07:04:34 PM PDT 24
Finished Jul 17 07:04:38 PM PDT 24
Peak memory 193088 kb
Host smart-152a9d22-24a2-4d64-870d-1dde9ee6a068
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455179252 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3455179252
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1479012904
Short name T353
Test name
Test status
Simulation time 343204349 ps
CPU time 0.63 seconds
Started Jul 17 07:04:26 PM PDT 24
Finished Jul 17 07:04:29 PM PDT 24
Peak memory 183784 kb
Host smart-cca61d0a-fc7f-429a-a321-d6970d2e6eea
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479012904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.1479012904
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2879144178
Short name T291
Test name
Test status
Simulation time 322555603 ps
CPU time 0.92 seconds
Started Jul 17 07:04:32 PM PDT 24
Finished Jul 17 07:04:36 PM PDT 24
Peak memory 183784 kb
Host smart-46e8938a-8f74-462e-9499-1f22a29ff59d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879144178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.2879144178
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3707520831
Short name T317
Test name
Test status
Simulation time 2240349972 ps
CPU time 2.34 seconds
Started Jul 17 07:04:24 PM PDT 24
Finished Jul 17 07:04:27 PM PDT 24
Peak memory 192120 kb
Host smart-f8282230-d008-44e5-9874-32b5a009a3e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707520831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.3707520831
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1398506964
Short name T334
Test name
Test status
Simulation time 635537460 ps
CPU time 2.08 seconds
Started Jul 17 07:04:25 PM PDT 24
Finished Jul 17 07:04:28 PM PDT 24
Peak memory 198944 kb
Host smart-fc73d654-d3d7-47d4-a54c-8e77adde9604
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398506964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1398506964
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.4271368854
Short name T348
Test name
Test status
Simulation time 4354669378 ps
CPU time 1.39 seconds
Started Jul 17 07:04:30 PM PDT 24
Finished Jul 17 07:04:34 PM PDT 24
Peak memory 196708 kb
Host smart-74716efb-2229-4ce4-89cf-e02e160f36ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271368854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.4271368854
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.968341102
Short name T319
Test name
Test status
Simulation time 428062918 ps
CPU time 0.86 seconds
Started Jul 17 07:04:46 PM PDT 24
Finished Jul 17 07:04:49 PM PDT 24
Peak memory 183864 kb
Host smart-08707632-5826-49bb-b589-94f2237cfdd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968341102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.968341102
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2138753480
Short name T308
Test name
Test status
Simulation time 285523645 ps
CPU time 0.7 seconds
Started Jul 17 07:04:49 PM PDT 24
Finished Jul 17 07:04:54 PM PDT 24
Peak memory 183876 kb
Host smart-f197caeb-7ea7-4021-9146-59ffad15a110
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138753480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2138753480
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3011912553
Short name T401
Test name
Test status
Simulation time 521237395 ps
CPU time 0.84 seconds
Started Jul 17 07:04:46 PM PDT 24
Finished Jul 17 07:04:51 PM PDT 24
Peak memory 183868 kb
Host smart-8b68407d-7f75-4c09-8016-35cfe5aba0e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011912553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.3011912553
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3937921609
Short name T288
Test name
Test status
Simulation time 340538772 ps
CPU time 0.62 seconds
Started Jul 17 07:04:45 PM PDT 24
Finished Jul 17 07:04:48 PM PDT 24
Peak memory 193076 kb
Host smart-60f12872-a279-4b91-8057-d62f5212e7d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937921609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3937921609
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3018317687
Short name T309
Test name
Test status
Simulation time 452403872 ps
CPU time 0.7 seconds
Started Jul 17 07:04:45 PM PDT 24
Finished Jul 17 07:04:47 PM PDT 24
Peak memory 183848 kb
Host smart-5a1b62e3-2411-405e-a4ed-6ff5b9834493
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018317687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3018317687
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3018898464
Short name T372
Test name
Test status
Simulation time 386875432 ps
CPU time 0.73 seconds
Started Jul 17 07:04:49 PM PDT 24
Finished Jul 17 07:04:54 PM PDT 24
Peak memory 193084 kb
Host smart-15f52387-0a56-4a7f-a885-b486b1b9d137
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018898464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3018898464
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3084722404
Short name T300
Test name
Test status
Simulation time 425092684 ps
CPU time 1.03 seconds
Started Jul 17 07:04:49 PM PDT 24
Finished Jul 17 07:04:53 PM PDT 24
Peak memory 183864 kb
Host smart-687bfae1-4375-422d-8e3a-25792131d4dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084722404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3084722404
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2751274998
Short name T392
Test name
Test status
Simulation time 427109944 ps
CPU time 0.66 seconds
Started Jul 17 07:04:47 PM PDT 24
Finished Jul 17 07:04:51 PM PDT 24
Peak memory 183880 kb
Host smart-5e1ea247-ded2-4e72-9d79-154c1c1f07d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751274998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2751274998
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1598657769
Short name T342
Test name
Test status
Simulation time 439703673 ps
CPU time 1.12 seconds
Started Jul 17 07:04:47 PM PDT 24
Finished Jul 17 07:04:52 PM PDT 24
Peak memory 183908 kb
Host smart-bb1df316-9a73-4c98-bf9b-5b39e880df33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598657769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1598657769
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2331072551
Short name T403
Test name
Test status
Simulation time 482080634 ps
CPU time 1.21 seconds
Started Jul 17 07:04:48 PM PDT 24
Finished Jul 17 07:04:52 PM PDT 24
Peak memory 183892 kb
Host smart-6136f625-672a-487e-8367-a64831fa4d77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331072551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2331072551
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1272821834
Short name T338
Test name
Test status
Simulation time 471858902 ps
CPU time 0.87 seconds
Started Jul 17 07:04:30 PM PDT 24
Finished Jul 17 07:04:34 PM PDT 24
Peak memory 193328 kb
Host smart-b1b64b49-511d-4d67-bae7-0da8fef5609e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272821834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1272821834
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.479857455
Short name T60
Test name
Test status
Simulation time 4372712972 ps
CPU time 5.54 seconds
Started Jul 17 07:04:27 PM PDT 24
Finished Jul 17 07:04:35 PM PDT 24
Peak memory 184120 kb
Host smart-76203abb-35b2-4cc2-a0fc-d8163c94a09e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479857455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bi
t_bash.479857455
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.723313118
Short name T419
Test name
Test status
Simulation time 1027366151 ps
CPU time 2.05 seconds
Started Jul 17 07:04:33 PM PDT 24
Finished Jul 17 07:04:38 PM PDT 24
Peak memory 194084 kb
Host smart-d7bbf8d3-dfce-416d-8127-6edecba414ad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723313118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw
_reset.723313118
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.4100178671
Short name T420
Test name
Test status
Simulation time 584152882 ps
CPU time 1.11 seconds
Started Jul 17 07:04:28 PM PDT 24
Finished Jul 17 07:04:32 PM PDT 24
Peak memory 197468 kb
Host smart-ee7a7c59-86ad-4d03-8b80-01b30a704ba8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100178671 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.4100178671
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3407891624
Short name T283
Test name
Test status
Simulation time 474380937 ps
CPU time 1.12 seconds
Started Jul 17 07:04:25 PM PDT 24
Finished Jul 17 07:04:27 PM PDT 24
Peak memory 183852 kb
Host smart-e7828096-3af5-4aa1-b3d7-e1efe2862c8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407891624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3407891624
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1201525764
Short name T357
Test name
Test status
Simulation time 480918395 ps
CPU time 0.61 seconds
Started Jul 17 07:04:28 PM PDT 24
Finished Jul 17 07:04:31 PM PDT 24
Peak memory 183820 kb
Host smart-d355f351-e8c4-47dd-94d5-3ddd31fce301
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201525764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.1201525764
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2860120477
Short name T332
Test name
Test status
Simulation time 433609940 ps
CPU time 0.58 seconds
Started Jul 17 07:04:26 PM PDT 24
Finished Jul 17 07:04:28 PM PDT 24
Peak memory 183808 kb
Host smart-8443be90-eb9a-4932-a616-90281fe94d78
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860120477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2860120477
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1432007588
Short name T80
Test name
Test status
Simulation time 1372088143 ps
CPU time 1.06 seconds
Started Jul 17 07:04:32 PM PDT 24
Finished Jul 17 07:04:36 PM PDT 24
Peak memory 192080 kb
Host smart-dc573b0f-7c44-4b2b-b60a-9bdac0517657
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432007588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1432007588
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.968191289
Short name T415
Test name
Test status
Simulation time 534920449 ps
CPU time 1.45 seconds
Started Jul 17 07:04:28 PM PDT 24
Finished Jul 17 07:04:33 PM PDT 24
Peak memory 198696 kb
Host smart-f0c46afb-7f75-41fe-a5eb-c25e883bde45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968191289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.968191289
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.768398124
Short name T192
Test name
Test status
Simulation time 8381452044 ps
CPU time 12.92 seconds
Started Jul 17 07:04:25 PM PDT 24
Finished Jul 17 07:04:39 PM PDT 24
Peak memory 198328 kb
Host smart-8a74e0f4-1bc9-4cbe-b247-0e0e05b4d5df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768398124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.768398124
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1576003347
Short name T307
Test name
Test status
Simulation time 474651810 ps
CPU time 0.89 seconds
Started Jul 17 07:04:48 PM PDT 24
Finished Jul 17 07:04:53 PM PDT 24
Peak memory 183872 kb
Host smart-e9951f17-c4dd-4e58-a437-5217e7716fc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576003347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1576003347
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.408485537
Short name T360
Test name
Test status
Simulation time 315164622 ps
CPU time 1.04 seconds
Started Jul 17 07:04:49 PM PDT 24
Finished Jul 17 07:04:54 PM PDT 24
Peak memory 183904 kb
Host smart-88629d9a-7878-480a-be00-27fc562875f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408485537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.408485537
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1369114265
Short name T327
Test name
Test status
Simulation time 340726585 ps
CPU time 0.74 seconds
Started Jul 17 07:04:50 PM PDT 24
Finished Jul 17 07:04:54 PM PDT 24
Peak memory 193084 kb
Host smart-eedbd3a5-5f15-4eba-a571-1df7c8c89b9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369114265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1369114265
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3750872580
Short name T411
Test name
Test status
Simulation time 532572861 ps
CPU time 0.6 seconds
Started Jul 17 07:04:48 PM PDT 24
Finished Jul 17 07:04:52 PM PDT 24
Peak memory 183892 kb
Host smart-bf357c47-f4a1-4e24-a4ae-f326cd24f3b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750872580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3750872580
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.915077194
Short name T368
Test name
Test status
Simulation time 327710948 ps
CPU time 0.63 seconds
Started Jul 17 07:04:48 PM PDT 24
Finished Jul 17 07:04:52 PM PDT 24
Peak memory 183864 kb
Host smart-71fa61da-e246-42f5-b2c4-2a5b0e60e803
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915077194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.915077194
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2848456894
Short name T409
Test name
Test status
Simulation time 340027105 ps
CPU time 0.79 seconds
Started Jul 17 07:04:46 PM PDT 24
Finished Jul 17 07:04:50 PM PDT 24
Peak memory 183884 kb
Host smart-bdd7a415-1fe5-406e-acb0-9b53944c45b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848456894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2848456894
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.175240615
Short name T323
Test name
Test status
Simulation time 387067464 ps
CPU time 0.81 seconds
Started Jul 17 07:04:49 PM PDT 24
Finished Jul 17 07:04:54 PM PDT 24
Peak memory 183864 kb
Host smart-947cc7f8-e1dd-44cc-8a7b-776e9952023d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175240615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.175240615
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2217878685
Short name T285
Test name
Test status
Simulation time 308951487 ps
CPU time 0.67 seconds
Started Jul 17 07:04:50 PM PDT 24
Finished Jul 17 07:04:54 PM PDT 24
Peak memory 183872 kb
Host smart-7435b336-3118-46a6-a95b-63b7f44dcece
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217878685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2217878685
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2299338517
Short name T339
Test name
Test status
Simulation time 326963725 ps
CPU time 0.83 seconds
Started Jul 17 07:04:50 PM PDT 24
Finished Jul 17 07:04:55 PM PDT 24
Peak memory 183868 kb
Host smart-66fc874a-1073-4913-aea0-62fae2d7aed9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299338517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.2299338517
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.607182516
Short name T374
Test name
Test status
Simulation time 419975121 ps
CPU time 1.15 seconds
Started Jul 17 07:04:55 PM PDT 24
Finished Jul 17 07:04:58 PM PDT 24
Peak memory 183896 kb
Host smart-b1a6f201-0e93-4a11-a05b-e55475b55cee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607182516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.607182516
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.4104911124
Short name T58
Test name
Test status
Simulation time 467635975 ps
CPU time 0.8 seconds
Started Jul 17 07:04:26 PM PDT 24
Finished Jul 17 07:04:29 PM PDT 24
Peak memory 183868 kb
Host smart-14ea3057-155e-4637-93f8-2605b87cb21b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104911124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.4104911124
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3554636662
Short name T66
Test name
Test status
Simulation time 12804631975 ps
CPU time 8.67 seconds
Started Jul 17 07:04:31 PM PDT 24
Finished Jul 17 07:04:42 PM PDT 24
Peak memory 192352 kb
Host smart-02e12d65-2c8a-405f-805e-87f4782074b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554636662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.3554636662
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2648786203
Short name T369
Test name
Test status
Simulation time 682902008 ps
CPU time 0.73 seconds
Started Jul 17 07:04:32 PM PDT 24
Finished Jul 17 07:04:36 PM PDT 24
Peak memory 192216 kb
Host smart-fa75e614-ce3e-4407-9c46-efce9995edcc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648786203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.2648786203
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2696589300
Short name T417
Test name
Test status
Simulation time 521103772 ps
CPU time 1.5 seconds
Started Jul 17 07:04:27 PM PDT 24
Finished Jul 17 07:04:31 PM PDT 24
Peak memory 196812 kb
Host smart-394da0d6-bc76-4959-b5da-6d5aa1df0999
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696589300 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.2696589300
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2687041190
Short name T311
Test name
Test status
Simulation time 368543528 ps
CPU time 0.82 seconds
Started Jul 17 07:04:24 PM PDT 24
Finished Jul 17 07:04:25 PM PDT 24
Peak memory 193124 kb
Host smart-ed281a25-61cc-48b6-b008-51cb97a4d791
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687041190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2687041190
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1114863343
Short name T316
Test name
Test status
Simulation time 554763462 ps
CPU time 0.65 seconds
Started Jul 17 07:04:23 PM PDT 24
Finished Jul 17 07:04:24 PM PDT 24
Peak memory 183880 kb
Host smart-70cb12b0-3d66-4a34-a0e9-d68d916d5b1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114863343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1114863343
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1007346639
Short name T349
Test name
Test status
Simulation time 494795423 ps
CPU time 1.32 seconds
Started Jul 17 07:04:23 PM PDT 24
Finished Jul 17 07:04:26 PM PDT 24
Peak memory 183820 kb
Host smart-696e808d-4eef-4142-a8b8-16f10b015c77
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007346639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.1007346639
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3767202983
Short name T377
Test name
Test status
Simulation time 440819030 ps
CPU time 1.1 seconds
Started Jul 17 07:04:28 PM PDT 24
Finished Jul 17 07:04:32 PM PDT 24
Peak memory 183796 kb
Host smart-87277057-e075-4c5e-ad91-2b7f3410473f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767202983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.3767202983
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.996071257
Short name T313
Test name
Test status
Simulation time 1375337765 ps
CPU time 2.16 seconds
Started Jul 17 07:04:26 PM PDT 24
Finished Jul 17 07:04:31 PM PDT 24
Peak memory 194192 kb
Host smart-7fe35382-24b9-4d74-bd59-77d907611354
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996071257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_
timer_same_csr_outstanding.996071257
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.4078646314
Short name T299
Test name
Test status
Simulation time 519504851 ps
CPU time 2.4 seconds
Started Jul 17 07:04:29 PM PDT 24
Finished Jul 17 07:04:34 PM PDT 24
Peak memory 198764 kb
Host smart-d7395644-cf68-4dcf-8cf5-75ca66eccf39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078646314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.4078646314
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1058006925
Short name T358
Test name
Test status
Simulation time 4254229251 ps
CPU time 2.14 seconds
Started Jul 17 07:04:24 PM PDT 24
Finished Jul 17 07:04:28 PM PDT 24
Peak memory 198208 kb
Host smart-dd768cd9-23e7-4564-a2df-d414add30c6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058006925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1058006925
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.230510470
Short name T302
Test name
Test status
Simulation time 461684589 ps
CPU time 0.67 seconds
Started Jul 17 07:04:55 PM PDT 24
Finished Jul 17 07:04:57 PM PDT 24
Peak memory 183900 kb
Host smart-dbcbabea-6d89-4917-99c1-b3641fb0b197
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230510470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.230510470
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2921413248
Short name T286
Test name
Test status
Simulation time 471379537 ps
CPU time 0.87 seconds
Started Jul 17 07:04:55 PM PDT 24
Finished Jul 17 07:04:57 PM PDT 24
Peak memory 183848 kb
Host smart-d6c33f67-96b2-4d98-996e-1280245c68fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921413248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2921413248
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3816549989
Short name T298
Test name
Test status
Simulation time 404257660 ps
CPU time 1.15 seconds
Started Jul 17 07:04:55 PM PDT 24
Finished Jul 17 07:04:58 PM PDT 24
Peak memory 183872 kb
Host smart-cb8a7003-ae7d-41ff-8ed8-f4a4530e4d66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816549989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.3816549989
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3550013672
Short name T328
Test name
Test status
Simulation time 429374604 ps
CPU time 0.64 seconds
Started Jul 17 07:04:47 PM PDT 24
Finished Jul 17 07:04:51 PM PDT 24
Peak memory 183796 kb
Host smart-143321c9-ffbf-40ea-80d8-f803ab094605
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550013672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.3550013672
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.4290828760
Short name T314
Test name
Test status
Simulation time 314749361 ps
CPU time 0.96 seconds
Started Jul 17 07:04:55 PM PDT 24
Finished Jul 17 07:04:57 PM PDT 24
Peak memory 193104 kb
Host smart-c41a9dfd-5560-4134-8e41-93cbbf1f2abe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290828760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.4290828760
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1552146320
Short name T352
Test name
Test status
Simulation time 438376333 ps
CPU time 1.19 seconds
Started Jul 17 07:04:58 PM PDT 24
Finished Jul 17 07:05:00 PM PDT 24
Peak memory 193100 kb
Host smart-5697fed2-df4e-4f52-a05f-cd2ac465bb34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552146320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1552146320
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2935367362
Short name T402
Test name
Test status
Simulation time 324401493 ps
CPU time 0.76 seconds
Started Jul 17 07:04:58 PM PDT 24
Finished Jul 17 07:04:59 PM PDT 24
Peak memory 193100 kb
Host smart-4b46ba02-538a-4e26-8c1d-d92a563e05dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935367362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2935367362
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3334961396
Short name T312
Test name
Test status
Simulation time 296753340 ps
CPU time 0.73 seconds
Started Jul 17 07:04:52 PM PDT 24
Finished Jul 17 07:04:55 PM PDT 24
Peak memory 183868 kb
Host smart-bf469e0e-b605-463a-b06c-2097cede9400
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334961396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3334961396
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.786605842
Short name T408
Test name
Test status
Simulation time 477020266 ps
CPU time 1.27 seconds
Started Jul 17 07:04:52 PM PDT 24
Finished Jul 17 07:04:56 PM PDT 24
Peak memory 193092 kb
Host smart-816bc2fa-d9c1-403a-9c9b-f615d87f3844
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786605842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.786605842
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.428297499
Short name T304
Test name
Test status
Simulation time 486608044 ps
CPU time 0.61 seconds
Started Jul 17 07:04:58 PM PDT 24
Finished Jul 17 07:05:00 PM PDT 24
Peak memory 193100 kb
Host smart-f7b5d308-1698-4e43-9aa0-f700a8ea6b26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428297499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.428297499
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2579878407
Short name T381
Test name
Test status
Simulation time 497599414 ps
CPU time 0.86 seconds
Started Jul 17 07:04:26 PM PDT 24
Finished Jul 17 07:04:29 PM PDT 24
Peak memory 196292 kb
Host smart-134dea86-5da2-4839-aeef-0a6ff3f8d105
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579878407 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.2579878407
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.39988004
Short name T301
Test name
Test status
Simulation time 571390509 ps
CPU time 0.61 seconds
Started Jul 17 07:04:28 PM PDT 24
Finished Jul 17 07:04:31 PM PDT 24
Peak memory 192136 kb
Host smart-21754243-321a-4316-8ff1-67bb2d0f65e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39988004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.39988004
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3115125308
Short name T361
Test name
Test status
Simulation time 424197032 ps
CPU time 0.92 seconds
Started Jul 17 07:04:26 PM PDT 24
Finished Jul 17 07:04:28 PM PDT 24
Peak memory 183884 kb
Host smart-59abd5fc-d527-48f1-8895-dde7bbdae8c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115125308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3115125308
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2038500977
Short name T389
Test name
Test status
Simulation time 1255713761 ps
CPU time 1.33 seconds
Started Jul 17 07:04:28 PM PDT 24
Finished Jul 17 07:04:32 PM PDT 24
Peak memory 193624 kb
Host smart-634ee06a-124d-40b8-bbaf-532ad415656d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038500977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2038500977
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3249392303
Short name T362
Test name
Test status
Simulation time 1139583790 ps
CPU time 2.33 seconds
Started Jul 17 07:04:28 PM PDT 24
Finished Jul 17 07:04:34 PM PDT 24
Peak memory 198720 kb
Host smart-e8fd27df-15f6-40ce-918c-5f716d1cd696
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249392303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3249392303
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2513589832
Short name T412
Test name
Test status
Simulation time 8590535828 ps
CPU time 2.56 seconds
Started Jul 17 07:04:29 PM PDT 24
Finished Jul 17 07:04:34 PM PDT 24
Peak memory 198164 kb
Host smart-cbec3a3c-b0f8-40ab-a4d5-a3b0f8db82b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513589832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2513589832
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2477066010
Short name T386
Test name
Test status
Simulation time 434758764 ps
CPU time 1.05 seconds
Started Jul 17 07:04:31 PM PDT 24
Finished Jul 17 07:04:35 PM PDT 24
Peak memory 197452 kb
Host smart-33c916ba-051d-4b25-a24f-122ca9647e06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477066010 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.2477066010
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2417451723
Short name T351
Test name
Test status
Simulation time 504478527 ps
CPU time 1.07 seconds
Started Jul 17 07:04:30 PM PDT 24
Finished Jul 17 07:04:34 PM PDT 24
Peak memory 193124 kb
Host smart-c8515274-d424-401c-bedd-2ce1ace9712e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417451723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.2417451723
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1918872085
Short name T284
Test name
Test status
Simulation time 301526615 ps
CPU time 0.63 seconds
Started Jul 17 07:04:31 PM PDT 24
Finished Jul 17 07:04:35 PM PDT 24
Peak memory 183868 kb
Host smart-c8140a16-74c1-40fa-b910-8bb2267670de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918872085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.1918872085
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2726668167
Short name T385
Test name
Test status
Simulation time 1299196490 ps
CPU time 1.54 seconds
Started Jul 17 07:04:34 PM PDT 24
Finished Jul 17 07:04:38 PM PDT 24
Peak memory 193900 kb
Host smart-dd4d98cf-4a1a-4a56-9594-ff2b3317e39a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726668167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2726668167
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.713368512
Short name T367
Test name
Test status
Simulation time 554916150 ps
CPU time 1.88 seconds
Started Jul 17 07:04:28 PM PDT 24
Finished Jul 17 07:04:33 PM PDT 24
Peak memory 198548 kb
Host smart-67364167-9c8b-476a-a600-a54160122405
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713368512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.713368512
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3088370143
Short name T326
Test name
Test status
Simulation time 365160886 ps
CPU time 1.17 seconds
Started Jul 17 07:04:35 PM PDT 24
Finished Jul 17 07:04:39 PM PDT 24
Peak memory 196260 kb
Host smart-87f6a865-f39a-4462-8e44-01724594943c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088370143 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.3088370143
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.514571318
Short name T56
Test name
Test status
Simulation time 544945066 ps
CPU time 0.74 seconds
Started Jul 17 07:07:52 PM PDT 24
Finished Jul 17 07:08:03 PM PDT 24
Peak memory 192048 kb
Host smart-594b717a-5bea-489a-8a69-6ce11a6834e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514571318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.514571318
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.4121879635
Short name T400
Test name
Test status
Simulation time 493759456 ps
CPU time 0.7 seconds
Started Jul 17 07:04:30 PM PDT 24
Finished Jul 17 07:04:34 PM PDT 24
Peak memory 193140 kb
Host smart-65a365b0-6aed-4925-8dbb-c8701971f4fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121879635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.4121879635
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1012228548
Short name T85
Test name
Test status
Simulation time 1421962188 ps
CPU time 1.06 seconds
Started Jul 17 07:04:35 PM PDT 24
Finished Jul 17 07:04:39 PM PDT 24
Peak memory 193036 kb
Host smart-cc4da68a-0a23-42f9-add3-ad67b4038b7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012228548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.1012228548
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1433115586
Short name T375
Test name
Test status
Simulation time 1548671951 ps
CPU time 2.06 seconds
Started Jul 17 07:04:35 PM PDT 24
Finished Jul 17 07:04:40 PM PDT 24
Peak memory 198692 kb
Host smart-5d5bdd03-39e5-4ebe-89b0-f3f81c854a00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433115586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.1433115586
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1675819539
Short name T193
Test name
Test status
Simulation time 8144509615 ps
CPU time 12.93 seconds
Started Jul 17 07:04:33 PM PDT 24
Finished Jul 17 07:04:50 PM PDT 24
Peak memory 198244 kb
Host smart-6edee66b-ec72-4910-ac41-c9a45cd25cdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675819539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1675819539
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2155294644
Short name T393
Test name
Test status
Simulation time 439920437 ps
CPU time 0.94 seconds
Started Jul 17 07:04:28 PM PDT 24
Finished Jul 17 07:04:31 PM PDT 24
Peak memory 196216 kb
Host smart-527938b0-9a96-4867-83be-87789298b7e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155294644 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2155294644
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.312084449
Short name T344
Test name
Test status
Simulation time 436943933 ps
CPU time 0.71 seconds
Started Jul 17 07:04:31 PM PDT 24
Finished Jul 17 07:04:35 PM PDT 24
Peak memory 193104 kb
Host smart-b957fca3-3231-4b14-ada2-11bc45a0b693
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312084449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.312084449
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2442857742
Short name T378
Test name
Test status
Simulation time 449722679 ps
CPU time 0.66 seconds
Started Jul 17 07:04:34 PM PDT 24
Finished Jul 17 07:04:38 PM PDT 24
Peak memory 183864 kb
Host smart-0650a45b-63bf-47cf-b70a-3b89e0d60c47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442857742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2442857742
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1272250408
Short name T365
Test name
Test status
Simulation time 1006772942 ps
CPU time 1.42 seconds
Started Jul 17 07:04:31 PM PDT 24
Finished Jul 17 07:04:35 PM PDT 24
Peak memory 193528 kb
Host smart-7befa213-4480-4b4d-ad27-b4483cb523ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272250408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1272250408
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2624238400
Short name T297
Test name
Test status
Simulation time 298694379 ps
CPU time 1.41 seconds
Started Jul 17 07:04:30 PM PDT 24
Finished Jul 17 07:04:35 PM PDT 24
Peak memory 198548 kb
Host smart-daa7dba5-3c67-40c3-893d-b686838686aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624238400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2624238400
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1865200007
Short name T324
Test name
Test status
Simulation time 4114155484 ps
CPU time 2.22 seconds
Started Jul 17 07:04:34 PM PDT 24
Finished Jul 17 07:04:39 PM PDT 24
Peak memory 197792 kb
Host smart-47638e9c-cef1-4dba-bdc0-1240bd1b1c5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865200007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.1865200007
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.4027929541
Short name T340
Test name
Test status
Simulation time 599187987 ps
CPU time 0.92 seconds
Started Jul 17 07:04:36 PM PDT 24
Finished Jul 17 07:04:39 PM PDT 24
Peak memory 197000 kb
Host smart-a7fd9d55-0aa4-4a07-874c-0c4ba9be37a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027929541 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.4027929541
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1261603298
Short name T63
Test name
Test status
Simulation time 354118160 ps
CPU time 0.64 seconds
Started Jul 17 07:04:34 PM PDT 24
Finished Jul 17 07:04:37 PM PDT 24
Peak memory 193104 kb
Host smart-d06cda8d-2617-4942-8ce3-1e2b29c02d5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261603298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.1261603298
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.290198922
Short name T404
Test name
Test status
Simulation time 304912025 ps
CPU time 0.95 seconds
Started Jul 17 07:04:36 PM PDT 24
Finished Jul 17 07:04:39 PM PDT 24
Peak memory 183820 kb
Host smart-ed768dcb-e756-4282-9498-a12b7fdb9704
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290198922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.290198922
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.863141267
Short name T355
Test name
Test status
Simulation time 1154322976 ps
CPU time 3.98 seconds
Started Jul 17 07:04:35 PM PDT 24
Finished Jul 17 07:04:42 PM PDT 24
Peak memory 193784 kb
Host smart-06d98c7c-8d0e-413e-b43b-1838d9f56eee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863141267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_
timer_same_csr_outstanding.863141267
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1714152609
Short name T390
Test name
Test status
Simulation time 480013094 ps
CPU time 2.02 seconds
Started Jul 17 07:04:35 PM PDT 24
Finished Jul 17 07:04:39 PM PDT 24
Peak memory 198688 kb
Host smart-5cae88a1-88e7-4f93-84ed-5496179da77e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714152609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1714152609
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1146606456
Short name T36
Test name
Test status
Simulation time 4524245319 ps
CPU time 8.19 seconds
Started Jul 17 07:04:34 PM PDT 24
Finished Jul 17 07:04:46 PM PDT 24
Peak memory 197904 kb
Host smart-ae3668cc-dd87-4422-8b8e-d62dd7917ed1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146606456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.1146606456
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.3753411241
Short name T217
Test name
Test status
Simulation time 61168607196 ps
CPU time 7.35 seconds
Started Jul 17 07:03:18 PM PDT 24
Finished Jul 17 07:03:30 PM PDT 24
Peak memory 191916 kb
Host smart-9bda8ff1-f9c5-46c5-89ed-f061e8f601e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753411241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3753411241
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.983496694
Short name T246
Test name
Test status
Simulation time 518398506 ps
CPU time 0.99 seconds
Started Jul 17 07:03:14 PM PDT 24
Finished Jul 17 07:03:18 PM PDT 24
Peak memory 191912 kb
Host smart-cdbcde41-0db5-4781-8b84-2ce8461e1006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983496694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.983496694
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1632049845
Short name T174
Test name
Test status
Simulation time 549473000 ps
CPU time 1.29 seconds
Started Jul 17 07:03:17 PM PDT 24
Finished Jul 17 07:03:23 PM PDT 24
Peak memory 196704 kb
Host smart-3ddba872-e1a3-48c1-9645-3869c64704f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632049845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1632049845
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.733886778
Short name T209
Test name
Test status
Simulation time 41265758807 ps
CPU time 26.42 seconds
Started Jul 17 07:03:23 PM PDT 24
Finished Jul 17 07:03:53 PM PDT 24
Peak memory 191984 kb
Host smart-3a8e3069-94a1-4979-88aa-05b615e34ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733886778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.733886778
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.48518274
Short name T16
Test name
Test status
Simulation time 4160496696 ps
CPU time 2.18 seconds
Started Jul 17 07:03:17 PM PDT 24
Finished Jul 17 07:03:25 PM PDT 24
Peak memory 215448 kb
Host smart-11d855ea-4d6b-46f0-84e0-bdffa3a28bf6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48518274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.48518274
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.1790335419
Short name T212
Test name
Test status
Simulation time 495694578 ps
CPU time 1.34 seconds
Started Jul 17 07:03:17 PM PDT 24
Finished Jul 17 07:03:24 PM PDT 24
Peak memory 191740 kb
Host smart-7f68f1da-6a31-428a-9e76-e8cefdd772bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790335419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1790335419
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.1126785419
Short name T202
Test name
Test status
Simulation time 54802934360 ps
CPU time 77.48 seconds
Started Jul 17 07:03:37 PM PDT 24
Finished Jul 17 07:04:59 PM PDT 24
Peak memory 196984 kb
Host smart-40c12fe0-dde5-40d5-ad91-7259fdfdd5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126785419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.1126785419
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.2188325597
Short name T258
Test name
Test status
Simulation time 465415591 ps
CPU time 0.76 seconds
Started Jul 17 07:03:32 PM PDT 24
Finished Jul 17 07:03:34 PM PDT 24
Peak memory 192108 kb
Host smart-9f043667-abb6-4322-b772-4e8e4f455c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188325597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.2188325597
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.4215228349
Short name T247
Test name
Test status
Simulation time 56203295475 ps
CPU time 13.11 seconds
Started Jul 17 07:03:32 PM PDT 24
Finished Jul 17 07:03:47 PM PDT 24
Peak memory 191884 kb
Host smart-7267ef01-e793-4a1e-93cc-1c0f30699f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215228349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.4215228349
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.924780910
Short name T259
Test name
Test status
Simulation time 566402158 ps
CPU time 0.77 seconds
Started Jul 17 07:03:34 PM PDT 24
Finished Jul 17 07:03:37 PM PDT 24
Peak memory 191988 kb
Host smart-c8762c3b-d4ce-4aa8-ad3a-ceacf47697a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924780910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.924780910
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.3905951739
Short name T229
Test name
Test status
Simulation time 18977712125 ps
CPU time 7.32 seconds
Started Jul 17 07:03:40 PM PDT 24
Finished Jul 17 07:03:52 PM PDT 24
Peak memory 191828 kb
Host smart-7953aa8d-c2d0-4a6c-a629-19d8862e8f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905951739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.3905951739
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.1963256954
Short name T219
Test name
Test status
Simulation time 463743822 ps
CPU time 1.21 seconds
Started Jul 17 07:03:37 PM PDT 24
Finished Jul 17 07:03:43 PM PDT 24
Peak memory 191912 kb
Host smart-06e154da-9ee9-4909-92d6-f9ab884b347e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963256954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.1963256954
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3589360388
Short name T264
Test name
Test status
Simulation time 533434888 ps
CPU time 1.27 seconds
Started Jul 17 07:03:40 PM PDT 24
Finished Jul 17 07:03:46 PM PDT 24
Peak memory 196624 kb
Host smart-a0098af1-684a-4f59-9836-0d56455cb361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589360388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3589360388
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.4156788378
Short name T233
Test name
Test status
Simulation time 389787408 ps
CPU time 0.79 seconds
Started Jul 17 07:03:40 PM PDT 24
Finished Jul 17 07:03:45 PM PDT 24
Peak memory 191924 kb
Host smart-94075bf1-9ba7-48db-a6d1-d0ece50555d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156788378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.4156788378
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3431977804
Short name T188
Test name
Test status
Simulation time 552190027 ps
CPU time 0.76 seconds
Started Jul 17 07:03:37 PM PDT 24
Finished Jul 17 07:03:43 PM PDT 24
Peak memory 196708 kb
Host smart-6bc241d5-d20b-4672-8da7-2c32c63f9199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431977804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3431977804
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.2705681583
Short name T270
Test name
Test status
Simulation time 22843584194 ps
CPU time 32.87 seconds
Started Jul 17 07:03:37 PM PDT 24
Finished Jul 17 07:04:15 PM PDT 24
Peak memory 196960 kb
Host smart-0f077700-57f6-4865-b134-7744f925554f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705681583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.2705681583
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2542719413
Short name T218
Test name
Test status
Simulation time 394395848 ps
CPU time 1.1 seconds
Started Jul 17 07:03:37 PM PDT 24
Finished Jul 17 07:03:43 PM PDT 24
Peak memory 196724 kb
Host smart-7031fe2d-6c19-4ec2-aa7a-4418d1e57fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542719413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2542719413
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1048995315
Short name T230
Test name
Test status
Simulation time 27951900154 ps
CPU time 44.05 seconds
Started Jul 17 07:03:36 PM PDT 24
Finished Jul 17 07:04:25 PM PDT 24
Peak memory 196972 kb
Host smart-475fe478-b1c7-4577-a1fe-a0dd1e1feed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048995315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1048995315
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.3321224329
Short name T208
Test name
Test status
Simulation time 439216557 ps
CPU time 1.24 seconds
Started Jul 17 07:03:37 PM PDT 24
Finished Jul 17 07:03:42 PM PDT 24
Peak memory 196748 kb
Host smart-e93fa629-97bf-446c-b87b-b8d50fcea40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321224329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3321224329
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.2175228683
Short name T245
Test name
Test status
Simulation time 20303825084 ps
CPU time 7.49 seconds
Started Jul 17 07:03:37 PM PDT 24
Finished Jul 17 07:03:49 PM PDT 24
Peak memory 191988 kb
Host smart-1262409e-bcde-4c98-b45a-6d21373cdaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175228683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.2175228683
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2292132701
Short name T225
Test name
Test status
Simulation time 475323026 ps
CPU time 0.67 seconds
Started Jul 17 07:03:40 PM PDT 24
Finished Jul 17 07:03:45 PM PDT 24
Peak memory 196752 kb
Host smart-bb4cdfae-d064-4a80-9b53-69aea002848c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292132701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2292132701
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1429254560
Short name T206
Test name
Test status
Simulation time 3541281326 ps
CPU time 1.74 seconds
Started Jul 17 07:03:39 PM PDT 24
Finished Jul 17 07:03:45 PM PDT 24
Peak memory 191996 kb
Host smart-d6a31d23-b92f-4dc0-b7bb-5bc2d309d4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429254560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1429254560
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.3069033778
Short name T213
Test name
Test status
Simulation time 566558741 ps
CPU time 0.94 seconds
Started Jul 17 07:03:37 PM PDT 24
Finished Jul 17 07:03:43 PM PDT 24
Peak memory 196736 kb
Host smart-ed5b9c9b-ff3e-48bb-944e-f366f2b0462a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069033778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3069033778
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.3682623446
Short name T252
Test name
Test status
Simulation time 8327645094 ps
CPU time 1.44 seconds
Started Jul 17 07:03:36 PM PDT 24
Finished Jul 17 07:03:41 PM PDT 24
Peak memory 191976 kb
Host smart-7838eedc-c9f0-449b-b268-9d1a30764146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682623446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.3682623446
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.3875894795
Short name T226
Test name
Test status
Simulation time 409940078 ps
CPU time 0.72 seconds
Started Jul 17 07:03:34 PM PDT 24
Finished Jul 17 07:03:36 PM PDT 24
Peak memory 191860 kb
Host smart-3a395def-d4fc-464a-9a9e-2afb36408392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875894795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3875894795
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1180181043
Short name T203
Test name
Test status
Simulation time 27804237960 ps
CPU time 11.52 seconds
Started Jul 17 07:03:37 PM PDT 24
Finished Jul 17 07:03:54 PM PDT 24
Peak memory 191912 kb
Host smart-f457d1b2-2295-4f99-915a-29914fb945fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180181043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1180181043
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.2577336680
Short name T210
Test name
Test status
Simulation time 398816637 ps
CPU time 1.11 seconds
Started Jul 17 07:03:39 PM PDT 24
Finished Jul 17 07:03:44 PM PDT 24
Peak memory 191920 kb
Host smart-3c72f2d0-912c-4703-ad9e-5487f3fdf13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577336680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2577336680
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1828765675
Short name T9
Test name
Test status
Simulation time 556104244 ps
CPU time 0.77 seconds
Started Jul 17 07:03:33 PM PDT 24
Finished Jul 17 07:03:35 PM PDT 24
Peak memory 196788 kb
Host smart-93bd8ff5-ec1a-444a-b45a-6ba9c17acfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828765675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1828765675
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.3281661469
Short name T222
Test name
Test status
Simulation time 29135009348 ps
CPU time 21.08 seconds
Started Jul 17 07:03:32 PM PDT 24
Finished Jul 17 07:03:53 PM PDT 24
Peak memory 196988 kb
Host smart-5e33a879-0b84-494e-804f-72309f76dfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281661469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.3281661469
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.354473523
Short name T17
Test name
Test status
Simulation time 7764820673 ps
CPU time 10.45 seconds
Started Jul 17 07:03:40 PM PDT 24
Finished Jul 17 07:03:55 PM PDT 24
Peak memory 215524 kb
Host smart-54e5c153-729d-4f05-8053-e6e007768916
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354473523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.354473523
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.2774906131
Short name T265
Test name
Test status
Simulation time 585601477 ps
CPU time 0.94 seconds
Started Jul 17 07:03:21 PM PDT 24
Finished Jul 17 07:03:27 PM PDT 24
Peak memory 191908 kb
Host smart-c4fe5bb3-c950-46ea-99ae-4b71e8e30be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774906131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2774906131
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1235924166
Short name T175
Test name
Test status
Simulation time 392379170 ps
CPU time 0.76 seconds
Started Jul 17 07:03:37 PM PDT 24
Finished Jul 17 07:03:42 PM PDT 24
Peak memory 196688 kb
Host smart-8a2d77a7-fc56-46ce-9479-0e6973a7db83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235924166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1235924166
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.702092737
Short name T244
Test name
Test status
Simulation time 17375863014 ps
CPU time 25.99 seconds
Started Jul 17 07:03:38 PM PDT 24
Finished Jul 17 07:04:09 PM PDT 24
Peak memory 196908 kb
Host smart-993d8be6-cf0b-457e-ae18-877fab52f2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702092737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.702092737
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.567109819
Short name T29
Test name
Test status
Simulation time 647830861 ps
CPU time 0.68 seconds
Started Jul 17 07:03:38 PM PDT 24
Finished Jul 17 07:03:43 PM PDT 24
Peak memory 191828 kb
Host smart-53fd1db9-7b91-4e40-9f0d-9e95d692a99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567109819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.567109819
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_jump.798027144
Short name T189
Test name
Test status
Simulation time 477427726 ps
CPU time 1.4 seconds
Started Jul 17 07:03:45 PM PDT 24
Finished Jul 17 07:03:48 PM PDT 24
Peak memory 196676 kb
Host smart-b659c899-8662-4045-9c4a-1b64bcb85928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798027144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.798027144
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.624318343
Short name T232
Test name
Test status
Simulation time 25493123858 ps
CPU time 10.26 seconds
Started Jul 17 07:03:38 PM PDT 24
Finished Jul 17 07:03:53 PM PDT 24
Peak memory 191904 kb
Host smart-90ded2af-d059-4aca-9a11-e16b23fbfd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624318343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.624318343
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.607241607
Short name T279
Test name
Test status
Simulation time 537827718 ps
CPU time 0.78 seconds
Started Jul 17 07:03:35 PM PDT 24
Finished Jul 17 07:03:39 PM PDT 24
Peak memory 191872 kb
Host smart-72f7ba3e-a997-41c9-881a-a9b65682e3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607241607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.607241607
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.731898369
Short name T199
Test name
Test status
Simulation time 35438138803 ps
CPU time 26 seconds
Started Jul 17 07:03:45 PM PDT 24
Finished Jul 17 07:04:12 PM PDT 24
Peak memory 191976 kb
Host smart-a49522aa-35df-49aa-8d79-126b696158f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731898369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.731898369
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.2789769543
Short name T205
Test name
Test status
Simulation time 569014493 ps
CPU time 0.77 seconds
Started Jul 17 07:03:45 PM PDT 24
Finished Jul 17 07:03:47 PM PDT 24
Peak memory 191904 kb
Host smart-f0da3deb-b9e6-4563-966f-7f66714d3990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789769543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.2789769543
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.350818217
Short name T228
Test name
Test status
Simulation time 33230313941 ps
CPU time 13.21 seconds
Started Jul 17 07:03:37 PM PDT 24
Finished Jul 17 07:03:54 PM PDT 24
Peak memory 192000 kb
Host smart-ed42705d-7b53-4a88-93da-1c5edcfa4f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350818217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.350818217
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.3830669633
Short name T260
Test name
Test status
Simulation time 595932912 ps
CPU time 0.83 seconds
Started Jul 17 07:03:45 PM PDT 24
Finished Jul 17 07:03:47 PM PDT 24
Peak memory 191904 kb
Host smart-efe75fd2-2ce2-4c59-ba84-d3c7194f7890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830669633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.3830669633
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.481703957
Short name T273
Test name
Test status
Simulation time 20399236172 ps
CPU time 27.69 seconds
Started Jul 17 07:03:54 PM PDT 24
Finished Jul 17 07:04:23 PM PDT 24
Peak memory 191924 kb
Host smart-731d31bd-345e-472a-a415-a185e9995411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481703957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.481703957
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.225306551
Short name T269
Test name
Test status
Simulation time 560864036 ps
CPU time 0.63 seconds
Started Jul 17 07:03:58 PM PDT 24
Finished Jul 17 07:04:01 PM PDT 24
Peak memory 196760 kb
Host smart-14b178c2-fd38-496f-9e88-132ca32ae4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225306551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.225306551
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.521054288
Short name T2
Test name
Test status
Simulation time 4430951985 ps
CPU time 6.37 seconds
Started Jul 17 07:03:58 PM PDT 24
Finished Jul 17 07:04:07 PM PDT 24
Peak memory 196972 kb
Host smart-e19cf6b2-93d3-4a50-b226-5bc7a447c2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521054288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.521054288
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3506332237
Short name T196
Test name
Test status
Simulation time 600902574 ps
CPU time 1.33 seconds
Started Jul 17 07:03:59 PM PDT 24
Finished Jul 17 07:04:03 PM PDT 24
Peak memory 191920 kb
Host smart-3817c0a4-e484-48d1-9d5d-3b5c2dbe03f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506332237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3506332237
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2367982688
Short name T250
Test name
Test status
Simulation time 22364594300 ps
CPU time 9.71 seconds
Started Jul 17 07:03:56 PM PDT 24
Finished Jul 17 07:04:08 PM PDT 24
Peak memory 191980 kb
Host smart-f868941c-afca-457f-b1ed-7b949deee4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367982688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2367982688
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.95306056
Short name T223
Test name
Test status
Simulation time 372548195 ps
CPU time 1.14 seconds
Started Jul 17 07:03:57 PM PDT 24
Finished Jul 17 07:04:01 PM PDT 24
Peak memory 196748 kb
Host smart-4c3cf55d-371d-48b1-9eff-8e6fba2cc6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95306056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.95306056
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2982474582
Short name T164
Test name
Test status
Simulation time 571092178 ps
CPU time 1.47 seconds
Started Jul 17 07:03:59 PM PDT 24
Finished Jul 17 07:04:03 PM PDT 24
Peak memory 196780 kb
Host smart-80e89a0e-8cc9-4497-a786-271df27eb2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982474582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2982474582
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.1894936558
Short name T234
Test name
Test status
Simulation time 38692925951 ps
CPU time 54.22 seconds
Started Jul 17 07:03:55 PM PDT 24
Finished Jul 17 07:04:52 PM PDT 24
Peak memory 196972 kb
Host smart-8b33fa1e-5153-4302-9dcd-d07acbc6ae75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894936558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1894936558
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.3481944634
Short name T214
Test name
Test status
Simulation time 477816918 ps
CPU time 0.76 seconds
Started Jul 17 07:03:58 PM PDT 24
Finished Jul 17 07:04:01 PM PDT 24
Peak memory 191924 kb
Host smart-952ee61a-0305-4038-9c35-58c9b7ea93ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481944634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3481944634
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.131711063
Short name T236
Test name
Test status
Simulation time 11399691207 ps
CPU time 8.56 seconds
Started Jul 17 07:03:55 PM PDT 24
Finished Jul 17 07:04:06 PM PDT 24
Peak memory 192160 kb
Host smart-93cbeddd-744d-41cf-a74a-6962b9ea0768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131711063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.131711063
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.2522292679
Short name T266
Test name
Test status
Simulation time 437431791 ps
CPU time 0.72 seconds
Started Jul 17 07:04:01 PM PDT 24
Finished Jul 17 07:04:05 PM PDT 24
Peak memory 191920 kb
Host smart-a2530a33-48aa-4c95-aefe-d6a8b6f9c44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522292679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2522292679
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2343259528
Short name T204
Test name
Test status
Simulation time 26434871166 ps
CPU time 7.4 seconds
Started Jul 17 07:03:55 PM PDT 24
Finished Jul 17 07:04:04 PM PDT 24
Peak memory 191988 kb
Host smart-b70f09b6-a88b-4dc3-a807-dd7105fc7ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343259528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2343259528
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.441241581
Short name T261
Test name
Test status
Simulation time 615325125 ps
CPU time 1.45 seconds
Started Jul 17 07:03:55 PM PDT 24
Finished Jul 17 07:03:58 PM PDT 24
Peak memory 196676 kb
Host smart-efcf225d-7c86-4c8b-87b8-e3a346a3477a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441241581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.441241581
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.3260841175
Short name T26
Test name
Test status
Simulation time 55455046486 ps
CPU time 72.94 seconds
Started Jul 17 07:03:35 PM PDT 24
Finished Jul 17 07:04:51 PM PDT 24
Peak memory 191976 kb
Host smart-e7ce48d4-df65-4a83-9757-e8b86fc0a642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260841175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3260841175
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.825274235
Short name T18
Test name
Test status
Simulation time 4672748262 ps
CPU time 2.72 seconds
Started Jul 17 07:03:33 PM PDT 24
Finished Jul 17 07:03:37 PM PDT 24
Peak memory 215776 kb
Host smart-ae021c75-55c4-46b4-a063-120e7345a73a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825274235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.825274235
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2894499856
Short name T198
Test name
Test status
Simulation time 471895850 ps
CPU time 1.16 seconds
Started Jul 17 07:03:34 PM PDT 24
Finished Jul 17 07:03:36 PM PDT 24
Peak memory 191916 kb
Host smart-00ba514d-a99c-4e8b-b527-96e5ce2bb84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894499856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2894499856
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.3680258502
Short name T249
Test name
Test status
Simulation time 21052745671 ps
CPU time 5.44 seconds
Started Jul 17 07:03:56 PM PDT 24
Finished Jul 17 07:04:05 PM PDT 24
Peak memory 191980 kb
Host smart-76491d41-f565-4cb7-82d1-2db239bbbdca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680258502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.3680258502
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.28294574
Short name T4
Test name
Test status
Simulation time 405039912 ps
CPU time 0.74 seconds
Started Jul 17 07:03:59 PM PDT 24
Finished Jul 17 07:04:02 PM PDT 24
Peak memory 191720 kb
Host smart-74f479d8-f357-4e08-86fb-9a9f010b9e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28294574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.28294574
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.1806898214
Short name T154
Test name
Test status
Simulation time 269590141139 ps
CPU time 134.49 seconds
Started Jul 17 07:03:56 PM PDT 24
Finished Jul 17 07:06:12 PM PDT 24
Peak memory 207904 kb
Host smart-96483ed2-15e9-4c88-a597-cb0e3d872744
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806898214 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.1806898214
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1253560008
Short name T10
Test name
Test status
Simulation time 385912852 ps
CPU time 0.71 seconds
Started Jul 17 07:03:55 PM PDT 24
Finished Jul 17 07:03:57 PM PDT 24
Peak memory 196676 kb
Host smart-a25abe60-905d-463e-b307-a563bbf367e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253560008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1253560008
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.2918404432
Short name T215
Test name
Test status
Simulation time 30511591768 ps
CPU time 10.26 seconds
Started Jul 17 07:03:56 PM PDT 24
Finished Jul 17 07:04:08 PM PDT 24
Peak memory 191912 kb
Host smart-b3146c66-9d89-43d6-9b6b-01bd9db6e8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918404432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.2918404432
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.1116100373
Short name T278
Test name
Test status
Simulation time 503856800 ps
CPU time 1.22 seconds
Started Jul 17 07:03:55 PM PDT 24
Finished Jul 17 07:03:58 PM PDT 24
Peak memory 196856 kb
Host smart-17bfd03c-a001-41d3-bd92-8d10367d2e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116100373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.1116100373
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.4140776261
Short name T197
Test name
Test status
Simulation time 5490984850 ps
CPU time 2.52 seconds
Started Jul 17 07:04:02 PM PDT 24
Finished Jul 17 07:04:09 PM PDT 24
Peak memory 196948 kb
Host smart-9236957b-d2ab-442d-b101-61a4fe579ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140776261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.4140776261
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3018113953
Short name T51
Test name
Test status
Simulation time 461570497 ps
CPU time 0.72 seconds
Started Jul 17 07:04:01 PM PDT 24
Finished Jul 17 07:04:05 PM PDT 24
Peak memory 196740 kb
Host smart-e4a26b39-144b-471a-89b9-06fdb4f94c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018113953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3018113953
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1167207182
Short name T262
Test name
Test status
Simulation time 11304534195 ps
CPU time 4.97 seconds
Started Jul 17 07:03:56 PM PDT 24
Finished Jul 17 07:04:03 PM PDT 24
Peak memory 196980 kb
Host smart-2f1dd122-20db-4778-a76d-8e22d3e9b1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167207182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1167207182
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2627728922
Short name T280
Test name
Test status
Simulation time 388121254 ps
CPU time 0.71 seconds
Started Jul 17 07:04:00 PM PDT 24
Finished Jul 17 07:04:03 PM PDT 24
Peak memory 191920 kb
Host smart-c3ab8f10-a499-4f87-b35b-0e5bd5909ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627728922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2627728922
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.276019656
Short name T12
Test name
Test status
Simulation time 15482897965 ps
CPU time 20.5 seconds
Started Jul 17 07:03:55 PM PDT 24
Finished Jul 17 07:04:17 PM PDT 24
Peak memory 191992 kb
Host smart-3c2f416e-9d02-4234-9f7e-4afe8925f1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276019656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.276019656
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.1279807027
Short name T254
Test name
Test status
Simulation time 446727055 ps
CPU time 0.71 seconds
Started Jul 17 07:03:57 PM PDT 24
Finished Jul 17 07:04:00 PM PDT 24
Peak memory 191872 kb
Host smart-ce72bed9-29af-4c31-ad39-01da00b23185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279807027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1279807027
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.2863201986
Short name T221
Test name
Test status
Simulation time 23529352738 ps
CPU time 33.23 seconds
Started Jul 17 07:04:08 PM PDT 24
Finished Jul 17 07:04:44 PM PDT 24
Peak memory 191968 kb
Host smart-9e08d4d8-074e-4aef-9e4e-fd6181192dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863201986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.2863201986
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.3900449340
Short name T207
Test name
Test status
Simulation time 473214022 ps
CPU time 1.23 seconds
Started Jul 17 07:04:01 PM PDT 24
Finished Jul 17 07:04:05 PM PDT 24
Peak memory 196720 kb
Host smart-d6399cc3-762d-45dc-b033-c6d90ba37af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900449340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3900449340
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1724270346
Short name T76
Test name
Test status
Simulation time 36128242665 ps
CPU time 45.66 seconds
Started Jul 17 07:04:01 PM PDT 24
Finished Jul 17 07:04:49 PM PDT 24
Peak memory 191912 kb
Host smart-4e621149-6dd4-4d26-b040-a3b284f23bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724270346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1724270346
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1357891033
Short name T224
Test name
Test status
Simulation time 579111693 ps
CPU time 0.78 seconds
Started Jul 17 07:04:09 PM PDT 24
Finished Jul 17 07:04:13 PM PDT 24
Peak memory 196720 kb
Host smart-68133324-2ede-4610-8594-6aa7b8074607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357891033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1357891033
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.4200344413
Short name T272
Test name
Test status
Simulation time 22926881099 ps
CPU time 15.44 seconds
Started Jul 17 07:04:00 PM PDT 24
Finished Jul 17 07:04:18 PM PDT 24
Peak memory 196916 kb
Host smart-d7bf0e38-4244-4b95-959c-5b98826d997d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200344413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.4200344413
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.832024402
Short name T268
Test name
Test status
Simulation time 501112559 ps
CPU time 0.61 seconds
Started Jul 17 07:04:04 PM PDT 24
Finished Jul 17 07:04:08 PM PDT 24
Peak memory 191920 kb
Host smart-8dcffcc4-1dce-4175-9275-de70131c4537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832024402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.832024402
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2773817271
Short name T253
Test name
Test status
Simulation time 15393320226 ps
CPU time 21.71 seconds
Started Jul 17 07:04:04 PM PDT 24
Finished Jul 17 07:04:29 PM PDT 24
Peak memory 196984 kb
Host smart-3a7a170f-2864-4711-a238-89c738d2602e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773817271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2773817271
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3240227413
Short name T263
Test name
Test status
Simulation time 522134957 ps
CPU time 0.64 seconds
Started Jul 17 07:04:03 PM PDT 24
Finished Jul 17 07:04:07 PM PDT 24
Peak memory 191920 kb
Host smart-4078ca8a-04e5-4ab0-a6ec-a9138d2f7426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240227413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3240227413
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.2426671696
Short name T220
Test name
Test status
Simulation time 33311797797 ps
CPU time 11.11 seconds
Started Jul 17 07:04:09 PM PDT 24
Finished Jul 17 07:04:23 PM PDT 24
Peak memory 196956 kb
Host smart-ff6e00a5-d1b1-4c05-9418-4b9468e4a79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426671696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2426671696
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.1265099440
Short name T274
Test name
Test status
Simulation time 397657306 ps
CPU time 0.71 seconds
Started Jul 17 07:04:06 PM PDT 24
Finished Jul 17 07:04:10 PM PDT 24
Peak memory 191924 kb
Host smart-16cc24aa-83ba-4aef-b3f0-0d23b88f3642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265099440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1265099440
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.2908064322
Short name T255
Test name
Test status
Simulation time 23043749464 ps
CPU time 8.3 seconds
Started Jul 17 07:03:40 PM PDT 24
Finished Jul 17 07:03:53 PM PDT 24
Peak memory 191964 kb
Host smart-ed4bdee9-123c-4b5d-a16a-271578cd9967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908064322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.2908064322
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.1163336870
Short name T15
Test name
Test status
Simulation time 7760690000 ps
CPU time 6.83 seconds
Started Jul 17 07:03:32 PM PDT 24
Finished Jul 17 07:03:39 PM PDT 24
Peak memory 215796 kb
Host smart-6f77bd15-c029-4da0-92db-cea183b98a03
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163336870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.1163336870
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3655305155
Short name T237
Test name
Test status
Simulation time 431273676 ps
CPU time 1.2 seconds
Started Jul 17 07:03:36 PM PDT 24
Finished Jul 17 07:03:42 PM PDT 24
Peak memory 191900 kb
Host smart-aefee117-b991-4382-95e5-d23c818af344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655305155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3655305155
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.2706496937
Short name T235
Test name
Test status
Simulation time 33646800449 ps
CPU time 43.93 seconds
Started Jul 17 07:04:08 PM PDT 24
Finished Jul 17 07:04:55 PM PDT 24
Peak memory 191980 kb
Host smart-445cc7b1-cd32-426d-b8d6-deb29d1a4ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706496937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2706496937
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.2557540868
Short name T281
Test name
Test status
Simulation time 579218011 ps
CPU time 0.92 seconds
Started Jul 17 07:04:07 PM PDT 24
Finished Jul 17 07:04:11 PM PDT 24
Peak memory 196780 kb
Host smart-cdf6d91b-da69-4404-a390-60d9e6edd08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557540868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2557540868
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.2851117119
Short name T79
Test name
Test status
Simulation time 405676078620 ps
CPU time 600 seconds
Started Jul 17 07:04:07 PM PDT 24
Finished Jul 17 07:14:10 PM PDT 24
Peak memory 198324 kb
Host smart-1bb85f21-448b-45e9-84bf-a863c152f385
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851117119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.2851117119
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.1956916211
Short name T200
Test name
Test status
Simulation time 27505881151 ps
CPU time 9.88 seconds
Started Jul 17 07:04:07 PM PDT 24
Finished Jul 17 07:04:21 PM PDT 24
Peak memory 191980 kb
Host smart-b058caac-9f99-46af-ae7b-1966a5c568c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956916211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.1956916211
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2097497146
Short name T239
Test name
Test status
Simulation time 591602677 ps
CPU time 0.9 seconds
Started Jul 17 07:03:58 PM PDT 24
Finished Jul 17 07:04:02 PM PDT 24
Peak memory 191828 kb
Host smart-ee85b284-00e4-4e71-be05-b2fe962b4a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097497146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2097497146
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.2855050751
Short name T216
Test name
Test status
Simulation time 8045436334 ps
CPU time 12.27 seconds
Started Jul 17 07:04:01 PM PDT 24
Finished Jul 17 07:04:15 PM PDT 24
Peak memory 196984 kb
Host smart-d6f65925-be72-44aa-a64d-11b0ddd83885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855050751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.2855050751
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.1031244089
Short name T24
Test name
Test status
Simulation time 439256953 ps
CPU time 0.85 seconds
Started Jul 17 07:03:58 PM PDT 24
Finished Jul 17 07:04:01 PM PDT 24
Peak memory 196604 kb
Host smart-8faac066-413e-4290-9c3a-96bc37a3ac9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031244089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1031244089
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.416712760
Short name T6
Test name
Test status
Simulation time 51954982575 ps
CPU time 20.07 seconds
Started Jul 17 07:04:02 PM PDT 24
Finished Jul 17 07:04:25 PM PDT 24
Peak memory 196972 kb
Host smart-fcd09a9e-d1bd-47c1-b7c2-75f031c48f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416712760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.416712760
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.828461484
Short name T276
Test name
Test status
Simulation time 360354414 ps
CPU time 0.7 seconds
Started Jul 17 07:03:56 PM PDT 24
Finished Jul 17 07:03:59 PM PDT 24
Peak memory 191992 kb
Host smart-292d8657-0219-4354-8f41-4881fbd4576a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828461484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.828461484
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.2196019023
Short name T243
Test name
Test status
Simulation time 23771984674 ps
CPU time 37.14 seconds
Started Jul 17 07:04:01 PM PDT 24
Finished Jul 17 07:04:40 PM PDT 24
Peak memory 191976 kb
Host smart-a5322ff3-9b4d-41dc-9ebb-a65bc98764f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196019023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.2196019023
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2570199142
Short name T282
Test name
Test status
Simulation time 532358712 ps
CPU time 1.38 seconds
Started Jul 17 07:04:02 PM PDT 24
Finished Jul 17 07:04:07 PM PDT 24
Peak memory 196680 kb
Host smart-c4771775-ba81-44d4-8d72-02cb47283666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570199142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2570199142
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.3410387864
Short name T277
Test name
Test status
Simulation time 12232842549 ps
CPU time 18.97 seconds
Started Jul 17 07:04:02 PM PDT 24
Finished Jul 17 07:04:24 PM PDT 24
Peak memory 196972 kb
Host smart-089cdd2c-35e1-47d4-8ee6-5f19cf49d915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410387864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3410387864
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.3237109593
Short name T242
Test name
Test status
Simulation time 466820849 ps
CPU time 1.26 seconds
Started Jul 17 07:04:06 PM PDT 24
Finished Jul 17 07:04:10 PM PDT 24
Peak memory 191920 kb
Host smart-c9011bfa-0f45-438d-9f88-63c4b16a0d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237109593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3237109593
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.663935810
Short name T77
Test name
Test status
Simulation time 23647122471 ps
CPU time 33.86 seconds
Started Jul 17 07:04:06 PM PDT 24
Finished Jul 17 07:04:44 PM PDT 24
Peak memory 191992 kb
Host smart-087600bb-a725-43ce-9994-6dc9005b52cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663935810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.663935810
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.3445137522
Short name T241
Test name
Test status
Simulation time 405096336 ps
CPU time 0.73 seconds
Started Jul 17 07:04:01 PM PDT 24
Finished Jul 17 07:04:05 PM PDT 24
Peak memory 191912 kb
Host smart-80bab542-2234-4585-9800-46c79771a63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445137522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.3445137522
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.163110877
Short name T251
Test name
Test status
Simulation time 18285376058 ps
CPU time 30.1 seconds
Started Jul 17 07:04:05 PM PDT 24
Finished Jul 17 07:04:38 PM PDT 24
Peak memory 191996 kb
Host smart-2fa5e9f7-31ff-4355-a474-1f89235a3666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163110877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.163110877
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.3313016983
Short name T238
Test name
Test status
Simulation time 555709283 ps
CPU time 0.99 seconds
Started Jul 17 07:04:01 PM PDT 24
Finished Jul 17 07:04:05 PM PDT 24
Peak memory 196696 kb
Host smart-6e170cef-daed-41d5-8ee9-97909a499d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313016983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3313016983
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.2404881481
Short name T271
Test name
Test status
Simulation time 46642924736 ps
CPU time 32.82 seconds
Started Jul 17 07:04:06 PM PDT 24
Finished Jul 17 07:04:42 PM PDT 24
Peak memory 196888 kb
Host smart-cc508a19-1b51-411b-b880-85963eca091c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404881481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2404881481
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.3448675621
Short name T267
Test name
Test status
Simulation time 445033215 ps
CPU time 1.14 seconds
Started Jul 17 07:04:05 PM PDT 24
Finished Jul 17 07:04:09 PM PDT 24
Peak memory 196776 kb
Host smart-9b03d578-8ed0-4ba8-9e08-eb8dd613b259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448675621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.3448675621
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1816333572
Short name T5
Test name
Test status
Simulation time 7167427641 ps
CPU time 3.51 seconds
Started Jul 17 07:04:09 PM PDT 24
Finished Jul 17 07:04:16 PM PDT 24
Peak memory 191772 kb
Host smart-02e97fe0-afba-4c65-9218-6f93331472ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816333572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1816333572
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.2879854465
Short name T257
Test name
Test status
Simulation time 553178638 ps
CPU time 1.39 seconds
Started Jul 17 07:04:09 PM PDT 24
Finished Jul 17 07:04:14 PM PDT 24
Peak memory 196584 kb
Host smart-fbed4533-cb82-422f-8f64-ad6e0da070ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879854465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.2879854465
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1336093141
Short name T22
Test name
Test status
Simulation time 22003742074 ps
CPU time 128.58 seconds
Started Jul 17 07:04:11 PM PDT 24
Finished Jul 17 07:06:22 PM PDT 24
Peak memory 206836 kb
Host smart-255c9a25-356f-45a6-8faa-dcac11fdc096
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336093141 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1336093141
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.3096345833
Short name T75
Test name
Test status
Simulation time 30022132366 ps
CPU time 11.85 seconds
Started Jul 17 07:03:37 PM PDT 24
Finished Jul 17 07:03:53 PM PDT 24
Peak memory 192064 kb
Host smart-576487b3-f6ed-45a1-8d67-ed183e628588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096345833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.3096345833
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.1274088751
Short name T275
Test name
Test status
Simulation time 408926483 ps
CPU time 1.17 seconds
Started Jul 17 07:03:34 PM PDT 24
Finished Jul 17 07:03:37 PM PDT 24
Peak memory 196768 kb
Host smart-d81a73c8-9edf-4835-8480-450e949bff53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274088751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.1274088751
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.1884050097
Short name T240
Test name
Test status
Simulation time 33404213593 ps
CPU time 26.23 seconds
Started Jul 17 07:03:34 PM PDT 24
Finished Jul 17 07:04:03 PM PDT 24
Peak memory 196980 kb
Host smart-57c141b0-3fa5-482a-9bf6-a05ab48ad103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884050097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1884050097
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.389132446
Short name T227
Test name
Test status
Simulation time 403623530 ps
CPU time 0.71 seconds
Started Jul 17 07:03:32 PM PDT 24
Finished Jul 17 07:03:34 PM PDT 24
Peak memory 191896 kb
Host smart-4e5077fa-63df-4526-a94c-bc7a9862d8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389132446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.389132446
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.643840620
Short name T248
Test name
Test status
Simulation time 33423519282 ps
CPU time 46.06 seconds
Started Jul 17 07:03:34 PM PDT 24
Finished Jul 17 07:04:22 PM PDT 24
Peak memory 191976 kb
Host smart-adbc46ba-5556-4249-b9e4-95e01781b5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643840620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.643840620
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.2860662379
Short name T211
Test name
Test status
Simulation time 590783977 ps
CPU time 0.8 seconds
Started Jul 17 07:03:32 PM PDT 24
Finished Jul 17 07:03:34 PM PDT 24
Peak memory 196708 kb
Host smart-2d3417d8-5cfe-4289-b04c-7a50375b77a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860662379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.2860662379
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_jump.1176034687
Short name T182
Test name
Test status
Simulation time 362216884 ps
CPU time 1.08 seconds
Started Jul 17 07:03:34 PM PDT 24
Finished Jul 17 07:03:38 PM PDT 24
Peak memory 196804 kb
Host smart-828bb737-626e-4805-9e85-1e9f86884dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176034687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1176034687
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.1596335514
Short name T256
Test name
Test status
Simulation time 21228128529 ps
CPU time 29.63 seconds
Started Jul 17 07:03:35 PM PDT 24
Finished Jul 17 07:04:07 PM PDT 24
Peak memory 191980 kb
Host smart-8160621c-ceff-43d3-98af-e7865f29bf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596335514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1596335514
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.487578566
Short name T201
Test name
Test status
Simulation time 442314102 ps
CPU time 1.27 seconds
Started Jul 17 07:03:37 PM PDT 24
Finished Jul 17 07:03:42 PM PDT 24
Peak memory 196704 kb
Host smart-ee299ba7-9b70-4eaf-a522-d9b08e8670b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487578566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.487578566
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.103280314
Short name T231
Test name
Test status
Simulation time 3093363748 ps
CPU time 2.83 seconds
Started Jul 17 07:03:39 PM PDT 24
Finished Jul 17 07:03:46 PM PDT 24
Peak memory 191900 kb
Host smart-9cc09b54-d04f-4d0d-ae98-23a1501f5f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103280314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.103280314
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3619191002
Short name T21
Test name
Test status
Simulation time 568069820 ps
CPU time 0.78 seconds
Started Jul 17 07:03:35 PM PDT 24
Finished Jul 17 07:03:40 PM PDT 24
Peak memory 191796 kb
Host smart-cf54a323-2ec0-40d3-9eca-0ab6c0a1b17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619191002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3619191002
Directory /workspace/9.aon_timer_smoke/latest
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