Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	740887239	5512988	0	0
wdog_bark_thold_rd_A	740887239	82009	0	0
wdog_bite_thold_rd_A	740887239	72732	0	0
wdog_ctrl_rd_A	740887239	71992	0	0
wdog_regwen_rd_A	740887239	84709	0	0
wkup_ctrl_rd_A	740887239	72924	0	0
wkup_thold_hi_rd_A	740887239	83959	0	0
wkup_thold_lo_rd_A	740887239	72459	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740887239	5512988	0	0
T2	109455	19782	0	0
T3	50918	0	0	0
T5	530501	0	0	0
T6	450994	0	0	0
T7	24094	0	0	0
T8	350362	0	0	0
T9	281066	0	0	0
T10	15018	0	0	0
T11	5938	0	0	0
T12	545247	0	0	0
T15	0	28970	0	0
T19	0	113790	0	0
T28	0	320346	0	0
T29	0	99783	0	0
T39	0	57079	0	0
T40	0	180507	0	0
T41	0	132737	0	0
T42	0	227488	0	0
T43	0	14612	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740887239	82009	0	0
T2	109455	1128	0	0
T3	50918	0	0	0
T5	530501	0	0	0
T6	450994	0	0	0
T7	24094	0	0	0
T8	350362	0	0	0
T9	281066	0	0	0
T10	15018	0	0	0
T11	5938	0	0	0
T12	545247	0	0	0
T88	0	4173	0	0
T89	0	3168	0	0
T90	0	1382	0	0
T91	0	3971	0	0
T92	0	19652	0	0
T93	0	11039	0	0
T94	0	19085	0	0
T95	0	6802	0	0
T96	0	4536	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740887239	72732	0	0
T2	109455	922	0	0
T3	50918	0	0	0
T5	530501	0	0	0
T6	450994	0	0	0
T7	24094	0	0	0
T8	350362	0	0	0
T9	281066	0	0	0
T10	15018	0	0	0
T11	5938	0	0	0
T12	545247	0	0	0
T88	0	3843	0	0
T89	0	2949	0	0
T90	0	1209	0	0
T91	0	3540	0	0
T92	0	17024	0	0
T93	0	9735	0	0
T94	0	16624	0	0
T95	0	5842	0	0
T96	0	4364	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740887239	71992	0	0
T2	109455	971	0	0
T3	50918	0	0	0
T5	530501	0	0	0
T6	450994	0	0	0
T7	24094	0	0	0
T8	350362	0	0	0
T9	281066	0	0	0
T10	15018	0	0	0
T11	5938	0	0	0
T12	545247	0	0	0
T88	0	3791	0	0
T89	0	2962	0	0
T90	0	1329	0	0
T91	0	3489	0	0
T92	0	17249	0	0
T93	0	9459	0	0
T94	0	16038	0	0
T95	0	6061	0	0
T96	0	4268	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740887239	84709	0	0
T2	109455	1155	0	0
T3	50918	0	0	0
T5	530501	0	0	0
T6	450994	0	0	0
T7	24094	0	0	0
T8	350362	0	0	0
T9	281066	0	0	0
T10	15018	0	0	0
T11	5938	0	0	0
T12	545247	0	0	0
T88	0	4575	0	0
T89	0	3453	0	0
T90	0	1319	0	0
T91	0	4314	0	0
T92	0	19953	0	0
T93	0	11643	0	0
T94	0	19495	0	0
T95	0	6584	0	0
T96	0	4672	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740887239	72924	0	0
T2	109455	866	0	0
T3	50918	0	0	0
T5	530501	0	0	0
T6	450994	0	0	0
T7	24094	0	0	0
T8	350362	0	0	0
T9	281066	0	0	0
T10	15018	0	0	0
T11	5938	0	0	0
T12	545247	0	0	0
T88	0	3917	0	0
T89	0	3092	0	0
T90	0	1252	0	0
T91	0	3571	0	0
T92	0	16443	0	0
T93	0	9594	0	0
T94	0	16885	0	0
T95	0	5956	0	0
T96	0	4637	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740887239	83959	0	0
T2	109455	962	0	0
T3	50918	0	0	0
T5	530501	0	0	0
T6	450994	0	0	0
T7	24094	0	0	0
T8	350362	0	0	0
T9	281066	0	0	0
T10	15018	0	0	0
T11	5938	0	0	0
T12	545247	0	0	0
T88	0	4696	0	0
T89	0	3597	0	0
T90	0	1383	0	0
T91	0	4167	0	0
T92	0	19355	0	0
T93	0	10378	0	0
T94	0	19794	0	0
T95	0	7086	0	0
T96	0	5480	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740887239	72459	0	0
T2	109455	896	0	0
T3	50918	0	0	0
T5	530501	0	0	0
T6	450994	0	0	0
T7	24094	0	0	0
T8	350362	0	0	0
T9	281066	0	0	0
T10	15018	0	0	0
T11	5938	0	0	0
T12	545247	0	0	0
T88	0	3991	0	0
T89	0	2886	0	0
T90	0	1130	0	0
T91	0	3773	0	0
T92	0	16570	0	0
T93	0	9408	0	0
T94	0	16855	0	0
T95	0	6087	0	0
T96	0	4295	0	0