Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	344658	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4211299	1		T1	16		T2	160		T3	12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1118935	1		T1	1		T2	47		T3	1
values[0x0]	1609117	1		T1	13		T2	85		T3	5
values[0x1]	1827905	1		T1	8		T2	115		T3	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	154127	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4401830	1		T1	18		T2	175		T3	12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17906	1		T3	2		T9	2		T10	6
valid_sources[0x01]	18144	1		T11	272		T14	1		T15	232
valid_sources[0x02]	17780	1		T8	1		T11	279		T14	1
valid_sources[0x03]	18190	1		T11	246		T15	222		T16	546
valid_sources[0x04]	17696	1		T2	2		T11	300		T14	1
valid_sources[0x05]	18442	1		T8	1		T11	292		T15	238
valid_sources[0x06]	17986	1		T8	3		T9	3		T11	303
valid_sources[0x07]	18022	1		T8	2		T11	318		T15	179
valid_sources[0x08]	16948	1		T8	8		T9	2		T11	271
valid_sources[0x09]	16318	1		T2	6		T11	253		T14	1
valid_sources[0x0a]	16849	1		T8	1		T9	1		T11	314
valid_sources[0x0b]	17362	1		T6	1		T8	2		T11	280
valid_sources[0x0c]	16640	1		T6	1		T8	1		T9	3
valid_sources[0x0d]	16891	1		T8	3		T9	1		T11	245
valid_sources[0x0e]	18063	1		T8	2		T11	309		T14	1
valid_sources[0x0f]	16267	1		T8	3		T9	2		T11	268
valid_sources[0x10]	18635	1		T3	3		T8	1		T9	1
valid_sources[0x11]	17868	1		T8	4		T9	3		T11	256
valid_sources[0x12]	19950	1		T8	1		T9	4		T11	308
valid_sources[0x13]	17011	1		T8	3		T9	1		T11	318
valid_sources[0x14]	17368	1		T8	2		T9	2		T11	270
valid_sources[0x15]	17227	1		T8	1		T11	253		T14	5
valid_sources[0x16]	17230	1		T8	3		T9	1		T11	249
valid_sources[0x17]	17609	1		T9	1		T11	275		T15	172
valid_sources[0x18]	18360	1		T8	1		T9	1		T11	292
valid_sources[0x19]	17743	1		T8	2		T9	1		T11	269
valid_sources[0x1a]	17387	1		T6	1		T9	4		T11	267
valid_sources[0x1b]	19726	1		T8	9		T9	4		T11	225
valid_sources[0x1c]	16711	1		T7	1		T8	2		T9	1
valid_sources[0x1d]	18561	1		T7	1		T8	3		T11	313
valid_sources[0x1e]	17663	1		T8	1		T9	1		T11	261
valid_sources[0x1f]	17335	1		T9	3		T11	301		T14	4
valid_sources[0x20]	17118	1		T7	1		T8	1		T9	1
valid_sources[0x21]	17620	1		T11	320		T14	2		T15	164
valid_sources[0x22]	18431	1		T2	3		T9	1		T11	255
valid_sources[0x23]	18033	1		T7	1		T8	2		T11	287
valid_sources[0x24]	18653	1		T8	2		T9	3		T11	317
valid_sources[0x25]	17535	1		T8	1		T9	4		T11	288
valid_sources[0x26]	18713	1		T2	2		T8	1		T11	286
valid_sources[0x27]	16899	1		T9	1		T11	252		T14	2
valid_sources[0x28]	18144	1		T2	2		T11	280		T14	1
valid_sources[0x29]	17717	1		T3	3		T4	2		T9	2
valid_sources[0x2a]	18768	1		T8	1		T9	1		T11	248
valid_sources[0x2b]	19082	1		T11	302		T14	4		T15	223
valid_sources[0x2c]	17378	1		T11	262		T14	2		T15	156
valid_sources[0x2d]	17290	1		T2	7		T9	1		T11	289
valid_sources[0x2e]	19983	1		T8	1		T11	244		T15	201
valid_sources[0x2f]	18400	1		T7	1		T11	259		T14	2
valid_sources[0x30]	17952	1		T11	310		T14	2		T15	222
valid_sources[0x31]	16879	1		T8	1		T9	3		T11	234
valid_sources[0x32]	18241	1		T8	1		T11	289		T14	3
valid_sources[0x33]	16916	1		T8	3		T9	2		T11	303
valid_sources[0x34]	17163	1		T9	2		T11	287		T14	3
valid_sources[0x35]	17293	1		T2	16		T9	3		T11	269
valid_sources[0x36]	17105	1		T8	1		T9	2		T11	280
valid_sources[0x37]	17179	1		T8	4		T9	2		T11	251
valid_sources[0x38]	17774	1		T6	1		T8	1		T11	229
valid_sources[0x39]	19477	1		T8	4		T9	1		T11	252
valid_sources[0x3a]	16611	1		T11	250		T14	6		T15	197
valid_sources[0x3b]	17958	1		T6	1		T7	1		T9	1
valid_sources[0x3c]	18185	1		T9	2		T11	265		T14	1
valid_sources[0x3d]	17308	1		T8	2		T9	2		T11	248
valid_sources[0x3e]	17807	1		T8	1		T11	282		T13	5
valid_sources[0x3f]	17693	1		T8	1		T9	6		T11	280
valid_sources[0x40]	18769	1		T2	7		T9	2		T11	307
valid_sources[0x41]	17964	1		T8	3		T9	1		T11	290
valid_sources[0x42]	17606	1		T8	6		T9	1		T11	284
valid_sources[0x43]	18130	1		T8	3		T9	1		T10	11
valid_sources[0x44]	19322	1		T8	3		T11	258		T14	2
valid_sources[0x45]	17566	1		T8	1		T9	2		T11	275
valid_sources[0x46]	18214	1		T9	3		T11	234		T14	1
valid_sources[0x47]	17875	1		T9	2		T11	239		T14	2
valid_sources[0x48]	17452	1		T2	1		T9	1		T11	257
valid_sources[0x49]	18102	1		T11	284		T14	2		T15	175
valid_sources[0x4a]	17317	1		T9	2		T11	256		T15	200
valid_sources[0x4b]	18933	1		T8	5		T9	1		T11	271
valid_sources[0x4c]	17052	1		T9	3		T11	292		T14	1
valid_sources[0x4d]	17968	1		T9	1		T11	302		T15	166
valid_sources[0x4e]	18011	1		T11	302		T14	2		T15	183
valid_sources[0x4f]	16892	1		T6	1		T8	1		T9	4
valid_sources[0x50]	18154	1		T8	1		T9	2		T11	254
valid_sources[0x51]	18473	1		T9	2		T11	263		T14	1
valid_sources[0x52]	17495	1		T2	3		T9	1		T11	296
valid_sources[0x53]	18818	1		T8	2		T9	2		T11	319
valid_sources[0x54]	17229	1		T7	1		T9	1		T11	236
valid_sources[0x55]	18881	1		T7	1		T9	1		T11	273
valid_sources[0x56]	18334	1		T7	1		T8	3		T11	239
valid_sources[0x57]	18439	1		T8	2		T11	248		T14	2
valid_sources[0x58]	19114	1		T2	14		T11	228		T14	2
valid_sources[0x59]	18169	1		T8	2		T9	1		T11	298
valid_sources[0x5a]	19151	1		T8	1		T11	318		T14	2
valid_sources[0x5b]	16944	1		T8	1		T11	283		T14	3
valid_sources[0x5c]	17848	1		T9	2		T11	284		T14	1
valid_sources[0x5d]	18918	1		T8	4		T9	3		T11	273
valid_sources[0x5e]	16976	1		T8	5		T9	1		T11	264
valid_sources[0x5f]	17136	1		T9	1		T11	289		T31	22
valid_sources[0x60]	18223	1		T9	1		T11	292		T15	199
valid_sources[0x61]	16620	1		T8	3		T9	3		T11	261
valid_sources[0x62]	17762	1		T9	1		T11	273		T14	3
valid_sources[0x63]	16954	1		T9	1		T11	276		T13	10
valid_sources[0x64]	17871	1		T2	2		T8	1		T11	272
valid_sources[0x65]	16989	1		T8	5		T9	2		T11	266
valid_sources[0x66]	17600	1		T8	1		T9	3		T11	271
valid_sources[0x67]	17877	1		T9	1		T11	309		T15	222
valid_sources[0x68]	18485	1		T11	280		T14	4		T15	180
valid_sources[0x69]	19726	1		T2	12		T9	2		T11	298
valid_sources[0x6a]	17832	1		T6	2		T9	4		T11	288
valid_sources[0x6b]	17419	1		T8	5		T9	6		T11	271
valid_sources[0x6c]	17821	1		T8	2		T9	2		T11	286
valid_sources[0x6d]	19029	1		T8	4		T9	1		T11	259
valid_sources[0x6e]	16882	1		T8	2		T9	1		T11	277
valid_sources[0x6f]	17964	1		T8	2		T9	2		T11	309
valid_sources[0x70]	16918	1		T9	3		T11	252		T15	266
valid_sources[0x71]	17612	1		T2	14		T8	1		T11	258
valid_sources[0x72]	18570	1		T2	8		T3	1		T11	275
valid_sources[0x73]	17962	1		T9	1		T11	244		T14	3
valid_sources[0x74]	17935	1		T8	3		T9	1		T11	254
valid_sources[0x75]	17002	1		T8	2		T9	1		T11	262
valid_sources[0x76]	18515	1		T8	3		T9	3		T11	291
valid_sources[0x77]	18135	1		T2	18		T8	2		T9	1
valid_sources[0x78]	18870	1		T2	5		T8	4		T11	287
valid_sources[0x79]	17635	1		T2	31		T6	1		T8	2
valid_sources[0x7a]	18245	1		T11	272		T14	4		T15	181
valid_sources[0x7b]	17905	1		T9	2		T11	274		T15	182
valid_sources[0x7c]	18824	1		T8	1		T9	3		T11	273
valid_sources[0x7d]	17443	1		T8	1		T9	3		T11	242
valid_sources[0x7e]	16885	1		T2	9		T8	2		T9	1
valid_sources[0x7f]	17928	1		T8	1		T9	1		T11	313
valid_sources[0x80]	18705	1		T7	1		T8	1		T9	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1049249

1

T1

1

T2

27

T3

1

values[0x0]

all_enables

biggest_size

1579883

1

T1

9

T2

57

T3

3

values[0x1]

all_enables

biggest_size

1582167

1

T1

6

T2

76

T3

8