Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	778103403	4985478	0	0
wdog_bark_thold_rd_A	778103403	77731	0	0
wdog_bite_thold_rd_A	778103403	68132	0	0
wdog_ctrl_rd_A	778103403	68099	0	0
wdog_regwen_rd_A	778103403	78157	0	0
wkup_ctrl_rd_A	778103403	68010	0	0
wkup_thold_hi_rd_A	778103403	78821	0	0
wkup_thold_lo_rd_A	778103403	68897	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	778103403	4985478	0	0
T11	291934	80606	0	0
T12	514673	0	0	0
T13	533545	0	0	0
T14	246857	0	0	0
T15	152760	52231	0	0
T16	0	155434	0	0
T30	12462	0	0	0
T31	12644	0	0	0
T32	49471	0	0	0
T33	288113	0	0	0
T43	0	172686	0	0
T44	0	332100	0	0
T45	0	55613	0	0
T46	0	117987	0	0
T47	0	158243	0	0
T48	0	28699	0	0
T49	0	52295	0	0
T50	228734	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	778103403	77731	0	0
T43	721349	9003	0	0
T44	886565	0	0	0
T45	157115	0	0	0
T46	325936	0	0	0
T47	417430	0	0	0
T48	0	3013	0	0
T53	157313	0	0	0
T54	0	10450	0	0
T78	0	6725	0	0
T82	0	4602	0	0
T83	0	2263	0	0
T84	0	3315	0	0
T85	0	9458	0	0
T86	0	5440	0	0
T87	0	19173	0	0
T88	507324	0	0	0
T89	863690	0	0	0
T90	46494	0	0	0
T91	10264	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	778103403	68132	0	0
T43	721349	7566	0	0
T44	886565	0	0	0
T45	157115	0	0	0
T46	325936	0	0	0
T47	417430	0	0	0
T48	0	2584	0	0
T53	157313	0	0	0
T54	0	8811	0	0
T78	0	5902	0	0
T82	0	4294	0	0
T83	0	2073	0	0
T84	0	2899	0	0
T85	0	8556	0	0
T86	0	4437	0	0
T87	0	17030	0	0
T88	507324	0	0	0
T89	863690	0	0	0
T90	46494	0	0	0
T91	10264	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	778103403	68099	0	0
T43	721349	7955	0	0
T44	886565	0	0	0
T45	157115	0	0	0
T46	325936	0	0	0
T47	417430	0	0	0
T48	0	2454	0	0
T53	157313	0	0	0
T54	0	8987	0	0
T78	0	6021	0	0
T82	0	4017	0	0
T83	0	2054	0	0
T84	0	2679	0	0
T85	0	8330	0	0
T86	0	4282	0	0
T87	0	17157	0	0
T88	507324	0	0	0
T89	863690	0	0	0
T90	46494	0	0	0
T91	10264	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	778103403	78157	0	0
T43	721349	8849	0	0
T44	886565	0	0	0
T45	157115	0	0	0
T46	325936	0	0	0
T47	417430	0	0	0
T48	0	2900	0	0
T53	157313	0	0	0
T54	0	10117	0	0
T78	0	6708	0	0
T82	0	4619	0	0
T83	0	2343	0	0
T84	0	3322	0	0
T85	0	9607	0	0
T86	0	4889	0	0
T87	0	19933	0	0
T88	507324	0	0	0
T89	863690	0	0	0
T90	46494	0	0	0
T91	10264	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	778103403	68010	0	0
T43	721349	7725	0	0
T44	886565	0	0	0
T45	157115	0	0	0
T46	325936	0	0	0
T47	417430	0	0	0
T48	0	2537	0	0
T53	157313	0	0	0
T54	0	8571	0	0
T78	0	6045	0	0
T82	0	4368	0	0
T83	0	2102	0	0
T84	0	3002	0	0
T85	0	7995	0	0
T86	0	4483	0	0
T87	0	16767	0	0
T88	507324	0	0	0
T89	863690	0	0	0
T90	46494	0	0	0
T91	10264	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	778103403	78821	0	0
T43	721349	9264	0	0
T44	886565	0	0	0
T45	157115	0	0	0
T46	325936	0	0	0
T47	417430	0	0	0
T48	0	3098	0	0
T53	157313	0	0	0
T54	0	10415	0	0
T78	0	6779	0	0
T82	0	4702	0	0
T83	0	2345	0	0
T84	0	3583	0	0
T85	0	9062	0	0
T86	0	5383	0	0
T87	0	19625	0	0
T88	507324	0	0	0
T89	863690	0	0	0
T90	46494	0	0	0
T91	10264	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	778103403	68897	0	0
T43	721349	8523	0	0
T44	886565	0	0	0
T45	157115	0	0	0
T46	325936	0	0	0
T47	417430	0	0	0
T48	0	2668	0	0
T53	157313	0	0	0
T54	0	8553	0	0
T78	0	5917	0	0
T82	0	4281	0	0
T83	0	2222	0	0
T84	0	2852	0	0
T85	0	8116	0	0
T86	0	4433	0	0
T87	0	17386	0	0
T88	507324	0	0	0
T89	863690	0	0	0
T90	46494	0	0	0
T91	10264	0	0	0