Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	386780	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4729920	1		T1	110039		T2	194548		T3	246

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1256615	1		T1	29347		T2	51136		T3	43
values[0x0]	1807062	1		T1	41900		T2	74170		T3	162
values[0x1]	2053023	1		T1	48229		T2	84114		T3	158

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	171410	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4945290	1		T1	115378		T2	202968		T3	273

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19055	1		T1	466		T2	797		T3	1
valid_sources[0x01]	20320	1		T1	490		T2	841		T3	1
valid_sources[0x02]	19336	1		T1	480		T2	791		T3	1
valid_sources[0x03]	20134	1		T1	487		T2	770		T4	256
valid_sources[0x04]	19691	1		T1	470		T2	800		T3	1
valid_sources[0x05]	21215	1		T1	485		T2	786		T3	2
valid_sources[0x06]	21466	1		T1	474		T2	880		T3	2
valid_sources[0x07]	18142	1		T1	420		T2	777		T3	2
valid_sources[0x08]	18348	1		T1	454		T2	799		T3	1
valid_sources[0x09]	19609	1		T1	445		T2	819		T3	1
valid_sources[0x0a]	19848	1		T1	474		T2	772		T3	1
valid_sources[0x0b]	20538	1		T1	461		T2	844		T3	1
valid_sources[0x0c]	19539	1		T1	476		T2	799		T4	309
valid_sources[0x0d]	20044	1		T1	423		T2	852		T3	2
valid_sources[0x0e]	19989	1		T1	458		T2	821		T3	2
valid_sources[0x0f]	20270	1		T1	455		T2	842		T3	1
valid_sources[0x10]	19795	1		T1	480		T2	836		T3	2
valid_sources[0x11]	19440	1		T1	474		T2	842		T3	1
valid_sources[0x12]	20525	1		T1	492		T2	817		T3	2
valid_sources[0x13]	19236	1		T1	424		T2	776		T3	1
valid_sources[0x14]	19934	1		T1	472		T2	891		T3	1
valid_sources[0x15]	19893	1		T1	483		T2	807		T3	2
valid_sources[0x16]	18777	1		T1	448		T2	888		T3	2
valid_sources[0x17]	19809	1		T1	475		T2	831		T4	303
valid_sources[0x18]	20281	1		T1	457		T2	848		T3	2
valid_sources[0x19]	18995	1		T1	455		T2	787		T3	1
valid_sources[0x1a]	20174	1		T1	492		T2	784		T3	3
valid_sources[0x1b]	21546	1		T1	466		T2	871		T3	1
valid_sources[0x1c]	20318	1		T1	469		T2	801		T3	2
valid_sources[0x1d]	21807	1		T1	462		T2	806		T3	2
valid_sources[0x1e]	19808	1		T1	474		T2	827		T3	1
valid_sources[0x1f]	20641	1		T1	456		T2	820		T3	2
valid_sources[0x20]	21332	1		T1	504		T2	777		T4	295
valid_sources[0x21]	20145	1		T1	477		T2	810		T3	2
valid_sources[0x22]	20572	1		T1	443		T2	800		T3	2
valid_sources[0x23]	18424	1		T1	435		T2	848		T3	1
valid_sources[0x24]	21146	1		T1	473		T2	794		T3	1
valid_sources[0x25]	20166	1		T1	460		T2	792		T3	1
valid_sources[0x26]	19274	1		T1	468		T2	841		T3	3
valid_sources[0x27]	21848	1		T1	485		T2	853		T4	250
valid_sources[0x28]	19642	1		T1	407		T2	815		T3	4
valid_sources[0x29]	20033	1		T1	403		T2	832		T4	288
valid_sources[0x2a]	19403	1		T1	434		T2	850		T4	236
valid_sources[0x2b]	19231	1		T1	477		T2	889		T3	1
valid_sources[0x2c]	18718	1		T1	433		T2	781		T4	253
valid_sources[0x2d]	20506	1		T1	449		T2	787		T3	3
valid_sources[0x2e]	18820	1		T1	471		T2	783		T3	1
valid_sources[0x2f]	19738	1		T1	478		T2	850		T4	251
valid_sources[0x30]	18994	1		T1	429		T2	817		T3	1
valid_sources[0x31]	18939	1		T1	472		T2	822		T3	2
valid_sources[0x32]	18659	1		T1	446		T2	791		T3	2
valid_sources[0x33]	20407	1		T1	488		T2	768		T4	264
valid_sources[0x34]	20266	1		T1	425		T2	830		T3	3
valid_sources[0x35]	21577	1		T1	523		T2	811		T3	3
valid_sources[0x36]	19793	1		T1	483		T2	814		T3	6
valid_sources[0x37]	19362	1		T1	487		T2	847		T3	2
valid_sources[0x38]	19560	1		T1	476		T2	821		T3	2
valid_sources[0x39]	19566	1		T1	422		T2	812		T4	299
valid_sources[0x3a]	19248	1		T1	458		T2	859		T3	4
valid_sources[0x3b]	19282	1		T1	457		T2	802		T3	3
valid_sources[0x3c]	19575	1		T1	492		T2	853		T3	3
valid_sources[0x3d]	21070	1		T1	455		T2	776		T3	2
valid_sources[0x3e]	19557	1		T1	470		T2	817		T4	294
valid_sources[0x3f]	20728	1		T1	453		T2	827		T4	271
valid_sources[0x40]	18603	1		T1	475		T2	793		T4	342
valid_sources[0x41]	18793	1		T1	474		T2	828		T3	1
valid_sources[0x42]	20855	1		T1	457		T2	839		T3	2
valid_sources[0x43]	21295	1		T1	450		T2	814		T3	1
valid_sources[0x44]	20772	1		T1	514		T2	805		T3	2
valid_sources[0x45]	19333	1		T1	486		T2	804		T4	272
valid_sources[0x46]	20976	1		T1	460		T2	804		T4	238
valid_sources[0x47]	19928	1		T1	455		T2	781		T3	1
valid_sources[0x48]	19926	1		T1	504		T2	812		T3	4
valid_sources[0x49]	19478	1		T1	512		T2	796		T3	3
valid_sources[0x4a]	18855	1		T1	474		T2	797		T3	1
valid_sources[0x4b]	20974	1		T1	485		T2	803		T4	355
valid_sources[0x4c]	21194	1		T1	438		T2	827		T3	3
valid_sources[0x4d]	20017	1		T1	443		T2	812		T3	3
valid_sources[0x4e]	19203	1		T1	494		T2	838		T3	4
valid_sources[0x4f]	20741	1		T1	448		T2	819		T3	1
valid_sources[0x50]	20573	1		T1	438		T2	838		T3	2
valid_sources[0x51]	19683	1		T1	486		T2	811		T4	287
valid_sources[0x52]	18406	1		T1	501		T2	853		T3	1
valid_sources[0x53]	19448	1		T1	440		T2	803		T3	3
valid_sources[0x54]	20530	1		T1	468		T2	834		T4	283
valid_sources[0x55]	20688	1		T1	479		T2	833		T3	1
valid_sources[0x56]	19472	1		T1	508		T2	778		T4	316
valid_sources[0x57]	20480	1		T1	430		T2	829		T3	1
valid_sources[0x58]	19041	1		T1	459		T2	847		T3	2
valid_sources[0x59]	19629	1		T1	484		T2	814		T4	269
valid_sources[0x5a]	20870	1		T1	485		T2	818		T3	3
valid_sources[0x5b]	20411	1		T1	438		T2	792		T3	3
valid_sources[0x5c]	20630	1		T1	489		T2	791		T3	1
valid_sources[0x5d]	20763	1		T1	461		T2	814		T3	1
valid_sources[0x5e]	19920	1		T1	472		T2	824		T3	1
valid_sources[0x5f]	20681	1		T1	464		T2	820		T4	298
valid_sources[0x60]	20771	1		T1	482		T2	882		T3	1
valid_sources[0x61]	19856	1		T1	480		T2	853		T4	184
valid_sources[0x62]	19549	1		T1	497		T2	849		T3	3
valid_sources[0x63]	20328	1		T1	472		T2	835		T3	1
valid_sources[0x64]	20815	1		T1	478		T2	856		T3	2
valid_sources[0x65]	19687	1		T1	432		T2	853		T3	7
valid_sources[0x66]	21601	1		T1	510		T2	768		T4	437
valid_sources[0x67]	19843	1		T1	481		T2	785		T4	303
valid_sources[0x68]	19207	1		T1	440		T2	825		T3	2
valid_sources[0x69]	19427	1		T1	471		T2	825		T3	2
valid_sources[0x6a]	22550	1		T1	475		T2	858		T3	3
valid_sources[0x6b]	20633	1		T1	457		T2	813		T3	1
valid_sources[0x6c]	19598	1		T1	429		T2	792		T3	4
valid_sources[0x6d]	20571	1		T1	478		T2	790		T3	2
valid_sources[0x6e]	19185	1		T1	503		T2	819		T3	1
valid_sources[0x6f]	20691	1		T1	467		T2	795		T3	2
valid_sources[0x70]	18939	1		T1	441		T2	879		T3	1
valid_sources[0x71]	19724	1		T1	470		T2	887		T3	2
valid_sources[0x72]	20317	1		T1	491		T2	853		T3	3
valid_sources[0x73]	20047	1		T1	486		T2	796		T3	3
valid_sources[0x74]	19970	1		T1	488		T2	858		T4	245
valid_sources[0x75]	20141	1		T1	455		T2	862		T3	1
valid_sources[0x76]	19557	1		T1	470		T2	788		T3	1
valid_sources[0x77]	19111	1		T1	439		T2	771		T3	4
valid_sources[0x78]	20272	1		T1	481		T2	811		T3	3
valid_sources[0x79]	19188	1		T1	473		T2	772		T3	2
valid_sources[0x7a]	19510	1		T1	467		T2	859		T3	2
valid_sources[0x7b]	21264	1		T1	495		T2	801		T4	206
valid_sources[0x7c]	19128	1		T1	447		T2	905		T3	1
valid_sources[0x7d]	19449	1		T1	464		T2	817		T4	226
valid_sources[0x7e]	19778	1		T1	460		T2	804		T3	2
valid_sources[0x7f]	19486	1		T1	453		T2	787		T3	1
valid_sources[0x80]	20355	1		T1	479		T2	772		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1178391

1

T1

27529

T2

48187

T3

24

values[0x0]

all_enables

biggest_size

1774717

1

T1

41128

T2

73033

T3

114

values[0x1]

all_enables

biggest_size

1776812

1

T1

41382

T2

73328

T3

108