Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	638025099	5653680	0	0
wdog_bark_thold_rd_A	638025099	77916	0	0
wdog_bite_thold_rd_A	638025099	69613	0	0
wdog_ctrl_rd_A	638025099	67947	0	0
wdog_regwen_rd_A	638025099	78623	0	0
wkup_ctrl_rd_A	638025099	69022	0	0
wkup_thold_hi_rd_A	638025099	78586	0	0
wkup_thold_lo_rd_A	638025099	67552	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	638025099	5653680	0	0
T1	501314	137000	0	0
T2	915552	234209	0	0
T3	193506	0	0	0
T4	336187	81974	0	0
T5	566651	0	0	0
T6	7266	0	0	0
T7	792686	0	0	0
T8	193479	0	0	0
T9	723831	0	0	0
T10	14327	0	0	0
T11	0	92894	0	0
T26	0	17539	0	0
T27	0	119176	0	0
T28	0	194703	0	0
T34	0	98241	0	0
T35	0	90898	0	0
T36	0	49803	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	638025099	77916	0	0
T2	915552	12250	0	0
T3	193506	0	0	0
T4	336187	4100	0	0
T5	566651	0	0	0
T6	7266	0	0	0
T7	792686	0	0	0
T8	193479	0	0	0
T9	723831	0	0	0
T10	14327	0	0	0
T11	376151	0	0	0
T28	0	9991	0	0
T31	0	6	0	0
T43	0	6369	0	0
T89	0	6512	0	0
T90	0	17697	0	0
T91	0	5677	0	0
T92	0	9953	0	0
T93	0	4184	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	638025099	69613	0	0
T2	915552	11417	0	0
T3	193506	0	0	0
T4	336187	3749	0	0
T5	566651	0	0	0
T6	7266	0	0	0
T7	792686	0	0	0
T8	193479	0	0	0
T9	723831	0	0	0
T10	14327	0	0	0
T11	376151	0	0	0
T28	0	8776	0	0
T31	0	3	0	0
T43	0	5654	0	0
T89	0	5691	0	0
T90	0	15128	0	0
T91	0	5298	0	0
T92	0	8880	0	0
T93	0	4002	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	638025099	67947	0	0
T2	915552	11038	0	0
T3	193506	0	0	0
T4	336187	3512	0	0
T5	566651	0	0	0
T6	7266	0	0	0
T7	792686	0	0	0
T8	193479	0	0	0
T9	723831	0	0	0
T10	14327	0	0	0
T11	376151	0	0	0
T28	0	8721	0	0
T31	0	12	0	0
T43	0	5492	0	0
T89	0	5467	0	0
T90	0	15244	0	0
T91	0	5210	0	0
T92	0	8276	0	0
T93	0	3767	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	638025099	78623	0	0
T2	915552	12394	0	0
T3	193506	0	0	0
T4	336187	4111	0	0
T5	566651	0	0	0
T6	7266	0	0	0
T7	792686	0	0	0
T8	193479	0	0	0
T9	723831	0	0	0
T10	14327	0	0	0
T11	376151	0	0	0
T28	0	10018	0	0
T31	0	1	0	0
T43	0	6675	0	0
T89	0	6190	0	0
T90	0	18077	0	0
T91	0	5840	0	0
T92	0	9609	0	0
T93	0	4348	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	638025099	69022	0	0
T2	915552	10966	0	0
T3	193506	0	0	0
T4	336187	3544	0	0
T5	566651	0	0	0
T6	7266	0	0	0
T7	792686	0	0	0
T8	193479	0	0	0
T9	723831	0	0	0
T10	14327	0	0	0
T11	376151	0	0	0
T28	0	9024	0	0
T31	0	4	0	0
T43	0	5797	0	0
T89	0	5737	0	0
T90	0	15556	0	0
T91	0	5190	0	0
T92	0	8097	0	0
T93	0	3965	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	638025099	78586	0	0
T2	915552	12342	0	0
T3	193506	0	0	0
T4	336187	3962	0	0
T5	566651	0	0	0
T6	7266	0	0	0
T7	792686	0	0	0
T8	193479	0	0	0
T9	723831	0	0	0
T10	14327	0	0	0
T11	376151	0	0	0
T28	0	10504	0	0
T31	0	1	0	0
T43	0	6207	0	0
T89	0	6491	0	0
T90	0	17698	0	0
T91	0	6063	0	0
T92	0	9897	0	0
T93	0	4382	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	638025099	67552	0	0
T2	915552	10295	0	0
T3	193506	0	0	0
T4	336187	3623	0	0
T5	566651	0	0	0
T6	7266	0	0	0
T7	792686	0	0	0
T8	193479	0	0	0
T9	723831	0	0	0
T10	14327	0	0	0
T11	376151	0	0	0
T28	0	8628	0	0
T31	0	2	0	0
T43	0	5446	0	0
T89	0	5708	0	0
T90	0	15784	0	0
T91	0	4938	0	0
T92	0	8291	0	0
T93	0	3801	0	0