Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	327301	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4007528	1		T1	12		T2	15		T3	166034

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1063888	1		T1	1		T2	1		T3	43642
values[0x0]	1531337	1		T1	8		T2	9		T3	63156
values[0x1]	1739604	1		T1	9		T2	9		T3	72192

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	146416	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4188413	1		T1	12		T2	15		T3	173375

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16587	1		T3	302		T4	251		T7	550
valid_sources[0x01]	16830	1		T3	337		T4	336		T6	2
valid_sources[0x02]	15900	1		T3	279		T4	316		T6	2
valid_sources[0x03]	17678	1		T3	1187		T4	257		T6	2
valid_sources[0x04]	16750	1		T3	1010		T4	259		T7	567
valid_sources[0x05]	16369	1		T3	556		T4	273		T6	3
valid_sources[0x06]	16140	1		T3	1194		T4	322		T6	1
valid_sources[0x07]	16504	1		T3	484		T4	448		T6	3
valid_sources[0x08]	17732	1		T3	438		T4	227		T7	684
valid_sources[0x09]	16136	1		T3	315		T4	237		T6	1
valid_sources[0x0a]	16387	1		T3	287		T4	287		T7	633
valid_sources[0x0b]	16161	1		T3	761		T4	309		T7	546
valid_sources[0x0c]	16820	1		T3	939		T4	293		T6	3
valid_sources[0x0d]	16682	1		T3	773		T4	353		T6	2
valid_sources[0x0e]	18586	1		T3	1411		T4	322		T6	3
valid_sources[0x0f]	17215	1		T3	708		T4	286		T7	620
valid_sources[0x10]	16332	1		T3	337		T4	303		T7	546
valid_sources[0x11]	17077	1		T3	945		T4	327		T6	2
valid_sources[0x12]	17139	1		T3	974		T4	263		T7	611
valid_sources[0x13]	16086	1		T3	241		T4	325		T6	1
valid_sources[0x14]	17122	1		T3	1239		T4	348		T6	1
valid_sources[0x15]	17461	1		T3	1702		T4	251		T6	1
valid_sources[0x16]	16280	1		T3	2		T4	362		T6	3
valid_sources[0x17]	17190	1		T3	631		T4	316		T7	695
valid_sources[0x18]	17665	1		T3	632		T4	259		T7	667
valid_sources[0x19]	16602	1		T3	841		T4	316		T6	2
valid_sources[0x1a]	17022	1		T3	734		T4	420		T6	3
valid_sources[0x1b]	16086	1		T3	651		T4	318		T6	1
valid_sources[0x1c]	15984	1		T3	380		T4	189		T6	2
valid_sources[0x1d]	16417	1		T3	365		T4	199		T7	555
valid_sources[0x1e]	17444	1		T3	933		T4	224		T7	633
valid_sources[0x1f]	17032	1		T3	526		T4	305		T6	2
valid_sources[0x20]	17253	1		T3	719		T4	325		T6	1
valid_sources[0x21]	15279	1		T3	343		T4	262		T6	1
valid_sources[0x22]	16726	1		T3	721		T4	233		T7	588
valid_sources[0x23]	16964	1		T3	518		T4	291		T6	2
valid_sources[0x24]	17240	1		T3	515		T4	245		T6	2
valid_sources[0x25]	17845	1		T3	824		T4	384		T7	560
valid_sources[0x26]	18769	1		T3	442		T4	371		T6	2
valid_sources[0x27]	16565	1		T1	1		T3	770		T4	222
valid_sources[0x28]	17712	1		T3	1373		T4	295		T6	1
valid_sources[0x29]	17517	1		T3	844		T4	233		T6	1
valid_sources[0x2a]	16752	1		T3	807		T4	245		T6	2
valid_sources[0x2b]	17073	1		T3	550		T4	243		T6	2
valid_sources[0x2c]	17634	1		T3	1224		T4	196		T6	2
valid_sources[0x2d]	17446	1		T3	607		T4	262		T6	3
valid_sources[0x2e]	17045	1		T3	499		T4	351		T7	578
valid_sources[0x2f]	16523	1		T3	971		T4	269		T7	582
valid_sources[0x30]	18173	1		T3	805		T4	300		T6	1
valid_sources[0x31]	16197	1		T3	668		T4	352		T6	2
valid_sources[0x32]	17067	1		T3	601		T4	358		T6	2
valid_sources[0x33]	16128	1		T3	457		T4	257		T6	3
valid_sources[0x34]	17208	1		T3	1482		T4	266		T6	1
valid_sources[0x35]	17896	1		T3	481		T4	390		T6	1
valid_sources[0x36]	16678	1		T3	131		T4	280		T6	3
valid_sources[0x37]	17211	1		T3	738		T4	413		T5	346
valid_sources[0x38]	17568	1		T3	336		T4	253		T6	1
valid_sources[0x39]	17554	1		T3	471		T4	358		T6	3
valid_sources[0x3a]	16316	1		T3	991		T4	373		T6	1
valid_sources[0x3b]	16935	1		T3	361		T4	329		T6	2
valid_sources[0x3c]	16688	1		T3	231		T4	356		T6	3
valid_sources[0x3d]	17736	1		T3	1106		T4	265		T7	552
valid_sources[0x3e]	17072	1		T3	1005		T4	406		T6	1
valid_sources[0x3f]	16419	1		T3	1156		T4	253		T7	641
valid_sources[0x40]	16141	1		T3	1052		T4	389		T6	3
valid_sources[0x41]	17304	1		T3	1081		T4	295		T7	572
valid_sources[0x42]	18321	1		T3	1798		T4	293		T7	508
valid_sources[0x43]	17666	1		T3	918		T4	265		T6	4
valid_sources[0x44]	16717	1		T3	1097		T4	243		T6	1
valid_sources[0x45]	16532	1		T3	174		T4	190		T7	534
valid_sources[0x46]	17007	1		T3	202		T4	260		T6	1
valid_sources[0x47]	15494	1		T3	1314		T4	268		T6	1
valid_sources[0x48]	15342	1		T3	532		T4	397		T6	1
valid_sources[0x49]	15465	1		T3	618		T4	251		T6	4
valid_sources[0x4a]	17874	1		T3	697		T4	236		T6	2
valid_sources[0x4b]	16973	1		T3	735		T4	398		T7	613
valid_sources[0x4c]	16475	1		T3	134		T4	265		T6	2
valid_sources[0x4d]	16226	1		T3	182		T4	260		T6	1
valid_sources[0x4e]	15740	1		T3	258		T4	253		T7	475
valid_sources[0x4f]	17721	1		T3	881		T4	220		T7	675
valid_sources[0x50]	17097	1		T3	1695		T4	218		T7	593
valid_sources[0x51]	16066	1		T3	386		T4	240		T7	575
valid_sources[0x52]	16544	1		T3	837		T4	278		T6	2
valid_sources[0x53]	15445	1		T3	311		T4	407		T6	1
valid_sources[0x54]	16000	1		T3	703		T4	266		T6	1
valid_sources[0x55]	16302	1		T3	226		T4	239		T6	1
valid_sources[0x56]	15681	1		T3	354		T4	350		T6	1
valid_sources[0x57]	18092	1		T3	1002		T4	296		T6	2
valid_sources[0x58]	16293	1		T3	1090		T4	346		T6	2
valid_sources[0x59]	16443	1		T3	863		T4	328		T6	2
valid_sources[0x5a]	16209	1		T3	768		T4	329		T6	2
valid_sources[0x5b]	17289	1		T3	454		T4	238		T7	585
valid_sources[0x5c]	16882	1		T3	702		T4	275		T6	1
valid_sources[0x5d]	16838	1		T3	366		T4	353		T6	1
valid_sources[0x5e]	17495	1		T3	627		T4	275		T6	2
valid_sources[0x5f]	17518	1		T3	598		T4	261		T6	3
valid_sources[0x60]	17312	1		T3	457		T4	193		T7	574
valid_sources[0x61]	14844	1		T3	13		T4	223		T6	1
valid_sources[0x62]	18528	1		T3	1011		T4	264		T7	618
valid_sources[0x63]	17349	1		T3	383		T4	277		T6	4
valid_sources[0x64]	16613	1		T3	1266		T4	295		T7	578
valid_sources[0x65]	18040	1		T3	892		T4	289		T6	2
valid_sources[0x66]	16926	1		T3	1130		T4	275		T6	1
valid_sources[0x67]	17396	1		T3	964		T4	320		T7	654
valid_sources[0x68]	16694	1		T3	845		T4	339		T7	582
valid_sources[0x69]	17414	1		T3	609		T4	257		T6	1
valid_sources[0x6a]	17845	1		T3	1043		T4	302		T6	2
valid_sources[0x6b]	17037	1		T3	923		T4	334		T7	515
valid_sources[0x6c]	16278	1		T3	606		T4	279		T6	1
valid_sources[0x6d]	16671	1		T1	3		T3	869		T4	364
valid_sources[0x6e]	15579	1		T3	596		T4	371		T6	1
valid_sources[0x6f]	15590	1		T3	468		T4	200		T6	1
valid_sources[0x70]	17670	1		T3	619		T4	311		T6	2
valid_sources[0x71]	17490	1		T3	964		T4	447		T7	617
valid_sources[0x72]	17131	1		T3	1046		T4	260		T7	635
valid_sources[0x73]	18033	1		T3	988		T4	278		T6	1
valid_sources[0x74]	16957	1		T3	679		T4	303		T6	2
valid_sources[0x75]	16973	1		T3	1251		T4	251		T7	508
valid_sources[0x76]	19522	1		T3	1351		T4	350		T6	1
valid_sources[0x77]	15054	1		T3	795		T4	302		T6	2
valid_sources[0x78]	16735	1		T3	230		T4	350		T6	1
valid_sources[0x79]	19005	1		T3	228		T4	266		T6	1
valid_sources[0x7a]	17573	1		T3	1178		T4	234		T6	1
valid_sources[0x7b]	17104	1		T1	5		T3	617		T4	347
valid_sources[0x7c]	16320	1		T3	685		T4	240		T6	1
valid_sources[0x7d]	18472	1		T3	658		T4	267		T6	1
valid_sources[0x7e]	17174	1		T3	935		T4	282		T6	4
valid_sources[0x7f]	16429	1		T3	375		T4	155		T6	1
valid_sources[0x80]	17347	1		T3	1012		T4	295		T7	553

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

997314

1

T1

1

T2

1

T3

41195

values[0x0]

all_enables

biggest_size

1503618

1

T1

6

T2

7

T3

62151

values[0x1]

all_enables

biggest_size

1506596

1

T1

5

T2

7

T3

62688