Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	820326753	4763243	0	0
wdog_bark_thold_rd_A	820326753	129693	0	0
wdog_bite_thold_rd_A	820326753	112778	0	0
wdog_ctrl_rd_A	820326753	112471	0	0
wdog_regwen_rd_A	820326753	129693	0	0
wkup_ctrl_rd_A	820326753	112695	0	0
wkup_thold_hi_rd_A	820326753	130796	0	0
wkup_thold_lo_rd_A	820326753	113833	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	820326753	4763243	0	0
T3	727808	197375	0	0
T4	326896	84121	0	0
T5	345820	0	0	0
T6	390873	0	0	0
T7	641241	174715	0	0
T8	141001	0	0	0
T9	4329	0	0	0
T10	119721	0	0	0
T11	504498	0	0	0
T12	854067	187443	0	0
T33	0	142074	0	0
T34	0	166171	0	0
T35	0	99513	0	0
T36	0	118603	0	0
T37	0	57816	0	0
T38	0	121186	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	820326753	129693	0	0
T12	854067	9325	0	0
T18	0	3996	0	0
T33	0	14320	0	0
T36	0	11584	0	0
T39	662329	0	0	0
T40	5883	0	0	0
T41	481692	0	0	0
T42	444467	0	0	0
T43	28716	0	0	0
T44	364006	0	0	0
T47	139956	0	0	0
T48	11942	0	0	0
T49	483458	0	0	0
T78	0	7571	0	0
T83	0	9026	0	0
T84	0	7026	0	0
T85	0	6710	0	0
T86	0	3249	0	0
T87	0	7977	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	820326753	112778	0	0
T12	854067	8743	0	0
T18	0	3560	0	0
T33	0	12247	0	0
T36	0	10298	0	0
T39	662329	0	0	0
T40	5883	0	0	0
T41	481692	0	0	0
T42	444467	0	0	0
T43	28716	0	0	0
T44	364006	0	0	0
T47	139956	0	0	0
T48	11942	0	0	0
T49	483458	0	0	0
T78	0	7043	0	0
T83	0	8333	0	0
T84	0	6146	0	0
T85	0	5377	0	0
T86	0	2613	0	0
T87	0	6992	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	820326753	112471	0	0
T12	854067	8394	0	0
T18	0	3233	0	0
T33	0	12433	0	0
T36	0	10278	0	0
T39	662329	0	0	0
T40	5883	0	0	0
T41	481692	0	0	0
T42	444467	0	0	0
T43	28716	0	0	0
T44	364006	0	0	0
T47	139956	0	0	0
T48	11942	0	0	0
T49	483458	0	0	0
T78	0	6983	0	0
T83	0	7597	0	0
T84	0	6159	0	0
T85	0	5451	0	0
T86	0	2900	0	0
T87	0	7164	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	820326753	129693	0	0
T12	854067	9656	0	0
T18	0	3947	0	0
T33	0	14330	0	0
T36	0	11474	0	0
T39	662329	0	0	0
T40	5883	0	0	0
T41	481692	0	0	0
T42	444467	0	0	0
T43	28716	0	0	0
T44	364006	0	0	0
T47	139956	0	0	0
T48	11942	0	0	0
T49	483458	0	0	0
T78	0	8150	0	0
T83	0	9154	0	0
T84	0	7350	0	0
T85	0	6425	0	0
T86	0	3217	0	0
T87	0	7569	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	820326753	112695	0	0
T12	854067	8479	0	0
T18	0	3366	0	0
T33	0	12810	0	0
T36	0	10483	0	0
T39	662329	0	0	0
T40	5883	0	0	0
T41	481692	0	0	0
T42	444467	0	0	0
T43	28716	0	0	0
T44	364006	0	0	0
T47	139956	0	0	0
T48	11942	0	0	0
T49	483458	0	0	0
T78	0	6872	0	0
T83	0	7647	0	0
T84	0	5749	0	0
T85	0	5451	0	0
T86	0	2665	0	0
T87	0	6957	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	820326753	130796	0	0
T12	854067	9758	0	0
T18	0	3794	0	0
T33	0	14274	0	0
T36	0	12026	0	0
T39	662329	0	0	0
T40	5883	0	0	0
T41	481692	0	0	0
T42	444467	0	0	0
T43	28716	0	0	0
T44	364006	0	0	0
T47	139956	0	0	0
T48	11942	0	0	0
T49	483458	0	0	0
T78	0	8286	0	0
T83	0	8802	0	0
T84	0	7070	0	0
T85	0	6738	0	0
T86	0	3313	0	0
T87	0	8242	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	820326753	113833	0	0
T12	854067	8276	0	0
T18	0	3516	0	0
T33	0	12619	0	0
T36	0	9951	0	0
T39	662329	0	0	0
T40	5883	0	0	0
T41	481692	0	0	0
T42	444467	0	0	0
T43	28716	0	0	0
T44	364006	0	0	0
T47	139956	0	0	0
T48	11942	0	0	0
T49	483458	0	0	0
T78	0	6853	0	0
T83	0	7737	0	0
T84	0	6100	0	0
T85	0	5826	0	0
T86	0	2910	0	0
T87	0	7144	0	0