Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : aon_timer_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.57 100.00 98.28 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg 99.57 100.00 98.28 100.00 100.00



Module Instance : tb.dut.u_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.57 100.00 98.28 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.90 99.26 93.96 100.00 98.30 98.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 66.67 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_alert_test 100.00 100.00
u_chk 100.00 100.00 100.00 100.00
u_intr_state_wdog_timer_bark 100.00 100.00 100.00 100.00
u_intr_state_wkup_timer_expired 100.00 100.00 100.00 100.00
u_intr_test_wdog_timer_bark 100.00 100.00
u_intr_test_wkup_timer_expired 100.00 100.00
u_prim_reg_we_check 100.00 100.00 100.00
u_reg_if 98.69 97.14 97.62 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00
u_wdog_bark_thold 100.00 100.00 100.00 100.00
u_wdog_bark_thold_cdc 99.17 100.00 96.67 100.00 100.00
u_wdog_bite_thold 100.00 100.00 100.00 100.00
u_wdog_bite_thold_cdc 99.17 100.00 96.67 100.00 100.00
u_wdog_count 100.00 100.00 100.00 100.00
u_wdog_count_cdc 97.11 100.00 90.14 98.31 100.00
u_wdog_ctrl_cdc 99.17 100.00 96.67 100.00 100.00
u_wdog_ctrl_enable 100.00 100.00 100.00 100.00
u_wdog_ctrl_pause_in_sleep 100.00 100.00 100.00 100.00
u_wdog_regwen 100.00 100.00 100.00 100.00
u_wkup_cause 100.00 100.00 100.00 100.00
u_wkup_cause_cdc 97.18 100.00 90.41 98.31 100.00
u_wkup_count_hi 100.00 100.00 100.00 100.00
u_wkup_count_hi_cdc 84.10 94.74 71.83 89.83 80.00
u_wkup_count_lo 100.00 100.00 100.00 100.00
u_wkup_count_lo_cdc 97.11 100.00 90.14 98.31 100.00
u_wkup_ctrl_cdc 99.17 100.00 96.67 100.00 100.00
u_wkup_ctrl_enable 100.00 100.00 100.00 100.00
u_wkup_ctrl_prescaler 100.00 100.00 100.00 100.00
u_wkup_thold_hi 100.00 100.00 100.00 100.00
u_wkup_thold_hi_cdc 99.17 100.00 96.67 100.00 100.00
u_wkup_thold_lo 100.00 100.00 100.00 100.00
u_wkup_thold_lo_cdc 99.17 100.00 96.67 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : aon_timer_reg_top
Line No.TotalCoveredPercent
TOTAL146146100.00
ALWAYS7044100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN9111100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12111100.00
ALWAYS18033100.00
CONT_ASSIGN20911100.00
ALWAYS21922100.00
CONT_ASSIGN24711100.00
ALWAYS25722100.00
CONT_ASSIGN28511100.00
ALWAYS29844100.00
CONT_ASSIGN32811100.00
ALWAYS34144100.00
CONT_ASSIGN37111100.00
ALWAYS38333100.00
CONT_ASSIGN41211100.00
ALWAYS42322100.00
CONT_ASSIGN45111100.00
ALWAYS46222100.00
CONT_ASSIGN49011100.00
ALWAYS50344100.00
CONT_ASSIGN53311100.00
ALWAYS54644100.00
CONT_ASSIGN57611100.00
CONT_ASSIGN58311100.00
CONT_ASSIGN59711100.00
CONT_ASSIGN71411100.00
CONT_ASSIGN74411100.00
CONT_ASSIGN80311100.00
CONT_ASSIGN86211100.00
CONT_ASSIGN89311100.00
CONT_ASSIGN92311100.00
CONT_ASSIGN101011100.00
CONT_ASSIGN102511100.00
CONT_ASSIGN104111100.00
CONT_ASSIGN104611100.00
ALWAYS10771515100.00
CONT_ASSIGN109411100.00
ALWAYS109811100.00
CONT_ASSIGN111611100.00
CONT_ASSIGN111811100.00
CONT_ASSIGN111911100.00
CONT_ASSIGN112211100.00
CONT_ASSIGN112411100.00
CONT_ASSIGN112611100.00
CONT_ASSIGN112811100.00
CONT_ASSIGN113011100.00
CONT_ASSIGN113211100.00
CONT_ASSIGN113311100.00
CONT_ASSIGN113611100.00
CONT_ASSIGN113811100.00
CONT_ASSIGN114011100.00
CONT_ASSIGN114211100.00
CONT_ASSIGN114411100.00
CONT_ASSIGN114611100.00
CONT_ASSIGN114711100.00
CONT_ASSIGN114911100.00
CONT_ASSIGN115111100.00
CONT_ASSIGN115211100.00
ALWAYS11571515100.00
ALWAYS11761818100.00
CONT_ASSIGN123811100.00
ALWAYS12401212100.00
CONT_ASSIGN128511100.00
CONT_ASSIGN128611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_reg_top.sv' or '../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
79 1 1
91 1 1
92 1 1
120 1 1
121 1 1
180 1 1
181 1 1
182 1 1
209 1 1
219 1 1
220 1 1
247 1 1
257 1 1
258 1 1
285 1 1
298 1 1
299 1 1
300 1 1
301 1 1
328 1 1
341 1 1
342 1 1
343 1 1
344 1 1
371 1 1
383 1 1
384 1 1
385 1 1
412 1 1
423 1 1
424 1 1
451 1 1
462 1 1
463 1 1
490 1 1
503 1 1
504 1 1
505 1 1
506 1 1
533 1 1
546 1 1
547 1 1
548 1 1
549 1 1
576 1 1
583 1 1
597 1 1
714 1 1
744 1 1
803 1 1
862 1 1
893 1 1
923 1 1
1010 1 1
1025 1 1
1041 1 1
1046 1 1
1077 1 1
1078 1 1
1079 1 1
1080 1 1
1081 1 1
1082 1 1
1083 1 1
1084 1 1
1085 1 1
1086 1 1
1087 1 1
1088 1 1
1089 1 1
1090 1 1
1091 1 1
1094 1 1
1098 1 1
1116 1 1
1118 1 1
1119 1 1
1122 1 1
1124 1 1
1126 1 1
1128 1 1
1130 1 1
1132 1 1
1133 1 1
1136 1 1
1138 1 1
1140 1 1
1142 1 1
1144 1 1
1146 1 1
1147 1 1
1149 1 1
1151 1 1
1152 1 1
1157 1 1
1158 1 1
1159 1 1
1160 1 1
1161 1 1
1162 1 1
1163 1 1
1164 1 1
1165 1 1
1166 1 1
1167 1 1
1168 1 1
1169 1 1
1170 1 1
1171 1 1
1176 1 1
1177 1 1
1179 1 1
1183 1 1
1186 1 1
1189 1 1
1192 1 1
1195 1 1
1198 1 1
1202 1 1
1205 1 1
1208 1 1
1211 1 1
1214 1 1
1215 1 1
1219 1 1
1220 1 1
1224 1 1
1238 1 1
1240 1 1
1241 1 1
1243 1 1
1246 1 1
1249 1 1
1252 1 1
1255 1 1
1258 1 1
1261 1 1
1264 1 1
1267 1 1
1270 1 1
1285 1 1
1286 1 1


Cond Coverage for Module : aon_timer_reg_top
TotalCoveredPercent
Conditions17417198.28
Logical17417198.28
Non-Logical00
Event00

 LINE       60
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T7
11CoveredT1,T2,T3

 LINE       72
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT13,T14,T15
10CoveredT27,T29,T30

 LINE       79
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT13,T14,T15
010CoveredT27,T29,T30
100CoveredT13,T14,T15

 LINE       121
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT27,T29,T30
010CoveredT3,T4,T7
100CoveredT3,T4,T7

 LINE       803
 EXPRESSION (aon_wdog_ctrl_we & aon_wdog_ctrl_regwen)
             --------1-------   ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T4
11CoveredT2,T3,T4

 LINE       862
 EXPRESSION (aon_wdog_bark_thold_we & aon_wdog_bark_thold_regwen)
             -----------1----------   -------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT3,T4,T5
11CoveredT1,T2,T3

 LINE       893
 EXPRESSION (aon_wdog_bite_thold_we & aon_wdog_bite_thold_regwen)
             -----------1----------   -------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT3,T4,T5
11CoveredT1,T2,T3

 LINE       1078
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_ALERT_TEST_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T7

 LINE       1079
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WKUP_CTRL_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1080
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WKUP_THOLD_HI_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1081
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WKUP_THOLD_LO_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1082
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WKUP_COUNT_HI_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1083
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WKUP_COUNT_LO_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1084
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WDOG_REGWEN_OFFSET)
            ------------------------------1------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1085
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WDOG_CTRL_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1086
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WDOG_BARK_THOLD_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1087
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WDOG_BITE_THOLD_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1088
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WDOG_COUNT_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1089
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_INTR_STATE_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1090
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_INTR_TEST_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       1091
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WKUP_CAUSE_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1094
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1094
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       1098
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT3,T4,T5
10CoveredT1,T2,T3
11CoveredT3,T4,T7

 LINE       1098
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1111 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1111 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1 & (~reg_be))))))
-1--2--3--4--5--6--7--8--9--10--11--12--13--14-StatusTests
00000000000000CoveredT1,T2,T3
00000000000001CoveredT3,T4,T7
00000000000010CoveredT3,T4,T5
00000000000100CoveredT3,T4,T5
00000000001000CoveredT3,T4,T7
00000000010000CoveredT3,T4,T7
00000000100000CoveredT3,T4,T7
00000001000000CoveredT3,T4,T7
00000010000000CoveredT3,T4,T7
00000100000000CoveredT3,T4,T7
00001000000000CoveredT3,T4,T7
00010000000000CoveredT3,T4,T7
00100000000000CoveredT3,T4,T7
01000000000000CoveredT3,T4,T7
10000000000000CoveredT3,T4,T7

 LINE       1098
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT3,T4,T5
10CoveredT3,T4,T7
11CoveredT3,T4,T7

 LINE       1098
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT3,T4,T7

 LINE       1098
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT3,T4,T7

 LINE       1098
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT3,T4,T7

 LINE       1098
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT3,T4,T7

 LINE       1098
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT3,T4,T7

 LINE       1098
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT3,T4,T5
10CoveredT1,T2,T3
11CoveredT3,T4,T7

 LINE       1098
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT3,T4,T5
10CoveredT1,T2,T3
11CoveredT3,T4,T7

 LINE       1098
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT3,T4,T7

 LINE       1098
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT3,T4,T7

 LINE       1098
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT3,T4,T7

 LINE       1098
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT3,T4,T5
10CoveredT1,T2,T3
11CoveredT3,T4,T5

 LINE       1098
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT3,T4,T5
10CoveredT3,T4,T5
11CoveredT3,T4,T5

 LINE       1098
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT3,T4,T5
10CoveredT1,T2,T3
11CoveredT3,T4,T7

 LINE       1116
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T4,T7
110CoveredT3,T4,T7
111CoveredT27,T31,T32

 LINE       1119
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT3,T4,T7
111CoveredT1,T2,T3

 LINE       1122
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT3,T4,T7
111CoveredT1,T2,T3

 LINE       1124
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT3,T4,T7
111CoveredT1,T2,T3

 LINE       1126
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT3,T4,T7
111CoveredT1,T2,T3

 LINE       1128
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT3,T4,T7
111CoveredT1,T2,T3

 LINE       1130
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT3,T4,T7
111CoveredT1,T2,T3

 LINE       1133
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT3,T4,T7
111CoveredT1,T2,T3

 LINE       1136
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT3,T4,T7
111CoveredT1,T2,T3

 LINE       1138
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT3,T4,T7
111CoveredT1,T2,T3

 LINE       1140
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT3,T4,T7
111CoveredT1,T2,T3

 LINE       1142
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT3,T4,T7
111CoveredT1,T2,T3

 LINE       1147
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T4,T5
110CoveredT3,T4,T7
111CoveredT3,T4,T5

 LINE       1152
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT3,T4,T7
111CoveredT1,T2,T3

 LINE       1238
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

Branch Coverage for Module : aon_timer_reg_top
Line No.TotalCoveredPercent
Branches 31 31 100.00
TERNARY 1094 2 2 100.00
IF 70 3 3 100.00
CASE 1177 15 15 100.00
CASE 1241 11 11 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_reg_top.sv' or '../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 1094 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T13,T14,T15
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 1177 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T1,T2,T3
addr_hit[2] Covered T1,T2,T3
addr_hit[3] Covered T1,T2,T3
addr_hit[4] Covered T1,T2,T3
addr_hit[5] Covered T1,T2,T3
addr_hit[6] Covered T1,T2,T3
addr_hit[7] Covered T1,T2,T3
addr_hit[8] Covered T1,T2,T3
addr_hit[9] Covered T1,T2,T3
addr_hit[10] Covered T1,T2,T3
addr_hit[11] Covered T1,T2,T3
addr_hit[12] Covered T1,T2,T3
addr_hit[13] Covered T1,T2,T3
default Covered T1,T2,T3


LineNo. Expression -1-: 1241 case (1'b1)

Branches:
-1-StatusTests
addr_hit[1] Covered T1,T2,T3
addr_hit[2] Covered T1,T2,T3
addr_hit[3] Covered T1,T2,T3
addr_hit[4] Covered T1,T2,T3
addr_hit[5] Covered T1,T2,T3
addr_hit[7] Covered T1,T2,T3
addr_hit[8] Covered T1,T2,T3
addr_hit[9] Covered T1,T2,T3
addr_hit[10] Covered T1,T2,T3
addr_hit[13] Covered T1,T2,T3
default Covered T1,T2,T3


Assert Coverage for Module : aon_timer_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 820326753 358285 0 0
reAfterRv 820326753 358285 0 0
rePulse 820326753 77890 0 0
wePulse 820326753 280395 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 820326753 358285 0 0
T1 15346 18 0 0
T2 40425 19 0 0
T3 727808 13214 0 0
T4 326896 5611 0 0
T5 345820 346 0 0
T6 390873 295 0 0
T7 641241 12379 0 0
T8 141001 323 0 0
T9 4329 19 0 0
T10 119721 324 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 820326753 358285 0 0
T1 15346 18 0 0
T2 40425 19 0 0
T3 727808 13214 0 0
T4 326896 5611 0 0
T5 345820 346 0 0
T6 390873 295 0 0
T7 641241 12379 0 0
T8 141001 323 0 0
T9 4329 19 0 0
T10 119721 324 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 820326753 77890 0 0
T1 15346 1 0 0
T2 40425 1 0 0
T3 727808 2648 0 0
T4 326896 1152 0 0
T5 345820 27 0 0
T6 390873 29 0 0
T7 641241 2447 0 0
T8 141001 22 0 0
T9 4329 1 0 0
T10 119721 38 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 820326753 280395 0 0
T1 15346 17 0 0
T2 40425 18 0 0
T3 727808 10566 0 0
T4 326896 4459 0 0
T5 345820 319 0 0
T6 390873 266 0 0
T7 641241 9932 0 0
T8 141001 301 0 0
T9 4329 18 0 0
T10 119721 286 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%