Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	405169	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	5019040	1		T1	14		T2	16		T3	202

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1333127	1		T1	1		T2	1		T3	40
values[0x0]	1918999	1		T1	12		T2	8		T3	117
values[0x1]	2172083	1		T1	6		T2	13		T3	150

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	180384	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	5243825	1		T1	15		T2	19		T3	220

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21491	1		T6	10		T7	1		T8	297
valid_sources[0x01]	21994	1		T8	11		T10	1		T11	105
valid_sources[0x02]	20984	1		T8	20		T11	130		T12	1
valid_sources[0x03]	20195	1		T7	3		T8	18		T10	1
valid_sources[0x04]	20268	1		T7	1		T8	101		T10	1
valid_sources[0x05]	22199	1		T7	1		T8	109		T11	107
valid_sources[0x06]	21413	1		T8	77		T10	1		T11	325
valid_sources[0x07]	21917	1		T8	24		T10	1		T11	73
valid_sources[0x08]	21987	1		T8	123		T11	1		T12	5
valid_sources[0x09]	20613	1		T7	1		T8	170		T9	3
valid_sources[0x0a]	20540	1		T7	5		T8	404		T11	85
valid_sources[0x0b]	20283	1		T8	18		T11	209		T13	270
valid_sources[0x0c]	22233	1		T8	129		T11	666		T12	1
valid_sources[0x0d]	21452	1		T8	562		T10	1		T11	8
valid_sources[0x0e]	21207	1		T7	2		T8	129		T11	15
valid_sources[0x0f]	20706	1		T7	7		T8	88		T10	1
valid_sources[0x10]	21665	1		T7	1		T8	8		T11	169
valid_sources[0x11]	20816	1		T8	20		T10	2		T11	60
valid_sources[0x12]	21769	1		T7	2		T8	100		T10	1
valid_sources[0x13]	20787	1		T8	31		T11	17		T12	1
valid_sources[0x14]	22597	1		T8	18		T10	2		T11	109
valid_sources[0x15]	20098	1		T5	2		T8	70		T11	42
valid_sources[0x16]	20482	1		T7	3		T8	25		T10	1
valid_sources[0x17]	23039	1		T7	1		T8	112		T10	1
valid_sources[0x18]	21798	1		T7	2		T8	3		T10	2
valid_sources[0x19]	22093	1		T5	1		T7	2		T8	12
valid_sources[0x1a]	20091	1		T7	4		T8	87		T10	2
valid_sources[0x1b]	20963	1		T8	129		T10	3		T11	97
valid_sources[0x1c]	21555	1		T7	1		T8	186		T10	1
valid_sources[0x1d]	21536	1		T7	1		T8	75		T10	3
valid_sources[0x1e]	21110	1		T8	95		T10	3		T11	282
valid_sources[0x1f]	21468	1		T8	11		T10	1		T11	9
valid_sources[0x20]	20937	1		T8	260		T10	3		T11	253
valid_sources[0x21]	20977	1		T7	3		T8	141		T11	236
valid_sources[0x22]	21528	1		T7	1		T8	2		T10	3
valid_sources[0x23]	21737	1		T5	1		T7	1		T8	156
valid_sources[0x24]	21387	1		T8	42		T10	2		T11	68
valid_sources[0x25]	20840	1		T7	3		T8	165		T10	2
valid_sources[0x26]	22081	1		T3	307		T6	1		T7	1
valid_sources[0x27]	21835	1		T8	280		T11	177		T13	239
valid_sources[0x28]	20422	1		T8	1		T10	1		T11	315
valid_sources[0x29]	20300	1		T7	1		T8	5		T11	198
valid_sources[0x2a]	21168	1		T8	317		T10	1		T11	14
valid_sources[0x2b]	20111	1		T7	1		T8	8		T10	3
valid_sources[0x2c]	21044	1		T7	2		T8	128		T11	325
valid_sources[0x2d]	21334	1		T7	1		T8	401		T11	5
valid_sources[0x2e]	20669	1		T8	11		T10	1		T11	9
valid_sources[0x2f]	20379	1		T8	338		T10	3		T11	16
valid_sources[0x30]	21771	1		T7	1		T8	6		T10	3
valid_sources[0x31]	20812	1		T7	5		T8	416		T10	1
valid_sources[0x32]	21312	1		T7	1		T8	48		T11	143
valid_sources[0x33]	21605	1		T7	3		T8	14		T11	7
valid_sources[0x34]	21314	1		T7	2		T8	246		T10	1
valid_sources[0x35]	20857	1		T8	27		T11	321		T12	3
valid_sources[0x36]	21929	1		T8	243		T11	20		T18	1
valid_sources[0x37]	20730	1		T7	1		T8	293		T10	1
valid_sources[0x38]	20885	1		T7	3		T8	90		T10	2
valid_sources[0x39]	20836	1		T7	3		T8	34		T9	3
valid_sources[0x3a]	21088	1		T7	1		T8	9		T10	3
valid_sources[0x3b]	21401	1		T7	1		T8	2		T11	233
valid_sources[0x3c]	21942	1		T8	124		T10	2		T11	81
valid_sources[0x3d]	20558	1		T8	4		T10	2		T11	142
valid_sources[0x3e]	21597	1		T6	1		T7	4		T8	201
valid_sources[0x3f]	21779	1		T7	2		T8	230		T10	2
valid_sources[0x40]	20872	1		T8	43		T10	3		T11	39
valid_sources[0x41]	20496	1		T1	13		T7	3		T8	182
valid_sources[0x42]	20676	1		T7	1		T8	15		T11	17
valid_sources[0x43]	21811	1		T7	2		T8	162		T11	21
valid_sources[0x44]	20175	1		T8	57		T10	1		T11	120
valid_sources[0x45]	21569	1		T7	3		T8	17		T10	2
valid_sources[0x46]	21382	1		T7	1		T8	19		T11	20
valid_sources[0x47]	20747	1		T7	2		T8	78		T10	1
valid_sources[0x48]	20551	1		T7	4		T8	2		T11	339
valid_sources[0x49]	21106	1		T7	3		T8	368		T10	1
valid_sources[0x4a]	21483	1		T7	1		T8	190		T9	10
valid_sources[0x4b]	20759	1		T7	1		T8	371		T10	2
valid_sources[0x4c]	19679	1		T7	3		T8	35		T11	392
valid_sources[0x4d]	20311	1		T7	1		T8	84		T10	2
valid_sources[0x4e]	19872	1		T8	11		T11	53		T12	1
valid_sources[0x4f]	20937	1		T8	168		T11	125		T12	1
valid_sources[0x50]	20748	1		T5	1		T7	1		T8	82
valid_sources[0x51]	21003	1		T7	3		T8	352		T10	1
valid_sources[0x52]	20240	1		T7	1		T8	177		T11	21
valid_sources[0x53]	21361	1		T5	1		T7	2		T8	426
valid_sources[0x54]	21713	1		T7	2		T8	23		T10	1
valid_sources[0x55]	20946	1		T8	14		T10	3		T11	199
valid_sources[0x56]	21915	1		T7	2		T8	119		T10	3
valid_sources[0x57]	21912	1		T7	1		T8	128		T10	1
valid_sources[0x58]	21559	1		T5	1		T7	1		T8	255
valid_sources[0x59]	22394	1		T7	1		T8	103		T10	4
valid_sources[0x5a]	20668	1		T8	95		T11	117		T12	1
valid_sources[0x5b]	20613	1		T7	2		T8	371		T10	1
valid_sources[0x5c]	22324	1		T7	2		T8	46		T10	1
valid_sources[0x5d]	21044	1		T5	1		T7	2		T8	111
valid_sources[0x5e]	22335	1		T7	1		T8	501		T10	3
valid_sources[0x5f]	21674	1		T7	3		T8	61		T10	1
valid_sources[0x60]	20805	1		T7	1		T8	120		T10	1
valid_sources[0x61]	21721	1		T8	27		T10	2		T11	201
valid_sources[0x62]	20097	1		T7	3		T8	317		T11	103
valid_sources[0x63]	21756	1		T8	93		T11	411		T13	253
valid_sources[0x64]	21724	1		T7	4		T8	238		T10	1
valid_sources[0x65]	20937	1		T7	2		T8	258		T11	437
valid_sources[0x66]	21773	1		T7	3		T8	4		T11	216
valid_sources[0x67]	20792	1		T7	1		T8	73		T10	2
valid_sources[0x68]	21394	1		T7	2		T8	95		T10	2
valid_sources[0x69]	21263	1		T7	1		T8	61		T10	1
valid_sources[0x6a]	19729	1		T8	9		T10	2		T11	14
valid_sources[0x6b]	21317	1		T6	1		T8	319		T10	3
valid_sources[0x6c]	21361	1		T8	8		T10	1		T11	236
valid_sources[0x6d]	22215	1		T7	1		T8	137		T10	2
valid_sources[0x6e]	20645	1		T7	3		T8	362		T11	119
valid_sources[0x6f]	21599	1		T7	1		T8	85		T10	2
valid_sources[0x70]	21465	1		T1	1		T7	3		T8	8
valid_sources[0x71]	21631	1		T7	2		T8	78		T10	3
valid_sources[0x72]	21055	1		T7	2		T8	104		T10	1
valid_sources[0x73]	21497	1		T5	1		T7	1		T8	67
valid_sources[0x74]	22673	1		T2	22		T7	4		T8	239
valid_sources[0x75]	22238	1		T8	245		T10	1		T11	201
valid_sources[0x76]	20447	1		T7	1		T8	157		T10	2
valid_sources[0x77]	20402	1		T7	3		T8	90		T11	149
valid_sources[0x78]	20691	1		T8	14		T10	1		T11	20
valid_sources[0x79]	19606	1		T8	108		T10	1		T11	138
valid_sources[0x7a]	21213	1		T8	171		T10	2		T11	30
valid_sources[0x7b]	19988	1		T7	1		T8	11		T11	359
valid_sources[0x7c]	20890	1		T7	2		T8	334		T10	1
valid_sources[0x7d]	21076	1		T7	1		T8	63		T10	3
valid_sources[0x7e]	20404	1		T7	2		T8	180		T10	1
valid_sources[0x7f]	20165	1		T7	1		T8	268		T11	254
valid_sources[0x80]	20535	1		T8	2		T10	4		T11	231

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1251616

1

T1

1

T2

1

T3

22

values[0x0]

all_enables

biggest_size

1885161

1

T1

9

T2

8

T3

71

values[0x1]

all_enables

biggest_size

1882263

1

T1

4

T2

7

T3

109