Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	758349014	5891729	0	0
wdog_bark_thold_rd_A	758349014	153446	0	0
wdog_bite_thold_rd_A	758349014	134981	0	0
wdog_ctrl_rd_A	758349014	134569	0	0
wdog_regwen_rd_A	758349014	154547	0	0
wkup_ctrl_rd_A	758349014	134245	0	0
wkup_thold_hi_rd_A	758349014	154617	0	0
wkup_thold_lo_rd_A	758349014	133138	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758349014	5891729	0	0
T8	103211	38298	0	0
T9	23456	0	0	0
T10	130394	0	0	0
T11	191578	41208	0	0
T12	308051	0	0	0
T13	311236	71389	0	0
T14	144896	0	0	0
T18	15013	0	0	0
T19	208398	0	0	0
T27	0	187473	0	0
T28	0	59652	0	0
T29	0	185138	0	0
T30	0	172150	0	0
T31	0	164519	0	0
T32	0	142545	0	0
T33	0	143666	0	0
T34	12931	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758349014	153446	0	0
T11	191578	4515	0	0
T12	308051	0	0	0
T13	311236	6819	0	0
T14	144896	0	0	0
T18	15013	0	0	0
T19	208398	0	0	0
T27	827787	18109	0	0
T28	171987	0	0	0
T32	0	15139	0	0
T34	12931	0	0	0
T87	0	6493	0	0
T88	0	16947	0	0
T89	0	5683	0	0
T90	0	4030	0	0
T91	0	3679	0	0
T92	0	8935	0	0
T93	116566	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758349014	134981	0	0
T11	191578	3885	0	0
T12	308051	0	0	0
T13	311236	6181	0	0
T14	144896	0	0	0
T18	15013	0	0	0
T19	208398	0	0	0
T27	827787	15515	0	0
T28	171987	0	0	0
T32	0	12993	0	0
T34	12931	0	0	0
T87	0	5588	0	0
T88	0	14916	0	0
T89	0	5051	0	0
T90	0	3589	0	0
T91	0	3194	0	0
T92	0	7898	0	0
T93	116566	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758349014	134569	0	0
T11	191578	3880	0	0
T12	308051	0	0	0
T13	311236	6342	0	0
T14	144896	0	0	0
T18	15013	0	0	0
T19	208398	0	0	0
T27	827787	15586	0	0
T28	171987	0	0	0
T32	0	13241	0	0
T34	12931	0	0	0
T87	0	5778	0	0
T88	0	14814	0	0
T89	0	4675	0	0
T90	0	3706	0	0
T91	0	3269	0	0
T92	0	7615	0	0
T93	116566	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758349014	154547	0	0
T11	191578	4412	0	0
T12	308051	0	0	0
T13	311236	6810	0	0
T14	144896	0	0	0
T18	15013	0	0	0
T19	208398	0	0	0
T27	827787	18088	0	0
T28	171987	0	0	0
T32	0	14599	0	0
T34	12931	0	0	0
T87	0	6801	0	0
T88	0	17072	0	0
T89	0	5905	0	0
T90	0	4176	0	0
T91	0	3831	0	0
T92	0	8817	0	0
T93	116566	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758349014	134245	0	0
T11	191578	3763	0	0
T12	308051	0	0	0
T13	311236	5929	0	0
T14	144896	0	0	0
T18	15013	0	0	0
T19	208398	0	0	0
T27	827787	15322	0	0
T28	171987	0	0	0
T32	0	13202	0	0
T34	12931	0	0	0
T87	0	5804	0	0
T88	0	14256	0	0
T89	0	4915	0	0
T90	0	3560	0	0
T91	0	3117	0	0
T92	0	7829	0	0
T93	116566	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758349014	154617	0	0
T11	191578	4621	0	0
T12	308051	0	0	0
T13	311236	7079	0	0
T14	144896	0	0	0
T18	15013	0	0	0
T19	208398	0	0	0
T27	827787	17768	0	0
T28	171987	0	0	0
T32	0	14672	0	0
T34	12931	0	0	0
T87	0	6675	0	0
T88	0	17168	0	0
T89	0	5620	0	0
T90	0	3960	0	0
T91	0	3566	0	0
T92	0	9171	0	0
T93	116566	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758349014	133138	0	0
T11	191578	3823	0	0
T12	308051	0	0	0
T13	311236	6096	0	0
T14	144896	0	0	0
T18	15013	0	0	0
T19	208398	0	0	0
T27	827787	15598	0	0
T28	171987	0	0	0
T32	0	12608	0	0
T34	12931	0	0	0
T87	0	5898	0	0
T88	0	15164	0	0
T89	0	4774	0	0
T90	0	3448	0	0
T91	0	3250	0	0
T92	0	7758	0	0
T93	116566	0	0	0