Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	323171	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	3916627	1		T1	14		T2	12		T3	15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1042771	1		T1	1		T2	1		T3	1
values[0x0]	1498509	1		T1	8		T2	10		T3	12
values[0x1]	1698518	1		T1	13		T2	9		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	144221	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4095577	1		T1	15		T2	12		T3	15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16776	1		T8	1		T9	372		T14	463
valid_sources[0x01]	15549	1		T2	1		T8	3		T9	461
valid_sources[0x02]	16203	1		T8	2		T9	423		T30	3
valid_sources[0x03]	17716	1		T8	1		T9	393		T30	2
valid_sources[0x04]	16507	1		T2	1		T8	4		T9	390
valid_sources[0x05]	16893	1		T8	1		T9	369		T47	1
valid_sources[0x06]	16043	1		T8	1		T9	398		T14	542
valid_sources[0x07]	17230	1		T8	2		T9	416		T14	374
valid_sources[0x08]	16182	1		T6	1		T8	1		T9	417
valid_sources[0x09]	16923	1		T6	1		T9	410		T30	3
valid_sources[0x0a]	17291	1		T9	421		T30	1		T14	415
valid_sources[0x0b]	16894	1		T2	1		T9	404		T14	540
valid_sources[0x0c]	16786	1		T9	395		T30	3		T46	1
valid_sources[0x0d]	16908	1		T9	426		T30	1		T14	398
valid_sources[0x0e]	17554	1		T3	5		T8	1		T9	375
valid_sources[0x0f]	16022	1		T9	383		T30	1		T14	724
valid_sources[0x10]	16939	1		T8	1		T9	383		T30	1
valid_sources[0x11]	17599	1		T9	415		T30	1		T14	606
valid_sources[0x12]	17353	1		T8	2		T9	427		T30	1
valid_sources[0x13]	17812	1		T8	1		T9	446		T30	3
valid_sources[0x14]	15293	1		T8	1		T9	380		T14	538
valid_sources[0x15]	16781	1		T8	1		T9	451		T30	6
valid_sources[0x16]	17134	1		T9	419		T30	1		T14	499
valid_sources[0x17]	16396	1		T8	2		T9	391		T44	1
valid_sources[0x18]	16271	1		T9	406		T14	451		T15	488
valid_sources[0x19]	15953	1		T8	2		T9	427		T14	530
valid_sources[0x1a]	17072	1		T8	1		T9	437		T30	1
valid_sources[0x1b]	17322	1		T8	4		T9	385		T30	1
valid_sources[0x1c]	17443	1		T6	1		T9	400		T14	793
valid_sources[0x1d]	15864	1		T9	367		T30	1		T47	1
valid_sources[0x1e]	16947	1		T8	3		T9	390		T30	1
valid_sources[0x1f]	16106	1		T8	5		T9	381		T30	2
valid_sources[0x20]	18014	1		T8	1		T9	409		T14	549
valid_sources[0x21]	16831	1		T8	2		T9	417		T30	1
valid_sources[0x22]	16994	1		T8	2		T9	378		T30	1
valid_sources[0x23]	16797	1		T5	1		T9	432		T14	737
valid_sources[0x24]	17024	1		T9	398		T30	1		T14	699
valid_sources[0x25]	17158	1		T1	2		T8	1		T9	385
valid_sources[0x26]	17182	1		T8	5		T9	398		T30	1
valid_sources[0x27]	17014	1		T2	1		T8	1		T9	365
valid_sources[0x28]	16574	1		T1	2		T8	2		T9	414
valid_sources[0x29]	17231	1		T8	2		T9	429		T30	2
valid_sources[0x2a]	16419	1		T8	1		T9	414		T30	4
valid_sources[0x2b]	17718	1		T8	1		T9	418		T30	3
valid_sources[0x2c]	16145	1		T8	2		T9	380		T14	483
valid_sources[0x2d]	16075	1		T9	411		T30	2		T14	494
valid_sources[0x2e]	15135	1		T8	2		T9	417		T30	2
valid_sources[0x2f]	17037	1		T8	1		T9	389		T30	2
valid_sources[0x30]	17211	1		T8	4		T9	378		T14	500
valid_sources[0x31]	15462	1		T8	1		T9	426		T30	1
valid_sources[0x32]	17564	1		T1	1		T2	1		T9	409
valid_sources[0x33]	15424	1		T9	369		T30	2		T14	383
valid_sources[0x34]	17658	1		T1	1		T8	1		T9	463
valid_sources[0x35]	18028	1		T9	428		T30	1		T46	1
valid_sources[0x36]	17420	1		T8	3		T9	385		T14	644
valid_sources[0x37]	17402	1		T8	1		T9	385		T30	1
valid_sources[0x38]	16370	1		T9	450		T14	652		T15	411
valid_sources[0x39]	15324	1		T9	409		T14	476		T15	447
valid_sources[0x3a]	17176	1		T5	1		T9	421		T30	2
valid_sources[0x3b]	16264	1		T9	410		T14	493		T200	1
valid_sources[0x3c]	16274	1		T1	1		T8	2		T9	403
valid_sources[0x3d]	15842	1		T9	416		T30	3		T14	626
valid_sources[0x3e]	17762	1		T2	1		T5	1		T8	4
valid_sources[0x3f]	16280	1		T5	2		T9	399		T30	1
valid_sources[0x40]	16939	1		T9	371		T30	1		T14	624
valid_sources[0x41]	16835	1		T8	1		T9	402		T30	3
valid_sources[0x42]	17231	1		T9	375		T14	401		T201	3
valid_sources[0x43]	14958	1		T8	1		T9	372		T30	1
valid_sources[0x44]	15851	1		T9	386		T14	511		T15	522
valid_sources[0x45]	15658	1		T5	2		T9	409		T14	640
valid_sources[0x46]	17046	1		T9	384		T13	1		T30	2
valid_sources[0x47]	15751	1		T9	406		T30	2		T14	539
valid_sources[0x48]	17332	1		T5	1		T9	413		T13	1
valid_sources[0x49]	16314	1		T8	1		T9	429		T30	1
valid_sources[0x4a]	15389	1		T9	470		T30	1		T14	553
valid_sources[0x4b]	17594	1		T2	1		T9	413		T14	572
valid_sources[0x4c]	15759	1		T8	2		T9	403		T14	731
valid_sources[0x4d]	17722	1		T8	1		T9	403		T30	2
valid_sources[0x4e]	16585	1		T8	1		T9	380		T30	3
valid_sources[0x4f]	17151	1		T9	440		T14	556		T15	495
valid_sources[0x50]	17036	1		T6	1		T8	1		T9	384
valid_sources[0x51]	17629	1		T2	1		T8	2		T9	419
valid_sources[0x52]	15799	1		T6	1		T8	1		T9	405
valid_sources[0x53]	18314	1		T8	1		T9	402		T14	831
valid_sources[0x54]	16396	1		T8	2		T9	415		T30	1
valid_sources[0x55]	16872	1		T7	345		T9	424		T14	538
valid_sources[0x56]	15267	1		T1	3		T8	1		T9	409
valid_sources[0x57]	15690	1		T8	2		T9	418		T30	3
valid_sources[0x58]	16145	1		T8	1		T9	421		T13	1
valid_sources[0x59]	16083	1		T8	4		T9	392		T30	1
valid_sources[0x5a]	16008	1		T8	1		T9	393		T30	3
valid_sources[0x5b]	17253	1		T8	2		T9	411		T14	657
valid_sources[0x5c]	15709	1		T1	1		T8	1		T9	412
valid_sources[0x5d]	16959	1		T8	2		T9	405		T30	2
valid_sources[0x5e]	16479	1		T8	2		T9	416		T30	1
valid_sources[0x5f]	18029	1		T9	369		T14	588		T15	492
valid_sources[0x60]	15749	1		T2	1		T6	2		T9	397
valid_sources[0x61]	17683	1		T9	404		T30	4		T14	662
valid_sources[0x62]	16459	1		T8	1		T9	380		T30	1
valid_sources[0x63]	15559	1		T8	1		T9	372		T46	2
valid_sources[0x64]	16596	1		T8	1		T9	390		T14	510
valid_sources[0x65]	17385	1		T8	2		T9	419		T13	1
valid_sources[0x66]	16567	1		T8	1		T9	385		T30	4
valid_sources[0x67]	16856	1		T9	387		T30	2		T46	1
valid_sources[0x68]	16614	1		T1	4		T9	406		T14	517
valid_sources[0x69]	16259	1		T8	1		T9	433		T30	2
valid_sources[0x6a]	16588	1		T8	2		T9	391		T13	1
valid_sources[0x6b]	16147	1		T9	408		T30	3		T44	5
valid_sources[0x6c]	17499	1		T9	376		T30	2		T47	1
valid_sources[0x6d]	16997	1		T8	1		T9	360		T14	521
valid_sources[0x6e]	16963	1		T9	383		T46	1		T14	551
valid_sources[0x6f]	17091	1		T5	3		T8	1		T9	430
valid_sources[0x70]	16795	1		T6	1		T8	3		T9	439
valid_sources[0x71]	16883	1		T8	3		T9	405		T14	623
valid_sources[0x72]	15873	1		T8	1		T9	384		T46	3
valid_sources[0x73]	15563	1		T8	2		T9	382		T13	1
valid_sources[0x74]	14657	1		T8	2		T9	358		T14	623
valid_sources[0x75]	15403	1		T9	409		T14	525		T189	1
valid_sources[0x76]	16019	1		T8	1		T9	410		T30	1
valid_sources[0x77]	17096	1		T8	2		T9	404		T30	2
valid_sources[0x78]	16787	1		T8	2		T9	381		T14	619
valid_sources[0x79]	17946	1		T8	1		T9	386		T14	548
valid_sources[0x7a]	16955	1		T9	423		T30	1		T47	1
valid_sources[0x7b]	16453	1		T8	1		T9	429		T12	20
valid_sources[0x7c]	15449	1		T8	1		T9	405		T44	1
valid_sources[0x7d]	17311	1		T9	352		T30	4		T14	795
valid_sources[0x7e]	17343	1		T8	2		T9	381		T30	1
valid_sources[0x7f]	16487	1		T1	1		T8	1		T9	392
valid_sources[0x80]	17128	1		T8	1		T9	342		T14	551

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

976875

1

T3

1

T5

1

T6

1

values[0x0]

all_enables

biggest_size

1471256

1

T1

7

T2

6

T3

7

values[0x1]

all_enables

biggest_size

1468496

1

T1

7

T2

6

T3

7