Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	733232260	4663573	0	0
wdog_bark_thold_rd_A	733232260	85925	0	0
wdog_bite_thold_rd_A	733232260	76122	0	0
wdog_ctrl_rd_A	733232260	76247	0	0
wdog_regwen_rd_A	733232260	84794	0	0
wkup_ctrl_rd_A	733232260	75791	0	0
wkup_thold_hi_rd_A	733232260	86485	0	0
wkup_thold_lo_rd_A	733232260	75479	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733232260	4663573	0	0
T9	429242	116776	0	0
T10	211907	0	0	0
T11	514798	0	0	0
T12	809473	0	0	0
T13	54401	0	0	0
T14	0	160738	0	0
T15	0	140993	0	0
T30	193228	0	0	0
T37	0	219362	0	0
T38	0	97852	0	0
T39	0	141862	0	0
T40	0	101733	0	0
T41	0	51983	0	0
T42	0	33885	0	0
T43	0	38867	0	0
T44	102749	0	0	0
T45	34129	0	0	0
T46	49940	0	0	0
T47	55967	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733232260	85925	0	0
T61	0	17738	0	0
T62	0	8357	0	0
T94	998611	2261	0	0
T99	366692	8343	0	0
T100	289181	6028	0	0
T101	0	830	0	0
T102	0	1988	0	0
T103	0	29655	0	0
T104	0	2936	0	0
T105	0	6934	0	0
T106	51764	0	0	0
T107	761922	0	0	0
T108	3658	0	0	0
T109	793658	0	0	0
T110	151508	0	0	0
T111	253589	0	0	0
T112	111041	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733232260	76122	0	0
T61	0	15169	0	0
T62	0	7615	0	0
T94	998611	1808	0	0
T99	366692	7215	0	0
T100	289181	5448	0	0
T101	0	858	0	0
T102	0	1770	0	0
T103	0	26606	0	0
T104	0	2563	0	0
T105	0	6232	0	0
T106	51764	0	0	0
T107	761922	0	0	0
T108	3658	0	0	0
T109	793658	0	0	0
T110	151508	0	0	0
T111	253589	0	0	0
T112	111041	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733232260	76247	0	0
T61	0	15198	0	0
T62	0	7448	0	0
T94	998611	1783	0	0
T99	366692	7687	0	0
T100	289181	5643	0	0
T101	0	725	0	0
T102	0	1706	0	0
T103	0	26257	0	0
T104	0	2595	0	0
T105	0	6295	0	0
T106	51764	0	0	0
T107	761922	0	0	0
T108	3658	0	0	0
T109	793658	0	0	0
T110	151508	0	0	0
T111	253589	0	0	0
T112	111041	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733232260	84794	0	0
T61	0	16962	0	0
T62	0	8599	0	0
T94	998611	2038	0	0
T99	366692	8013	0	0
T100	289181	6299	0	0
T101	0	827	0	0
T102	0	1991	0	0
T103	0	29158	0	0
T104	0	2771	0	0
T105	0	7153	0	0
T106	51764	0	0	0
T107	761922	0	0	0
T108	3658	0	0	0
T109	793658	0	0	0
T110	151508	0	0	0
T111	253589	0	0	0
T112	111041	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733232260	75791	0	0
T61	0	14818	0	0
T62	0	7759	0	0
T94	998611	1853	0	0
T99	366692	7411	0	0
T100	289181	5351	0	0
T101	0	889	0	0
T102	0	1626	0	0
T103	0	25869	0	0
T104	0	2774	0	0
T105	0	6413	0	0
T106	51764	0	0	0
T107	761922	0	0	0
T108	3658	0	0	0
T109	793658	0	0	0
T110	151508	0	0	0
T111	253589	0	0	0
T112	111041	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733232260	86485	0	0
T61	0	17125	0	0
T62	0	8367	0	0
T94	998611	2026	0	0
T99	366692	8446	0	0
T100	289181	6032	0	0
T101	0	881	0	0
T102	0	2175	0	0
T103	0	30319	0	0
T104	0	3122	0	0
T105	0	7169	0	0
T106	51764	0	0	0
T107	761922	0	0	0
T108	3658	0	0	0
T109	793658	0	0	0
T110	151508	0	0	0
T111	253589	0	0	0
T112	111041	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733232260	75479	0	0
T61	0	15070	0	0
T62	0	7686	0	0
T94	998611	1990	0	0
T99	366692	7519	0	0
T100	289181	5302	0	0
T101	0	808	0	0
T102	0	1697	0	0
T103	0	25949	0	0
T104	0	2612	0	0
T105	0	6031	0	0
T106	51764	0	0	0
T107	761922	0	0	0
T108	3658	0	0	0
T109	793658	0	0	0
T110	151508	0	0	0
T111	253589	0	0	0
T112	111041	0	0	0