Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	418387	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	5184928	1		T1	12		T2	71383		T3	101151

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1378211	1		T1	1		T2	18802		T3	26915
values[0x0]	1979168	1		T1	8		T2	27282		T3	38440
values[0x1]	2245936	1		T1	11		T2	31096		T3	44175

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	185703	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	5417612	1		T1	14		T2	74650		T3	105994

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21047	1		T2	261		T3	381		T4	4
valid_sources[0x01]	23122	1		T2	275		T3	616		T5	2
valid_sources[0x02]	21075	1		T2	325		T4	1		T7	312
valid_sources[0x03]	23760	1		T2	325		T3	1149		T4	1
valid_sources[0x04]	21691	1		T2	298		T3	308		T6	1
valid_sources[0x05]	23027	1		T2	269		T3	302		T4	2
valid_sources[0x06]	20324	1		T2	286		T3	331		T7	316
valid_sources[0x07]	23217	1		T2	290		T3	368		T4	4
valid_sources[0x08]	22459	1		T2	291		T3	245		T4	3
valid_sources[0x09]	20846	1		T2	285		T3	203		T7	290
valid_sources[0x0a]	22182	1		T2	320		T3	232		T4	2
valid_sources[0x0b]	21707	1		T2	279		T3	422		T4	1
valid_sources[0x0c]	22119	1		T2	293		T3	245		T7	275
valid_sources[0x0d]	21071	1		T2	292		T3	353		T4	3
valid_sources[0x0e]	22623	1		T2	344		T3	55		T4	3
valid_sources[0x0f]	22565	1		T2	260		T3	399		T4	3
valid_sources[0x10]	24143	1		T2	285		T3	1282		T7	323
valid_sources[0x11]	22827	1		T2	312		T3	171		T7	287
valid_sources[0x12]	20612	1		T2	275		T3	152		T7	285
valid_sources[0x13]	21011	1		T2	312		T3	264		T4	1
valid_sources[0x14]	21882	1		T2	328		T3	349		T7	311
valid_sources[0x15]	22321	1		T2	284		T3	355		T5	1
valid_sources[0x16]	23384	1		T2	302		T3	885		T4	4
valid_sources[0x17]	19889	1		T1	2		T2	322		T3	194
valid_sources[0x18]	22169	1		T2	264		T3	508		T5	1
valid_sources[0x19]	20878	1		T2	325		T3	589		T4	1
valid_sources[0x1a]	20535	1		T2	317		T3	224		T5	2
valid_sources[0x1b]	23989	1		T2	311		T3	319		T4	4
valid_sources[0x1c]	21611	1		T2	272		T3	309		T4	4
valid_sources[0x1d]	21736	1		T2	321		T3	240		T4	1
valid_sources[0x1e]	20956	1		T2	264		T3	432		T4	3
valid_sources[0x1f]	21389	1		T2	288		T3	361		T7	319
valid_sources[0x20]	21807	1		T2	261		T3	136		T7	303
valid_sources[0x21]	22307	1		T2	268		T3	307		T4	3
valid_sources[0x22]	21212	1		T2	317		T3	496		T7	299
valid_sources[0x23]	22669	1		T2	312		T3	285		T4	4
valid_sources[0x24]	20618	1		T2	288		T3	156		T4	2
valid_sources[0x25]	20604	1		T2	314		T3	277		T5	2
valid_sources[0x26]	22613	1		T2	289		T3	437		T4	8
valid_sources[0x27]	21436	1		T2	262		T3	283		T4	3
valid_sources[0x28]	21095	1		T1	2		T2	325		T3	142
valid_sources[0x29]	21649	1		T2	324		T3	145		T4	1
valid_sources[0x2a]	20510	1		T2	303		T3	122		T4	1
valid_sources[0x2b]	23091	1		T2	319		T3	533		T7	310
valid_sources[0x2c]	21652	1		T2	294		T3	1207		T4	2
valid_sources[0x2d]	21383	1		T2	304		T3	193		T4	2
valid_sources[0x2e]	21056	1		T2	297		T3	412		T5	1
valid_sources[0x2f]	19967	1		T2	308		T3	162		T4	1
valid_sources[0x30]	21199	1		T2	327		T3	462		T7	297
valid_sources[0x31]	21626	1		T2	291		T3	5		T4	4
valid_sources[0x32]	22612	1		T2	265		T3	584		T4	1
valid_sources[0x33]	23621	1		T2	311		T3	177		T4	11
valid_sources[0x34]	21144	1		T2	272		T3	532		T4	4
valid_sources[0x35]	21622	1		T2	319		T3	546		T7	281
valid_sources[0x36]	19271	1		T2	281		T3	189		T5	7
valid_sources[0x37]	22421	1		T2	274		T3	381		T7	311
valid_sources[0x38]	22708	1		T2	306		T3	540		T4	1
valid_sources[0x39]	22235	1		T2	291		T3	767		T5	2
valid_sources[0x3a]	21536	1		T2	301		T3	191		T4	3
valid_sources[0x3b]	21423	1		T2	290		T3	136		T4	3
valid_sources[0x3c]	21069	1		T2	310		T3	290		T7	296
valid_sources[0x3d]	23155	1		T2	278		T3	565		T5	2
valid_sources[0x3e]	20294	1		T2	316		T3	375		T5	2
valid_sources[0x3f]	21922	1		T2	251		T3	1332		T7	275
valid_sources[0x40]	21910	1		T2	318		T3	918		T4	1
valid_sources[0x41]	21032	1		T2	298		T3	107		T4	2
valid_sources[0x42]	21433	1		T2	306		T3	282		T6	1
valid_sources[0x43]	22740	1		T1	3		T2	313		T3	1159
valid_sources[0x44]	21519	1		T2	290		T3	631		T7	301
valid_sources[0x45]	22892	1		T2	298		T3	490		T5	5
valid_sources[0x46]	21437	1		T2	323		T3	377		T4	1
valid_sources[0x47]	21656	1		T2	349		T3	416		T7	283
valid_sources[0x48]	23539	1		T2	316		T3	713		T4	5
valid_sources[0x49]	19955	1		T2	337		T3	408		T7	281
valid_sources[0x4a]	22341	1		T2	340		T5	3		T7	285
valid_sources[0x4b]	22470	1		T2	300		T3	384		T4	6
valid_sources[0x4c]	22992	1		T1	3		T2	382		T3	439
valid_sources[0x4d]	21701	1		T2	280		T3	41		T5	3
valid_sources[0x4e]	21641	1		T2	253		T3	343		T7	342
valid_sources[0x4f]	21843	1		T2	354		T3	496		T7	323
valid_sources[0x50]	20314	1		T2	288		T3	236		T5	5
valid_sources[0x51]	21816	1		T2	286		T3	366		T4	1
valid_sources[0x52]	21301	1		T2	278		T3	182		T7	322
valid_sources[0x53]	22145	1		T2	314		T3	260		T4	3
valid_sources[0x54]	22965	1		T2	289		T3	787		T5	5
valid_sources[0x55]	22829	1		T2	313		T3	659		T4	4
valid_sources[0x56]	23827	1		T2	326		T3	969		T7	302
valid_sources[0x57]	22447	1		T2	287		T3	292		T4	5
valid_sources[0x58]	20762	1		T2	271		T3	11		T5	2
valid_sources[0x59]	22835	1		T2	323		T3	366		T7	277
valid_sources[0x5a]	21852	1		T1	1		T2	319		T3	372
valid_sources[0x5b]	22419	1		T2	286		T3	334		T4	1
valid_sources[0x5c]	21925	1		T2	283		T3	94		T7	333
valid_sources[0x5d]	21997	1		T2	277		T3	338		T4	3
valid_sources[0x5e]	21700	1		T2	299		T3	314		T4	3
valid_sources[0x5f]	22772	1		T2	304		T3	690		T7	305
valid_sources[0x60]	21068	1		T2	228		T3	629		T5	8
valid_sources[0x61]	22085	1		T2	310		T3	457		T5	2
valid_sources[0x62]	20731	1		T2	305		T3	69		T4	3
valid_sources[0x63]	20223	1		T2	328		T3	137		T5	7
valid_sources[0x64]	21554	1		T2	328		T3	546		T5	2
valid_sources[0x65]	23527	1		T2	319		T3	188		T7	319
valid_sources[0x66]	22129	1		T2	328		T3	374		T4	4
valid_sources[0x67]	21947	1		T2	299		T3	606		T5	1
valid_sources[0x68]	21770	1		T2	301		T3	255		T5	1
valid_sources[0x69]	24528	1		T2	317		T3	1513		T4	1
valid_sources[0x6a]	21652	1		T2	306		T3	394		T4	3
valid_sources[0x6b]	21485	1		T2	280		T3	391		T7	327
valid_sources[0x6c]	21116	1		T2	284		T3	455		T4	3
valid_sources[0x6d]	21996	1		T2	340		T3	699		T4	1
valid_sources[0x6e]	22003	1		T2	316		T3	497		T7	286
valid_sources[0x6f]	19634	1		T2	310		T3	220		T4	2
valid_sources[0x70]	21695	1		T2	307		T3	434		T4	2
valid_sources[0x71]	22197	1		T2	268		T3	529		T7	319
valid_sources[0x72]	22213	1		T2	266		T3	490		T5	5
valid_sources[0x73]	22215	1		T2	267		T3	388		T4	3
valid_sources[0x74]	20939	1		T2	305		T3	625		T5	7
valid_sources[0x75]	23033	1		T2	320		T3	330		T7	324
valid_sources[0x76]	22340	1		T2	352		T3	169		T4	1
valid_sources[0x77]	21420	1		T2	298		T3	112		T5	3
valid_sources[0x78]	23550	1		T2	285		T3	542		T5	3
valid_sources[0x79]	21081	1		T2	309		T3	274		T5	3
valid_sources[0x7a]	22609	1		T2	288		T3	258		T5	4
valid_sources[0x7b]	21853	1		T2	249		T3	383		T4	3
valid_sources[0x7c]	25560	1		T2	268		T3	887		T6	1
valid_sources[0x7d]	21418	1		T2	278		T3	132		T7	314
valid_sources[0x7e]	21213	1		T2	303		T3	262		T7	321
valid_sources[0x7f]	21751	1		T2	308		T3	312		T7	340
valid_sources[0x80]	21141	1		T2	297		T3	705		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1293546

1

T2

17705

T3

25361

T4

17

values[0x0]

all_enables

biggest_size

1944777

1

T1

5

T2

26830

T3

37819

values[0x1]

all_enables

biggest_size

1946605

1

T1

7

T2

26848

T3

37971