Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
92.86 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_cgs_wrap[aon_timer_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_cgs_wrap[aon_timer_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_cgs_wrap[aon_timer_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 1 13 100.00


Variables for Group Instance tl_intg_err_cgs_wrap[aon_timer_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_is_mem 2 1 1 50.00 100 0 0 2
cp_num_cmd_err_bits 4 0 4 100.00 100 1 1 0
cp_num_data_err_bits 4 0 4 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0


Summary for Variable cp_is_mem

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_is_mem

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
[auto[1]] 0 0 - - - - - -
auto[0] 16217143 0 T1 20 T2 228516 T3 332374



Summary for Variable cp_num_cmd_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_num_cmd_err_bits

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 16216955 1 T1 20 T2 228516 T3 332374
values[1] 16 1 T187 2 T188 1 T189 1
values[2] 4 1 T190 2 T191 2 - -
values[3] 93 1 T32 9 T33 2 T34 2



Summary for Variable cp_num_data_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_num_data_err_bits

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 16216932 1 T1 20 T2 228516 T3 332374
values[1] 24 1 T33 1 T34 1 T192 1
values[2] 10 1 T33 2 T34 2 T189 1
values[3] 104 1 T32 8 T33 1 T34 5



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 16216843 1 T1 20 T2 228516 T3 332374
auto[TlIntgErrCmd] 89 1 T32 8 T33 3 T192 1
auto[TlIntgErrData] 112 1 T32 7 T33 6 T34 6
auto[TlIntgErrBoth] 99 1 T32 5 T33 1 T34 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%