Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	682268804	6148449	0	0
wdog_bark_thold_rd_A	682268804	118143	0	0
wdog_bite_thold_rd_A	682268804	104174	0	0
wdog_ctrl_rd_A	682268804	104111	0	0
wdog_regwen_rd_A	682268804	118972	0	0
wkup_ctrl_rd_A	682268804	102704	0	0
wkup_thold_hi_rd_A	682268804	117257	0	0
wkup_thold_lo_rd_A	682268804	103972	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682268804	6148449	0	0
T2	318637	86153	0	0
T3	466510	127279	0	0
T4	239876	0	0	0
T5	180199	0	0	0
T6	4366	0	0	0
T7	517697	90614	0	0
T8	273732	73769	0	0
T9	312149	0	0	0
T10	638050	235068	0	0
T14	365872	0	0	0
T27	0	113499	0	0
T36	0	64728	0	0
T37	0	130100	0	0
T38	0	189293	0	0
T39	0	226369	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682268804	118143	0	0
T7	517697	4649	0	0
T8	273732	0	0	0
T9	312149	0	0	0
T10	638050	0	0	0
T14	365872	0	0	0
T26	314057	0	0	0
T27	405848	0	0	0
T31	27048	0	0	0
T36	0	6484	0	0
T37	0	13105	0	0
T40	351003	0	0	0
T45	0	6020	0	0
T46	0	2451	0	0
T49	0	7842	0	0
T73	274056	0	0	0
T78	0	27245	0	0
T79	0	10129	0	0
T80	0	10182	0	0
T81	0	3134	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682268804	104174	0	0
T7	517697	4095	0	0
T8	273732	0	0	0
T9	312149	0	0	0
T10	638050	0	0	0
T14	365872	0	0	0
T26	314057	0	0	0
T27	405848	0	0	0
T31	27048	0	0	0
T36	0	5969	0	0
T37	0	11986	0	0
T40	351003	0	0	0
T45	0	5046	0	0
T46	0	2421	0	0
T49	0	6666	0	0
T73	274056	0	0	0
T78	0	24445	0	0
T79	0	8620	0	0
T80	0	8829	0	0
T81	0	2967	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682268804	104111	0	0
T7	517697	3829	0	0
T8	273732	0	0	0
T9	312149	0	0	0
T10	638050	0	0	0
T14	365872	0	0	0
T26	314057	0	0	0
T27	405848	0	0	0
T31	27048	0	0	0
T36	0	5749	0	0
T37	0	11627	0	0
T40	351003	0	0	0
T45	0	5273	0	0
T46	0	2296	0	0
T49	0	6633	0	0
T73	274056	0	0	0
T78	0	23689	0	0
T79	0	8977	0	0
T80	0	8290	0	0
T81	0	2940	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682268804	118972	0	0
T7	517697	4699	0	0
T8	273732	0	0	0
T9	312149	0	0	0
T10	638050	0	0	0
T14	365872	0	0	0
T26	314057	0	0	0
T27	405848	0	0	0
T31	27048	0	0	0
T36	0	6642	0	0
T37	0	13463	0	0
T40	351003	0	0	0
T45	0	5894	0	0
T46	0	2690	0	0
T49	0	7622	0	0
T73	274056	0	0	0
T78	0	26853	0	0
T79	0	10205	0	0
T80	0	9552	0	0
T81	0	3217	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682268804	102704	0	0
T7	517697	4178	0	0
T8	273732	0	0	0
T9	312149	0	0	0
T10	638050	0	0	0
T14	365872	0	0	0
T26	314057	0	0	0
T27	405848	0	0	0
T31	27048	0	0	0
T36	0	5520	0	0
T37	0	11768	0	0
T40	351003	0	0	0
T45	0	4674	0	0
T46	0	2303	0	0
T49	0	6818	0	0
T73	274056	0	0	0
T78	0	23388	0	0
T79	0	8687	0	0
T80	0	8545	0	0
T81	0	2740	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682268804	117257	0	0
T7	517697	4634	0	0
T8	273732	0	0	0
T9	312149	0	0	0
T10	638050	0	0	0
T14	365872	0	0	0
T26	314057	0	0	0
T27	405848	0	0	0
T31	27048	0	0	0
T36	0	6877	0	0
T37	0	12939	0	0
T40	351003	0	0	0
T45	0	5698	0	0
T46	0	2767	0	0
T49	0	7594	0	0
T73	274056	0	0	0
T78	0	26880	0	0
T79	0	9893	0	0
T80	0	10034	0	0
T81	0	3169	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	682268804	103972	0	0
T7	517697	3991	0	0
T8	273732	0	0	0
T9	312149	0	0	0
T10	638050	0	0	0
T14	365872	0	0	0
T26	314057	0	0	0
T27	405848	0	0	0
T31	27048	0	0	0
T36	0	5778	0	0
T37	0	11712	0	0
T40	351003	0	0	0
T45	0	5354	0	0
T46	0	2550	0	0
T49	0	6463	0	0
T73	274056	0	0	0
T78	0	23714	0	0
T79	0	9241	0	0
T80	0	8713	0	0
T81	0	2726	0	0