Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	408988	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	5122982	1		T1	16		T2	232		T3	13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1361576	1		T1	1		T2	49		T3	1
values[0x0]	1954609	1		T1	13		T2	134		T3	7
values[0x1]	2215785	1		T1	8		T2	161		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	181282	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	5350688	1		T1	17		T2	260		T3	13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21574	1		T2	1		T11	208		T13	2
valid_sources[0x01]	22002	1		T2	1		T13	3		T32	1
valid_sources[0x02]	21113	1		T11	8		T13	2		T41	1
valid_sources[0x03]	21565	1		T8	1		T11	45		T32	3
valid_sources[0x04]	21510	1		T2	1		T11	252		T13	3
valid_sources[0x05]	21875	1		T8	6		T11	467		T13	1
valid_sources[0x06]	20931	1		T2	1		T11	77		T13	2
valid_sources[0x07]	21479	1		T13	2		T32	2		T126	1
valid_sources[0x08]	21953	1		T11	28		T13	4		T126	1
valid_sources[0x09]	22609	1		T2	1		T11	33		T13	2
valid_sources[0x0a]	21137	1		T2	1		T11	544		T32	1
valid_sources[0x0b]	21101	1		T2	6		T11	183		T13	1
valid_sources[0x0c]	21380	1		T2	6		T11	48		T13	2
valid_sources[0x0d]	20805	1		T6	1		T13	1		T32	1
valid_sources[0x0e]	20247	1		T2	1		T11	139		T32	4
valid_sources[0x0f]	21199	1		T2	1		T11	94		T12	1
valid_sources[0x10]	22211	1		T2	1		T11	126		T12	2
valid_sources[0x11]	22701	1		T2	2		T11	677		T13	2
valid_sources[0x12]	20591	1		T8	2		T11	1		T13	2
valid_sources[0x13]	21688	1		T11	116		T13	1		T32	2
valid_sources[0x14]	22442	1		T10	2		T11	131		T13	2
valid_sources[0x15]	21319	1		T8	1		T9	1		T13	1
valid_sources[0x16]	22388	1		T2	1		T11	4		T45	3
valid_sources[0x17]	21995	1		T10	15		T11	215		T13	2
valid_sources[0x18]	21938	1		T11	133		T32	3		T15	818
valid_sources[0x19]	22155	1		T5	300		T13	2		T126	7
valid_sources[0x1a]	23154	1		T1	2		T2	1		T11	337
valid_sources[0x1b]	21887	1		T11	124		T13	2		T32	1
valid_sources[0x1c]	20365	1		T2	2		T4	1		T32	1
valid_sources[0x1d]	22594	1		T11	95		T12	1		T13	1
valid_sources[0x1e]	21746	1		T11	407		T126	3		T15	728
valid_sources[0x1f]	21640	1		T2	3		T7	1		T8	5
valid_sources[0x20]	22530	1		T11	123		T13	2		T15	721
valid_sources[0x21]	19217	1		T1	4		T2	1		T11	17
valid_sources[0x22]	20797	1		T11	154		T32	1		T126	2
valid_sources[0x23]	21284	1		T2	1		T11	10		T32	1
valid_sources[0x24]	22001	1		T2	2		T11	121		T13	2
valid_sources[0x25]	21446	1		T2	1		T7	1		T11	119
valid_sources[0x26]	20255	1		T2	3		T32	1		T126	1
valid_sources[0x27]	23564	1		T2	1		T13	2		T41	1
valid_sources[0x28]	21104	1		T11	147		T126	2		T15	768
valid_sources[0x29]	21943	1		T2	4		T11	613		T13	2
valid_sources[0x2a]	21913	1		T2	1		T11	20		T13	2
valid_sources[0x2b]	22349	1		T11	104		T41	2		T32	2
valid_sources[0x2c]	22736	1		T7	1		T8	7		T11	234
valid_sources[0x2d]	22806	1		T11	20		T13	2		T32	3
valid_sources[0x2e]	20519	1		T2	1		T10	2		T13	3
valid_sources[0x2f]	20511	1		T11	267		T13	1		T126	2
valid_sources[0x30]	21591	1		T2	1		T8	2		T11	226
valid_sources[0x31]	20389	1		T2	2		T9	1		T11	3
valid_sources[0x32]	20841	1		T2	1		T11	1		T13	3
valid_sources[0x33]	20929	1		T1	1		T2	3		T11	130
valid_sources[0x34]	21241	1		T2	3		T11	1		T13	2
valid_sources[0x35]	20989	1		T2	2		T8	4		T13	1
valid_sources[0x36]	21510	1		T126	4		T15	691		T16	9
valid_sources[0x37]	21443	1		T2	1		T11	310		T12	3
valid_sources[0x38]	22881	1		T11	101		T13	2		T51	3
valid_sources[0x39]	21035	1		T2	4		T11	4		T32	3
valid_sources[0x3a]	23791	1		T2	1		T3	18		T8	4
valid_sources[0x3b]	19864	1		T11	12		T32	2		T126	1
valid_sources[0x3c]	21093	1		T1	1		T11	231		T13	1
valid_sources[0x3d]	21506	1		T2	2		T11	187		T13	3
valid_sources[0x3e]	20404	1		T2	1		T8	22		T11	8
valid_sources[0x3f]	20257	1		T11	8		T13	2		T32	2
valid_sources[0x40]	22044	1		T2	2		T12	2		T32	1
valid_sources[0x41]	21349	1		T8	10		T11	167		T13	1
valid_sources[0x42]	22228	1		T32	2		T15	728		T98	5
valid_sources[0x43]	21113	1		T2	3		T7	1		T11	196
valid_sources[0x44]	21121	1		T2	1		T32	1		T126	3
valid_sources[0x45]	20293	1		T11	94		T32	4		T207	3
valid_sources[0x46]	22389	1		T2	1		T11	213		T13	2
valid_sources[0x47]	20800	1		T2	3		T4	2		T11	175
valid_sources[0x48]	22999	1		T2	1		T32	2		T15	741
valid_sources[0x49]	22573	1		T2	2		T11	8		T13	3
valid_sources[0x4a]	22063	1		T2	4		T11	137		T12	1
valid_sources[0x4b]	21180	1		T2	3		T8	4		T11	80
valid_sources[0x4c]	21999	1		T9	1		T13	2		T32	1
valid_sources[0x4d]	21727	1		T2	4		T13	2		T32	1
valid_sources[0x4e]	21708	1		T11	111		T13	2		T32	5
valid_sources[0x4f]	20577	1		T2	2		T6	2		T13	1
valid_sources[0x50]	20404	1		T1	1		T2	3		T11	5
valid_sources[0x51]	21282	1		T6	2		T11	259		T13	1
valid_sources[0x52]	21514	1		T13	2		T32	1		T126	3
valid_sources[0x53]	22270	1		T2	1		T8	25		T11	70
valid_sources[0x54]	22326	1		T11	279		T32	1		T126	7
valid_sources[0x55]	20138	1		T2	9		T11	185		T13	2
valid_sources[0x56]	22820	1		T2	5		T11	283		T32	1
valid_sources[0x57]	23377	1		T2	1		T6	8		T9	1
valid_sources[0x58]	22705	1		T2	2		T11	6		T13	2
valid_sources[0x59]	22481	1		T11	107		T13	2		T32	1
valid_sources[0x5a]	21253	1		T2	1		T13	2		T41	1
valid_sources[0x5b]	21109	1		T2	2		T4	1		T11	101
valid_sources[0x5c]	20536	1		T2	1		T8	8		T11	205
valid_sources[0x5d]	21804	1		T2	1		T11	131		T13	2
valid_sources[0x5e]	21638	1		T2	2		T8	1		T11	4
valid_sources[0x5f]	20658	1		T2	2		T11	6		T13	1
valid_sources[0x60]	20600	1		T7	1		T9	2		T13	3
valid_sources[0x61]	21896	1		T11	196		T13	1		T126	1
valid_sources[0x62]	21592	1		T11	91		T13	1		T31	6
valid_sources[0x63]	22263	1		T2	3		T9	2		T11	384
valid_sources[0x64]	21137	1		T2	1		T8	8		T11	55
valid_sources[0x65]	20551	1		T11	83		T13	1		T126	1
valid_sources[0x66]	22510	1		T11	636		T13	2		T32	2
valid_sources[0x67]	21884	1		T4	1		T8	1		T11	3
valid_sources[0x68]	21585	1		T1	4		T11	128		T13	1
valid_sources[0x69]	20308	1		T2	2		T32	1		T15	688
valid_sources[0x6a]	20710	1		T8	2		T11	344		T126	3
valid_sources[0x6b]	20499	1		T2	1		T11	215		T13	2
valid_sources[0x6c]	20638	1		T2	3		T13	1		T126	1
valid_sources[0x6d]	20747	1		T13	1		T32	3		T126	3
valid_sources[0x6e]	21378	1		T2	1		T8	16		T11	91
valid_sources[0x6f]	22126	1		T11	302		T13	1		T51	1
valid_sources[0x70]	20888	1		T2	2		T6	3		T7	2
valid_sources[0x71]	21582	1		T2	3		T11	66		T13	2
valid_sources[0x72]	21073	1		T11	240		T32	3		T126	2
valid_sources[0x73]	21507	1		T8	2		T11	6		T126	1
valid_sources[0x74]	21061	1		T2	1		T11	2		T32	1
valid_sources[0x75]	21809	1		T2	4		T13	5		T32	1
valid_sources[0x76]	22127	1		T8	9		T12	3		T13	3
valid_sources[0x77]	21819	1		T2	2		T11	298		T13	3
valid_sources[0x78]	20694	1		T41	2		T45	1		T32	1
valid_sources[0x79]	21581	1		T8	2		T11	33		T13	1
valid_sources[0x7a]	22109	1		T2	2		T9	1		T11	198
valid_sources[0x7b]	22453	1		T2	3		T11	1		T13	3
valid_sources[0x7c]	22039	1		T11	138		T13	1		T32	1
valid_sources[0x7d]	21410	1		T8	11		T32	2		T126	2
valid_sources[0x7e]	21799	1		T11	243		T15	856		T16	8
valid_sources[0x7f]	22362	1		T2	4		T7	1		T11	215
valid_sources[0x80]	22817	1		T2	1		T11	361		T13	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1279406

1

T1

1

T2

24

T5

31

values[0x0]

all_enables

biggest_size

1920831

1

T1

10

T2

101

T3

6

values[0x1]

all_enables

biggest_size

1922745

1

T1

5

T2

107

T3

7