Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	776322169	5988374	0	0
wdog_bark_thold_rd_A	776322169	171357	0	0
wdog_bite_thold_rd_A	776322169	148400	0	0
wdog_ctrl_rd_A	776322169	151398	0	0
wdog_regwen_rd_A	776322169	173724	0	0
wkup_ctrl_rd_A	776322169	151205	0	0
wkup_thold_hi_rd_A	776322169	170421	0	0
wkup_thold_lo_rd_A	776322169	151584	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	776322169	5988374	0	0
T11	163664	37827	0	0
T12	129612	0	0	0
T13	442938	0	0	0
T14	3826	0	0	0
T15	0	205811	0	0
T16	0	17419	0	0
T25	0	225195	0	0
T26	0	95776	0	0
T28	0	373861	0	0
T31	9570	0	0	0
T32	225409	0	0	0
T33	219043	0	0	0
T41	36400	0	0	0
T45	127907	0	0	0
T47	0	166343	0	0
T48	0	121570	0	0
T49	0	64751	0	0
T50	0	72091	0	0
T51	878499	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	776322169	171357	0	0
T16	780422	1775	0	0
T17	187700	0	0	0
T26	0	5086	0	0
T47	767614	18197	0	0
T88	0	9102	0	0
T89	0	5121	0	0
T90	0	10001	0	0
T91	0	16870	0	0
T92	0	8743	0	0
T93	0	4264	0	0
T94	0	21669	0	0
T95	33580	0	0	0
T96	40999	0	0	0
T97	37849	0	0	0
T98	158212	0	0	0
T99	747123	0	0	0
T100	784891	0	0	0
T101	20403	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	776322169	148400	0	0
T16	780422	1544	0	0
T17	187700	0	0	0
T26	0	4396	0	0
T47	767614	15457	0	0
T88	0	7702	0	0
T89	0	4359	0	0
T90	0	8654	0	0
T91	0	15009	0	0
T92	0	7666	0	0
T93	0	3394	0	0
T94	0	18991	0	0
T95	33580	0	0	0
T96	40999	0	0	0
T97	37849	0	0	0
T98	158212	0	0	0
T99	747123	0	0	0
T100	784891	0	0	0
T101	20403	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	776322169	151398	0	0
T16	780422	1512	0	0
T17	187700	0	0	0
T26	0	3993	0	0
T47	767614	16266	0	0
T88	0	7995	0	0
T89	0	4336	0	0
T90	0	9497	0	0
T91	0	14956	0	0
T92	0	7851	0	0
T93	0	3725	0	0
T94	0	19469	0	0
T95	33580	0	0	0
T96	40999	0	0	0
T97	37849	0	0	0
T98	158212	0	0	0
T99	747123	0	0	0
T100	784891	0	0	0
T101	20403	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	776322169	173724	0	0
T16	780422	1714	0	0
T17	187700	0	0	0
T26	0	5077	0	0
T47	767614	18188	0	0
T88	0	9217	0	0
T89	0	5297	0	0
T90	0	10649	0	0
T91	0	17534	0	0
T92	0	8930	0	0
T93	0	4087	0	0
T94	0	22446	0	0
T95	33580	0	0	0
T96	40999	0	0	0
T97	37849	0	0	0
T98	158212	0	0	0
T99	747123	0	0	0
T100	784891	0	0	0
T101	20403	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	776322169	151205	0	0
T16	780422	1621	0	0
T17	187700	0	0	0
T26	0	4128	0	0
T47	767614	15552	0	0
T88	0	7611	0	0
T89	0	4397	0	0
T90	0	9424	0	0
T91	0	14387	0	0
T92	0	8127	0	0
T93	0	3696	0	0
T94	0	19745	0	0
T95	33580	0	0	0
T96	40999	0	0	0
T97	37849	0	0	0
T98	158212	0	0	0
T99	747123	0	0	0
T100	784891	0	0	0
T101	20403	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	776322169	170421	0	0
T16	780422	1600	0	0
T17	187700	0	0	0
T26	0	5233	0	0
T47	767614	17475	0	0
T88	0	8287	0	0
T89	0	5382	0	0
T90	0	10180	0	0
T91	0	17149	0	0
T92	0	8969	0	0
T93	0	4026	0	0
T94	0	21604	0	0
T95	33580	0	0	0
T96	40999	0	0	0
T97	37849	0	0	0
T98	158212	0	0	0
T99	747123	0	0	0
T100	784891	0	0	0
T101	20403	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	776322169	151584	0	0
T16	780422	1358	0	0
T17	187700	0	0	0
T26	0	4245	0	0
T47	767614	15804	0	0
T88	0	8043	0	0
T89	0	4830	0	0
T90	0	8969	0	0
T91	0	14337	0	0
T92	0	8316	0	0
T93	0	3474	0	0
T94	0	19482	0	0
T95	33580	0	0	0
T96	40999	0	0	0
T97	37849	0	0	0
T98	158212	0	0	0
T99	747123	0	0	0
T100	784891	0	0	0
T101	20403	0	0	0