Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	327404	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	3998334	1		T1	15		T2	17		T3	19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1063174	1		T1	1		T2	1		T3	1
values[0x0]	1530071	1		T1	10		T2	11		T3	12
values[0x1]	1732493	1		T1	11		T2	10		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	147268	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4178470	1		T1	15		T2	18		T3	19

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16137	1		T6	2		T7	2		T8	932
valid_sources[0x01]	17020	1		T6	2		T7	2		T8	1000
valid_sources[0x02]	16080	1		T6	2		T7	1		T8	948
valid_sources[0x03]	15976	1		T7	1		T8	913		T9	115
valid_sources[0x04]	17202	1		T5	9		T7	1		T8	965
valid_sources[0x05]	16453	1		T3	1		T7	1		T8	1043
valid_sources[0x06]	16174	1		T7	2		T8	977		T9	141
valid_sources[0x07]	16950	1		T7	4		T8	1007		T9	469
valid_sources[0x08]	16406	1		T3	1		T6	2		T7	3
valid_sources[0x09]	17362	1		T7	2		T8	939		T9	51
valid_sources[0x0a]	16939	1		T5	1		T6	2		T8	1020
valid_sources[0x0b]	16874	1		T7	3		T8	919		T9	5
valid_sources[0x0c]	18102	1		T7	2		T8	1006		T9	181
valid_sources[0x0d]	15443	1		T7	1		T8	968		T9	19
valid_sources[0x0e]	15959	1		T7	3		T8	918		T9	110
valid_sources[0x0f]	15860	1		T7	3		T8	903		T9	4
valid_sources[0x10]	17298	1		T3	1		T7	2		T8	970
valid_sources[0x11]	17496	1		T8	959		T9	264		T31	1
valid_sources[0x12]	16199	1		T7	1		T8	898		T9	7
valid_sources[0x13]	16824	1		T7	2		T8	920		T9	241
valid_sources[0x14]	16677	1		T7	1		T8	912		T9	163
valid_sources[0x15]	17096	1		T7	2		T8	924		T9	329
valid_sources[0x16]	16325	1		T8	922		T9	499		T32	3
valid_sources[0x17]	16718	1		T7	2		T8	902		T9	5
valid_sources[0x18]	16556	1		T7	1		T8	926		T9	2
valid_sources[0x19]	17283	1		T6	4		T8	866		T9	12
valid_sources[0x1a]	16842	1		T6	1		T7	4		T8	893
valid_sources[0x1b]	16466	1		T3	1		T7	2		T8	912
valid_sources[0x1c]	17046	1		T7	2		T8	947		T9	210
valid_sources[0x1d]	16357	1		T7	2		T8	912		T9	22
valid_sources[0x1e]	16664	1		T6	1		T8	897		T9	302
valid_sources[0x1f]	17564	1		T7	1		T8	960		T9	9
valid_sources[0x20]	16713	1		T6	3		T7	2		T8	906
valid_sources[0x21]	16046	1		T8	977		T9	4		T15	1
valid_sources[0x22]	16568	1		T7	2		T8	879		T9	180
valid_sources[0x23]	16297	1		T8	991		T9	105		T11	1
valid_sources[0x24]	17519	1		T6	2		T8	953		T9	36
valid_sources[0x25]	17209	1		T6	3		T7	2		T8	977
valid_sources[0x26]	16533	1		T6	6		T8	969		T9	48
valid_sources[0x27]	17123	1		T6	2		T7	4		T8	912
valid_sources[0x28]	16670	1		T7	1		T8	965		T9	62
valid_sources[0x29]	16878	1		T7	2		T8	948		T9	161
valid_sources[0x2a]	17485	1		T6	5		T7	2		T8	1010
valid_sources[0x2b]	16819	1		T7	2		T8	962		T9	139
valid_sources[0x2c]	17345	1		T7	2		T8	901		T9	48
valid_sources[0x2d]	16531	1		T8	933		T9	186		T32	1
valid_sources[0x2e]	16642	1		T2	22		T8	953		T9	173
valid_sources[0x2f]	17557	1		T4	1		T6	2		T7	1
valid_sources[0x30]	16921	1		T7	2		T8	1009		T9	94
valid_sources[0x31]	16091	1		T8	972		T9	267		T12	2
valid_sources[0x32]	17222	1		T3	1		T7	3		T8	916
valid_sources[0x33]	17077	1		T3	2		T7	2		T8	968
valid_sources[0x34]	17137	1		T6	4		T8	908		T9	218
valid_sources[0x35]	16153	1		T7	3		T8	927		T9	11
valid_sources[0x36]	17115	1		T6	4		T7	2		T8	899
valid_sources[0x37]	16655	1		T6	3		T8	913		T9	202
valid_sources[0x38]	15935	1		T6	2		T7	3		T8	946
valid_sources[0x39]	16621	1		T7	4		T8	995		T9	24
valid_sources[0x3a]	15923	1		T7	1		T8	926		T9	300
valid_sources[0x3b]	17360	1		T7	2		T8	969		T9	282
valid_sources[0x3c]	16195	1		T7	3		T8	1002		T9	388
valid_sources[0x3d]	18286	1		T8	964		T9	662		T16	627
valid_sources[0x3e]	17281	1		T6	3		T7	1		T8	902
valid_sources[0x3f]	17434	1		T4	1		T7	1		T8	981
valid_sources[0x40]	17328	1		T7	2		T8	950		T9	175
valid_sources[0x41]	16140	1		T6	1		T7	1		T8	931
valid_sources[0x42]	16936	1		T7	1		T8	920		T9	88
valid_sources[0x43]	16858	1		T7	2		T8	964		T9	110
valid_sources[0x44]	17001	1		T8	964		T9	37		T32	3
valid_sources[0x45]	16844	1		T6	12		T7	1		T8	926
valid_sources[0x46]	15856	1		T8	919		T9	8		T32	4
valid_sources[0x47]	15985	1		T6	8		T8	947		T9	14
valid_sources[0x48]	16384	1		T6	4		T8	879		T9	129
valid_sources[0x49]	18054	1		T7	9		T8	946		T9	323
valid_sources[0x4a]	16567	1		T5	4		T6	7		T8	974
valid_sources[0x4b]	16861	1		T6	1		T7	2		T8	873
valid_sources[0x4c]	16324	1		T7	2		T8	969		T9	474
valid_sources[0x4d]	16746	1		T6	3		T7	3		T8	904
valid_sources[0x4e]	17385	1		T6	2		T7	1		T8	1006
valid_sources[0x4f]	16726	1		T7	1		T8	962		T9	240
valid_sources[0x50]	17753	1		T8	952		T9	345		T11	1
valid_sources[0x51]	16835	1		T6	1		T8	989		T9	218
valid_sources[0x52]	16080	1		T6	4		T7	1		T8	906
valid_sources[0x53]	15651	1		T8	985		T9	71		T47	1
valid_sources[0x54]	17221	1		T7	3		T8	972		T9	92
valid_sources[0x55]	17473	1		T7	1		T8	1005		T9	199
valid_sources[0x56]	17559	1		T6	6		T7	1		T8	926
valid_sources[0x57]	17096	1		T6	2		T7	1		T8	974
valid_sources[0x58]	17155	1		T7	2		T8	949		T9	239
valid_sources[0x59]	17125	1		T3	3		T7	1		T8	908
valid_sources[0x5a]	17132	1		T7	2		T8	997		T9	323
valid_sources[0x5b]	17420	1		T7	1		T8	941		T9	25
valid_sources[0x5c]	16698	1		T6	5		T7	1		T8	932
valid_sources[0x5d]	17616	1		T6	1		T7	2		T8	973
valid_sources[0x5e]	16763	1		T7	4		T8	959		T9	566
valid_sources[0x5f]	17122	1		T7	2		T8	942		T9	229
valid_sources[0x60]	16641	1		T7	1		T8	950		T9	33
valid_sources[0x61]	18046	1		T7	2		T8	984		T9	9
valid_sources[0x62]	17283	1		T4	1		T6	3		T7	1
valid_sources[0x63]	16178	1		T7	3		T8	954		T9	202
valid_sources[0x64]	15651	1		T6	7		T8	964		T9	68
valid_sources[0x65]	16561	1		T6	2		T7	2		T8	968
valid_sources[0x66]	16144	1		T4	2		T7	1		T8	850
valid_sources[0x67]	16497	1		T6	5		T7	2		T8	925
valid_sources[0x68]	16830	1		T8	937		T9	378		T32	2
valid_sources[0x69]	17752	1		T8	945		T9	555		T31	1
valid_sources[0x6a]	16900	1		T7	5		T8	959		T9	265
valid_sources[0x6b]	16127	1		T4	2		T6	2		T7	2
valid_sources[0x6c]	17296	1		T8	921		T9	119		T32	2
valid_sources[0x6d]	17218	1		T7	2		T8	990		T9	13
valid_sources[0x6e]	16275	1		T7	1		T8	944		T9	38
valid_sources[0x6f]	16172	1		T6	2		T8	885		T9	31
valid_sources[0x70]	16787	1		T7	1		T8	959		T9	416
valid_sources[0x71]	17153	1		T7	3		T8	956		T9	149
valid_sources[0x72]	17078	1		T6	4		T7	2		T8	977
valid_sources[0x73]	17188	1		T7	2		T8	1015		T9	17
valid_sources[0x74]	18967	1		T5	4		T7	2		T8	970
valid_sources[0x75]	17168	1		T7	1		T8	947		T9	18
valid_sources[0x76]	15822	1		T7	1		T8	967		T9	104
valid_sources[0x77]	16250	1		T8	875		T9	130		T32	1
valid_sources[0x78]	17217	1		T8	951		T9	251		T12	1
valid_sources[0x79]	16970	1		T3	1		T6	1		T7	2
valid_sources[0x7a]	16529	1		T7	3		T8	960		T9	382
valid_sources[0x7b]	16906	1		T7	3		T8	978		T9	165
valid_sources[0x7c]	18625	1		T7	1		T8	947		T9	415
valid_sources[0x7d]	16219	1		T7	1		T8	939		T9	11
valid_sources[0x7e]	16764	1		T7	4		T8	973		T9	20
valid_sources[0x7f]	16630	1		T7	1		T8	1002		T9	290
valid_sources[0x80]	17336	1		T6	2		T7	3		T8	918

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

996115

1

T1

1

T2

1

T3

1

values[0x0]

all_enables

biggest_size

1502189

1

T1

6

T2

8

T3

11

values[0x1]

all_enables

biggest_size

1500030

1

T1

8

T2

8

T3

7