Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	708698134	4726461	0	0
wdog_bark_thold_rd_A	708698134	105810	0	0
wdog_bite_thold_rd_A	708698134	92225	0	0
wdog_ctrl_rd_A	708698134	94076	0	0
wdog_regwen_rd_A	708698134	107818	0	0
wkup_ctrl_rd_A	708698134	92795	0	0
wkup_thold_hi_rd_A	708698134	106575	0	0
wkup_thold_lo_rd_A	708698134	93158	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708698134	4726461	0	0
T8	115405	257011	0	0
T9	111954	41846	0	0
T10	598869	0	0	0
T11	268406	0	0	0
T12	468079	0	0	0
T13	251278	0	0	0
T14	3756	0	0	0
T15	38201	0	0	0
T16	0	169724	0	0
T31	55824	0	0	0
T40	0	80508	0	0
T41	0	53453	0	0
T42	0	33828	0	0
T43	0	50986	0	0
T44	0	29292	0	0
T45	0	109473	0	0
T46	0	84859	0	0
T47	36894	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708698134	105810	0	0
T8	115405	25443	0	0
T9	111954	0	0	0
T10	598869	0	0	0
T11	268406	0	0	0
T12	468079	0	0	0
T13	251278	0	0	0
T14	3756	0	0	0
T15	38201	0	0	0
T31	55824	0	0	0
T40	0	7981	0	0
T41	0	2795	0	0
T42	0	3147	0	0
T44	0	3011	0	0
T47	36894	0	0	0
T57	0	2685	0	0
T92	0	1385	0	0
T93	0	2635	0	0
T94	0	12599	0	0
T95	0	10827	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708698134	92225	0	0
T8	115405	21645	0	0
T9	111954	0	0	0
T10	598869	0	0	0
T11	268406	0	0	0
T12	468079	0	0	0
T13	251278	0	0	0
T14	3756	0	0	0
T15	38201	0	0	0
T31	55824	0	0	0
T40	0	6506	0	0
T41	0	2456	0	0
T42	0	2954	0	0
T44	0	2721	0	0
T47	36894	0	0	0
T57	0	2380	0	0
T92	0	1133	0	0
T93	0	2067	0	0
T94	0	11040	0	0
T95	0	9984	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708698134	94076	0	0
T8	115405	21949	0	0
T9	111954	0	0	0
T10	598869	0	0	0
T11	268406	0	0	0
T12	468079	0	0	0
T13	251278	0	0	0
T14	3756	0	0	0
T15	38201	0	0	0
T31	55824	0	0	0
T40	0	6842	0	0
T41	0	2554	0	0
T42	0	2935	0	0
T44	0	2584	0	0
T47	36894	0	0	0
T57	0	2365	0	0
T92	0	1083	0	0
T93	0	2155	0	0
T94	0	11827	0	0
T95	0	9937	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708698134	107818	0	0
T8	115405	25501	0	0
T9	111954	0	0	0
T10	598869	0	0	0
T11	268406	0	0	0
T12	468079	0	0	0
T13	251278	0	0	0
T14	3756	0	0	0
T15	38201	0	0	0
T31	55824	0	0	0
T40	0	7602	0	0
T41	0	3150	0	0
T42	0	3237	0	0
T44	0	3350	0	0
T47	36894	0	0	0
T57	0	2965	0	0
T92	0	1213	0	0
T93	0	2530	0	0
T94	0	12484	0	0
T95	0	11321	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708698134	92795	0	0
T8	115405	21888	0	0
T9	111954	0	0	0
T10	598869	0	0	0
T11	268406	0	0	0
T12	468079	0	0	0
T13	251278	0	0	0
T14	3756	0	0	0
T15	38201	0	0	0
T31	55824	0	0	0
T40	0	6479	0	0
T41	0	2362	0	0
T42	0	2967	0	0
T44	0	2444	0	0
T47	36894	0	0	0
T57	0	2442	0	0
T92	0	1033	0	0
T93	0	2214	0	0
T94	0	11611	0	0
T95	0	9485	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708698134	106575	0	0
T8	115405	25420	0	0
T9	111954	0	0	0
T10	598869	0	0	0
T11	268406	0	0	0
T12	468079	0	0	0
T13	251278	0	0	0
T14	3756	0	0	0
T15	38201	0	0	0
T31	55824	0	0	0
T40	0	7608	0	0
T41	0	3115	0	0
T42	0	3427	0	0
T44	0	2854	0	0
T47	36894	0	0	0
T57	0	2787	0	0
T92	0	1266	0	0
T93	0	2344	0	0
T94	0	12577	0	0
T95	0	11187	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	708698134	93158	0	0
T8	115405	21834	0	0
T9	111954	0	0	0
T10	598869	0	0	0
T11	268406	0	0	0
T12	468079	0	0	0
T13	251278	0	0	0
T14	3756	0	0	0
T15	38201	0	0	0
T31	55824	0	0	0
T40	0	6533	0	0
T41	0	2606	0	0
T42	0	3040	0	0
T44	0	2617	0	0
T47	36894	0	0	0
T57	0	2408	0	0
T92	0	1191	0	0
T93	0	2325	0	0
T94	0	11794	0	0
T95	0	9437	0	0