Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	714923628	5219473	0	0
wdog_bark_thold_rd_A	714923628	133157	0	0
wdog_bite_thold_rd_A	714923628	117225	0	0
wdog_ctrl_rd_A	714923628	116056	0	0
wdog_regwen_rd_A	714923628	132493	0	0
wkup_ctrl_rd_A	714923628	116040	0	0
wkup_thold_hi_rd_A	714923628	132519	0	0
wkup_thold_lo_rd_A	714923628	116867	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714923628	5219473	0	0
T1	817201	129906	0	0
T2	229153	0	0	0
T3	330015	90043	0	0
T4	21922	0	0	0
T5	766838	0	0	0
T6	291082	0	0	0
T7	157649	0	0	0
T8	8144	0	0	0
T9	150897	0	0	0
T10	10240	0	0	0
T13	0	163332	0	0
T14	0	65235	0	0
T31	0	272345	0	0
T38	0	83827	0	0
T39	0	73000	0	0
T40	0	45469	0	0
T41	0	145604	0	0
T42	0	42690	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714923628	133157	0	0
T1	817201	13781	0	0
T2	229153	0	0	0
T3	330015	0	0	0
T4	21922	0	0	0
T5	766838	0	0	0
T6	291082	0	0	0
T7	157649	0	0	0
T8	8144	0	0	0
T9	150897	0	0	0
T10	10240	0	0	0
T38	0	4587	0	0
T41	0	14499	0	0
T48	0	2098	0	0
T50	0	4906	0	0
T96	0	13164	0	0
T97	0	20275	0	0
T98	0	3736	0	0
T99	0	3064	0	0
T100	0	3217	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714923628	117225	0	0
T1	817201	11664	0	0
T2	229153	0	0	0
T3	330015	0	0	0
T4	21922	0	0	0
T5	766838	0	0	0
T6	291082	0	0	0
T7	157649	0	0	0
T8	8144	0	0	0
T9	150897	0	0	0
T10	10240	0	0	0
T38	0	4044	0	0
T41	0	12409	0	0
T48	0	1760	0	0
T50	0	4159	0	0
T96	0	11144	0	0
T97	0	18084	0	0
T98	0	3301	0	0
T99	0	2875	0	0
T100	0	3374	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714923628	116056	0	0
T1	817201	12041	0	0
T2	229153	0	0	0
T3	330015	0	0	0
T4	21922	0	0	0
T5	766838	0	0	0
T6	291082	0	0	0
T7	157649	0	0	0
T8	8144	0	0	0
T9	150897	0	0	0
T10	10240	0	0	0
T38	0	3965	0	0
T41	0	12177	0	0
T48	0	1738	0	0
T50	0	4019	0	0
T96	0	11742	0	0
T97	0	18014	0	0
T98	0	3232	0	0
T99	0	2598	0	0
T100	0	2877	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714923628	132493	0	0
T1	817201	13472	0	0
T2	229153	0	0	0
T3	330015	0	0	0
T4	21922	0	0	0
T5	766838	0	0	0
T6	291082	0	0	0
T7	157649	0	0	0
T8	8144	0	0	0
T9	150897	0	0	0
T10	10240	0	0	0
T38	0	4686	0	0
T41	0	14064	0	0
T48	0	2133	0	0
T50	0	4492	0	0
T96	0	13063	0	0
T97	0	21218	0	0
T98	0	3728	0	0
T99	0	2948	0	0
T100	0	3592	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714923628	116040	0	0
T1	817201	11927	0	0
T2	229153	0	0	0
T3	330015	0	0	0
T4	21922	0	0	0
T5	766838	0	0	0
T6	291082	0	0	0
T7	157649	0	0	0
T8	8144	0	0	0
T9	150897	0	0	0
T10	10240	0	0	0
T38	0	3952	0	0
T41	0	12165	0	0
T48	0	1737	0	0
T50	0	3958	0	0
T96	0	11308	0	0
T97	0	17882	0	0
T98	0	3373	0	0
T99	0	2630	0	0
T100	0	2958	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714923628	132519	0	0
T1	817201	13225	0	0
T2	229153	0	0	0
T3	330015	0	0	0
T4	21922	0	0	0
T5	766838	0	0	0
T6	291082	0	0	0
T7	157649	0	0	0
T8	8144	0	0	0
T9	150897	0	0	0
T10	10240	0	0	0
T38	0	4671	0	0
T41	0	14071	0	0
T48	0	1831	0	0
T50	0	4745	0	0
T96	0	12676	0	0
T97	0	20448	0	0
T98	0	3837	0	0
T99	0	3229	0	0
T100	0	3263	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714923628	116867	0	0
T1	817201	11643	0	0
T2	229153	0	0	0
T3	330015	0	0	0
T4	21922	0	0	0
T5	766838	0	0	0
T6	291082	0	0	0
T7	157649	0	0	0
T8	8144	0	0	0
T9	150897	0	0	0
T10	10240	0	0	0
T38	0	4180	0	0
T41	0	12251	0	0
T48	0	1721	0	0
T50	0	4093	0	0
T96	0	11411	0	0
T97	0	18511	0	0
T98	0	3032	0	0
T99	0	2630	0	0
T100	0	3292	0	0