Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	295812	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	3576682	1		T1	16		T2	12		T3	14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	953290	1		T1	1		T2	1		T3	1
values[0x0]	1368106	1		T1	11		T2	9		T3	9
values[0x1]	1551098	1		T1	10		T2	8		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	133412	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	3739082	1		T1	16		T2	12		T3	16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14839	1		T8	1		T12	1		T17	74
valid_sources[0x01]	14194	1		T7	1		T8	1		T17	91
valid_sources[0x02]	15837	1		T6	1		T7	2		T8	1
valid_sources[0x03]	13697	1		T7	3		T17	93		T18	87
valid_sources[0x04]	14936	1		T7	1		T8	1		T17	84
valid_sources[0x05]	14520	1		T8	5		T17	79		T18	93
valid_sources[0x06]	15531	1		T7	5		T17	84		T18	71
valid_sources[0x07]	14649	1		T3	1		T7	2		T17	79
valid_sources[0x08]	15719	1		T8	6		T9	4		T15	1
valid_sources[0x09]	15485	1		T7	1		T17	73		T18	64
valid_sources[0x0a]	15465	1		T10	1		T13	2		T17	67
valid_sources[0x0b]	16836	1		T15	1		T17	86		T18	93
valid_sources[0x0c]	15043	1		T7	2		T8	4		T15	1
valid_sources[0x0d]	13916	1		T17	91		T18	74		T93	4
valid_sources[0x0e]	14762	1		T7	2		T8	2		T17	71
valid_sources[0x0f]	14696	1		T8	1		T17	85		T18	82
valid_sources[0x10]	14983	1		T7	1		T13	2		T15	1
valid_sources[0x11]	14083	1		T6	1		T7	2		T8	1
valid_sources[0x12]	15502	1		T7	1		T8	1		T13	1
valid_sources[0x13]	15119	1		T8	7		T17	64		T18	89
valid_sources[0x14]	14214	1		T7	2		T8	6		T17	74
valid_sources[0x15]	14985	1		T7	10		T17	75		T18	73
valid_sources[0x16]	15895	1		T6	1		T8	3		T15	2
valid_sources[0x17]	15870	1		T17	95		T18	91		T19	179
valid_sources[0x18]	14451	1		T3	6		T7	4		T8	1
valid_sources[0x19]	15012	1		T8	2		T17	76		T52	1
valid_sources[0x1a]	13955	1		T7	1		T8	1		T17	87
valid_sources[0x1b]	14716	1		T7	1		T17	70		T18	81
valid_sources[0x1c]	13839	1		T7	4		T12	3		T17	92
valid_sources[0x1d]	14488	1		T17	92		T18	97		T19	242
valid_sources[0x1e]	14404	1		T7	4		T8	2		T13	2
valid_sources[0x1f]	14689	1		T7	4		T17	77		T18	90
valid_sources[0x20]	14700	1		T8	2		T17	93		T18	87
valid_sources[0x21]	15875	1		T2	3		T7	2		T8	1
valid_sources[0x22]	15702	1		T8	2		T10	1		T17	74
valid_sources[0x23]	17117	1		T3	3		T8	1		T17	68
valid_sources[0x24]	14549	1		T7	5		T17	68		T18	78
valid_sources[0x25]	13376	1		T4	1		T6	3		T8	2
valid_sources[0x26]	14769	1		T8	1		T17	76		T18	86
valid_sources[0x27]	14561	1		T7	2		T17	80		T52	1
valid_sources[0x28]	16482	1		T4	1		T7	2		T8	2
valid_sources[0x29]	15476	1		T7	2		T8	3		T17	83
valid_sources[0x2a]	14889	1		T8	1		T17	97		T18	100
valid_sources[0x2b]	14920	1		T7	1		T8	1		T17	76
valid_sources[0x2c]	14101	1		T17	58		T18	82		T19	200
valid_sources[0x2d]	14503	1		T8	5		T17	79		T18	86
valid_sources[0x2e]	15675	1		T7	4		T17	108		T18	82
valid_sources[0x2f]	14854	1		T8	1		T17	90		T18	98
valid_sources[0x30]	15358	1		T15	1		T17	88		T18	104
valid_sources[0x31]	14016	1		T3	1		T17	106		T18	97
valid_sources[0x32]	14173	1		T8	1		T17	93		T18	83
valid_sources[0x33]	16218	1		T8	4		T17	88		T18	101
valid_sources[0x34]	16682	1		T12	1		T17	88		T18	80
valid_sources[0x35]	14992	1		T7	1		T17	83		T18	72
valid_sources[0x36]	14265	1		T7	4		T8	4		T17	80
valid_sources[0x37]	15510	1		T7	2		T8	1		T17	94
valid_sources[0x38]	14113	1		T8	4		T34	19		T17	92
valid_sources[0x39]	16817	1		T7	1		T8	1		T17	71
valid_sources[0x3a]	16005	1		T4	1		T17	74		T18	85
valid_sources[0x3b]	15089	1		T8	1		T12	1		T17	64
valid_sources[0x3c]	15366	1		T7	1		T17	83		T52	1
valid_sources[0x3d]	16459	1		T8	3		T12	1		T17	95
valid_sources[0x3e]	15350	1		T8	1		T17	77		T18	81
valid_sources[0x3f]	15445	1		T8	2		T17	86		T18	79
valid_sources[0x40]	16230	1		T7	1		T17	79		T18	74
valid_sources[0x41]	15191	1		T17	86		T18	73		T19	252
valid_sources[0x42]	14725	1		T12	1		T17	79		T18	86
valid_sources[0x43]	15616	1		T7	1		T8	3		T17	98
valid_sources[0x44]	16046	1		T7	3		T8	5		T17	81
valid_sources[0x45]	14957	1		T6	1		T8	1		T17	79
valid_sources[0x46]	15322	1		T10	1		T15	1		T17	68
valid_sources[0x47]	14351	1		T7	2		T17	86		T18	85
valid_sources[0x48]	15670	1		T17	84		T52	1		T18	91
valid_sources[0x49]	13549	1		T7	1		T8	2		T17	83
valid_sources[0x4a]	15126	1		T7	1		T8	1		T17	80
valid_sources[0x4b]	15818	1		T8	3		T17	104		T18	83
valid_sources[0x4c]	15293	1		T17	68		T18	77		T19	177
valid_sources[0x4d]	14152	1		T7	1		T17	93		T18	89
valid_sources[0x4e]	14340	1		T8	1		T16	1		T17	78
valid_sources[0x4f]	14989	1		T8	2		T17	72		T35	1
valid_sources[0x50]	15577	1		T3	2		T8	2		T17	71
valid_sources[0x51]	16374	1		T7	1		T8	3		T17	82
valid_sources[0x52]	15942	1		T4	1		T7	4		T8	1
valid_sources[0x53]	14385	1		T8	1		T17	92		T18	87
valid_sources[0x54]	15570	1		T6	1		T7	3		T17	76
valid_sources[0x55]	14172	1		T7	1		T17	96		T18	86
valid_sources[0x56]	15221	1		T4	1		T8	2		T17	81
valid_sources[0x57]	15704	1		T8	3		T17	76		T18	85
valid_sources[0x58]	16236	1		T8	2		T17	76		T52	1
valid_sources[0x59]	15719	1		T10	1		T17	76		T18	91
valid_sources[0x5a]	16387	1		T17	100		T18	78		T19	198
valid_sources[0x5b]	15066	1		T7	1		T8	1		T17	81
valid_sources[0x5c]	15240	1		T4	2		T10	1		T13	2
valid_sources[0x5d]	14800	1		T7	3		T8	5		T17	75
valid_sources[0x5e]	13928	1		T7	4		T8	2		T17	63
valid_sources[0x5f]	14249	1		T8	1		T17	86		T18	93
valid_sources[0x60]	15015	1		T7	8		T17	82		T52	1
valid_sources[0x61]	15246	1		T8	3		T17	86		T18	110
valid_sources[0x62]	14196	1		T7	4		T8	2		T15	1
valid_sources[0x63]	15282	1		T7	1		T17	77		T18	89
valid_sources[0x64]	15337	1		T8	1		T9	2		T17	89
valid_sources[0x65]	14110	1		T8	2		T17	77		T18	71
valid_sources[0x66]	14354	1		T7	1		T8	2		T17	81
valid_sources[0x67]	15233	1		T2	4		T7	4		T8	1
valid_sources[0x68]	15902	1		T7	3		T8	2		T17	81
valid_sources[0x69]	16024	1		T17	100		T18	59		T19	227
valid_sources[0x6a]	15445	1		T6	2		T8	3		T17	78
valid_sources[0x6b]	14781	1		T7	1		T8	3		T11	22
valid_sources[0x6c]	15157	1		T17	104		T18	61		T19	254
valid_sources[0x6d]	15715	1		T7	3		T8	1		T17	85
valid_sources[0x6e]	15667	1		T8	2		T17	69		T53	20
valid_sources[0x6f]	14755	1		T8	1		T17	88		T18	86
valid_sources[0x70]	15807	1		T3	2		T10	1		T17	73
valid_sources[0x71]	15227	1		T8	3		T17	72		T54	1
valid_sources[0x72]	15198	1		T8	2		T15	1		T17	76
valid_sources[0x73]	15082	1		T10	1		T16	3		T17	87
valid_sources[0x74]	16967	1		T8	1		T17	71		T54	1
valid_sources[0x75]	15386	1		T7	4		T8	2		T10	1
valid_sources[0x76]	15557	1		T7	1		T17	86		T18	92
valid_sources[0x77]	15541	1		T8	3		T17	68		T18	73
valid_sources[0x78]	15944	1		T17	88		T18	100		T93	2
valid_sources[0x79]	15353	1		T8	1		T17	94		T52	1
valid_sources[0x7a]	14973	1		T7	3		T17	87		T18	79
valid_sources[0x7b]	13957	1		T8	1		T17	67		T18	59
valid_sources[0x7c]	16918	1		T8	1		T13	1		T17	81
valid_sources[0x7d]	15494	1		T8	3		T17	85		T18	103
valid_sources[0x7e]	15894	1		T4	1		T7	2		T8	3
valid_sources[0x7f]	14230	1		T7	1		T8	2		T13	1
valid_sources[0x80]	16331	1		T8	2		T10	1		T15	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

892758

1

T7

16

T8

23

T11

1

values[0x0]

all_enables

biggest_size

1342511

1

T1

10

T2

6

T3

8

values[0x1]

all_enables

biggest_size

1341413

1

T1

6

T2

6

T3

6