Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	594682020	4235472	0	0
wdog_bark_thold_rd_A	594682020	102755	0	0
wdog_bite_thold_rd_A	594682020	89819	0	0
wdog_ctrl_rd_A	594682020	90670	0	0
wdog_regwen_rd_A	594682020	102181	0	0
wkup_ctrl_rd_A	594682020	89278	0	0
wkup_thold_hi_rd_A	594682020	102617	0	0
wkup_thold_lo_rd_A	594682020	89742	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	594682020	4235472	0	0
T17	996392	22862	0	0
T18	143730	26623	0	0
T19	0	59254	0	0
T35	10126	0	0	0
T36	38212	0	0	0
T37	581240	0	0	0
T38	0	91865	0	0
T46	0	58100	0	0
T47	0	209522	0	0
T48	0	87613	0	0
T49	0	146678	0	0
T50	0	132413	0	0
T51	0	141553	0	0
T52	10346	0	0	0
T53	630984	0	0	0
T54	51266	0	0	0
T55	11501	0	0	0
T56	53523	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	594682020	102755	0	0
T18	143730	1117	0	0
T19	332200	5656	0	0
T30	0	5216	0	0
T33	0	5393	0	0
T47	0	11176	0	0
T48	0	4556	0	0
T50	0	13371	0	0
T93	240432	0	0	0
T94	249197	0	0	0
T95	10707	0	0	0
T96	9463	0	0	0
T97	152406	0	0	0
T98	260518	0	0	0
T99	14387	0	0	0
T100	157125	0	0	0
T104	0	14154	0	0
T105	0	6943	0	0
T106	0	3550	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	594682020	89819	0	0
T18	143730	1076	0	0
T19	332200	5106	0	0
T30	0	4358	0	0
T33	0	4786	0	0
T47	0	9795	0	0
T48	0	3931	0	0
T50	0	11799	0	0
T93	240432	0	0	0
T94	249197	0	0	0
T95	10707	0	0	0
T96	9463	0	0	0
T97	152406	0	0	0
T98	260518	0	0	0
T99	14387	0	0	0
T100	157125	0	0	0
T104	0	12895	0	0
T105	0	6444	0	0
T106	0	2762	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	594682020	90670	0	0
T18	143730	1028	0	0
T19	332200	5089	0	0
T30	0	4381	0	0
T33	0	5016	0	0
T47	0	9508	0	0
T48	0	4102	0	0
T50	0	11462	0	0
T93	240432	0	0	0
T94	249197	0	0	0
T95	10707	0	0	0
T96	9463	0	0	0
T97	152406	0	0	0
T98	260518	0	0	0
T99	14387	0	0	0
T100	157125	0	0	0
T104	0	13071	0	0
T105	0	6321	0	0
T106	0	3111	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	594682020	102181	0	0
T18	143730	1217	0	0
T19	332200	5413	0	0
T30	0	5322	0	0
T33	0	5671	0	0
T47	0	11042	0	0
T48	0	4410	0	0
T50	0	12540	0	0
T93	240432	0	0	0
T94	249197	0	0	0
T95	10707	0	0	0
T96	9463	0	0	0
T97	152406	0	0	0
T98	260518	0	0	0
T99	14387	0	0	0
T100	157125	0	0	0
T104	0	14144	0	0
T105	0	7373	0	0
T106	0	3331	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	594682020	89278	0	0
T18	143730	1127	0	0
T19	332200	5102	0	0
T30	0	4552	0	0
T33	0	4713	0	0
T47	0	9589	0	0
T48	0	4046	0	0
T50	0	10956	0	0
T93	240432	0	0	0
T94	249197	0	0	0
T95	10707	0	0	0
T96	9463	0	0	0
T97	152406	0	0	0
T98	260518	0	0	0
T99	14387	0	0	0
T100	157125	0	0	0
T104	0	12437	0	0
T105	0	6445	0	0
T106	0	2964	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	594682020	102617	0	0
T18	143730	1313	0	0
T19	332200	5650	0	0
T30	0	5107	0	0
T33	0	5853	0	0
T47	0	11463	0	0
T48	0	4470	0	0
T50	0	13112	0	0
T93	240432	0	0	0
T94	249197	0	0	0
T95	10707	0	0	0
T96	9463	0	0	0
T97	152406	0	0	0
T98	260518	0	0	0
T99	14387	0	0	0
T100	157125	0	0	0
T104	0	14623	0	0
T105	0	6997	0	0
T106	0	3359	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	594682020	89742	0	0
T18	143730	999	0	0
T19	332200	5105	0	0
T30	0	4562	0	0
T33	0	4568	0	0
T47	0	9750	0	0
T48	0	3922	0	0
T50	0	11837	0	0
T93	240432	0	0	0
T94	249197	0	0	0
T95	10707	0	0	0
T96	9463	0	0	0
T97	152406	0	0	0
T98	260518	0	0	0
T99	14387	0	0	0
T100	157125	0	0	0
T104	0	12374	0	0
T105	0	5986	0	0
T106	0	2906	0	0