Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	31062	1		T2	784		T3	245		T5	830
bark[1]	657	1		T17	39		T32	93		T179	21
bark[2]	462	1		T31	64		T33	21		T134	21
bark[3]	458	1		T7	14		T11	26		T30	39
bark[4]	830	1		T14	21		T46	26		T131	26
bark[5]	564	1		T2	243		T29	7		T32	21
bark[6]	257	1		T17	39		T20	21		T32	21
bark[7]	548	1		T3	21		T20	21		T38	53
bark[8]	1146	1		T30	252		T32	30		T110	23
bark[9]	441	1		T3	21		T32	21		T183	14
bark[10]	332	1		T10	14		T160	7		T148	168
bark[11]	557	1		T2	21		T11	59		T32	42
bark[12]	759	1		T38	30		T46	21		T136	26
bark[13]	279	1		T2	21		T175	31		T139	26
bark[14]	529	1		T40	21		T48	14		T162	70
bark[15]	460	1		T17	35		T28	7		T38	21
bark[16]	827	1		T11	14		T30	26		T39	78
bark[17]	191	1		T2	35		T33	21		T42	44
bark[18]	221	1		T3	21		T40	148		T90	31
bark[19]	433	1		T6	112		T44	40		T173	21
bark[20]	417	1		T1	14		T47	21		T163	7
bark[21]	563	1		T79	21		T134	5		T47	61
bark[22]	453	1		T2	35		T14	26		T28	64
bark[23]	299	1		T43	21		T126	26		T83	212
bark[24]	333	1		T190	14		T49	14		T136	26
bark[25]	294	1		T5	43		T30	64		T42	21
bark[26]	449	1		T110	26		T44	40		T151	30
bark[27]	734	1		T38	26		T42	67		T47	73
bark[28]	519	1		T5	21		T32	54		T47	199
bark[29]	599	1		T14	21		T30	64		T126	7
bark[30]	261	1		T75	14		T123	21		T165	33
bark[31]	592	1		T2	183		T33	21		T46	21
bark_0	4640	1		T1	7		T2	103		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	30562	1		T2	767		T3	244		T5	823
bite[1]	482	1		T2	182		T38	21		T30	39
bite[2]	592	1		T3	21		T31	63		T32	21
bite[3]	514	1		T20	21		T115	26		T175	31
bite[4]	288	1		T2	21		T6	21		T38	26
bite[5]	409	1		T185	13		T190	13		T44	40
bite[6]	296	1		T42	30		T43	21		T44	40
bite[7]	284	1		T75	13		T79	21		T107	13
bite[8]	470	1		T5	21		T46	13		T179	21
bite[9]	551	1		T32	46		T47	198		T122	61
bite[10]	707	1		T30	251		T174	13		T49	13
bite[11]	1130	1		T2	21		T126	592		T137	288
bite[12]	474	1		T11	59		T79	21		T110	22
bite[13]	777	1		T38	31		T32	42		T42	67
bite[14]	460	1		T32	30		T163	25		T102	21
bite[15]	500	1		T3	21		T7	13		T11	13
bite[16]	282	1		T14	21		T20	21		T40	53
bite[17]	313	1		T3	21		T28	6		T32	21
bite[18]	704	1		T110	26		T43	21		T173	21
bite[19]	118	1		T79	21		T40	21		T130	13
bite[20]	820	1		T5	42		T17	35		T136	48
bite[21]	448	1		T17	39		T33	21		T44	13
bite[22]	543	1		T1	13		T2	246		T28	63
bite[23]	222	1		T134	21		T178	13		T123	42
bite[24]	314	1		T14	26		T19	13		T42	13
bite[25]	308	1		T6	90		T139	21		T112	56
bite[26]	509	1		T77	13		T33	26		T139	21
bite[27]	682	1		T11	26		T30	63		T33	21
bite[28]	647	1		T17	39		T38	30		T149	78
bite[29]	473	1		T10	13		T32	21		T116	40
bite[30]	630	1		T39	78		T33	217		T47	139
bite[31]	496	1		T2	69		T14	21		T38	21
bite_0	5161	1		T1	8		T2	119		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	42700	1		T1	21		T2	716		T3	291
auto[1]	8466	1		T2	709		T3	24		T14	57

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	1318	1		T2	19		T5	19		T6	57
prescale[1]	742	1		T2	89		T3	19		T17	19
prescale[2]	941	1		T5	19		T6	19		T30	49
prescale[3]	919	1		T5	38		T14	40		T30	19
prescale[4]	1654	1		T5	37		T28	149		T32	64
prescale[5]	776	1		T29	2		T38	19		T30	132
prescale[6]	679	1		T2	2		T3	28		T5	43
prescale[7]	881	1		T2	133		T3	24		T11	78
prescale[8]	1243	1		T3	23		T35	9		T28	49
prescale[9]	869	1		T6	2		T175	58		T42	46
prescale[10]	802	1		T2	125		T3	14		T11	43
prescale[11]	644	1		T2	163		T5	2		T31	19
prescale[12]	1068	1		T2	67		T17	9		T20	23
prescale[13]	1211	1		T5	147		T29	2		T30	147
prescale[14]	589	1		T5	19		T30	2		T115	9
prescale[15]	934	1		T2	57		T3	42		T5	19
prescale[16]	1038	1		T2	9		T5	19		T28	143
prescale[17]	638	1		T5	19		T29	19		T38	59
prescale[18]	696	1		T11	23		T17	40		T28	2
prescale[19]	668	1		T2	9		T3	40		T14	19
prescale[20]	305	1		T38	19		T44	23		T126	28
prescale[21]	1106	1		T2	159		T14	42		T28	49
prescale[22]	974	1		T2	94		T14	19		T30	2
prescale[23]	522	1		T5	38		T6	148		T28	2
prescale[24]	742	1		T5	45		T32	157		T200	9
prescale[25]	445	1		T2	9		T11	48		T86	9
prescale[26]	688	1		T5	9		T37	9		T28	44
prescale[27]	795	1		T5	61		T14	59		T20	9
prescale[28]	539	1		T5	85		T31	87		T32	2
prescale[29]	780	1		T29	2		T38	28		T31	121
prescale[30]	965	1		T5	48		T6	2		T20	87
prescale[31]	1402	1		T2	38		T5	144		T11	24
prescale_0	23593	1		T1	21		T2	452		T3	125

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	38403	1		T1	21		T2	1099		T3	203
auto[1]	12763	1		T2	326		T3	112		T5	192

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	51166	1		T1	21		T2	1425		T3	315

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	30313	1		T1	1		T2	793		T3	247
wkup[1]	162	1		T2	21		T122	21		T151	30
wkup[2]	247	1		T17	21		T46	21		T139	8
wkup[3]	241	1		T17	35		T28	21		T38	33
wkup[4]	218	1		T2	21		T5	21		T32	36
wkup[5]	164	1		T5	21		T156	21		T87	21
wkup[6]	267	1		T38	30		T115	40		T156	21
wkup[7]	248	1		T20	21		T33	21		T142	30
wkup[8]	250	1		T29	21		T32	47		T185	15
wkup[9]	309	1		T5	34		T32	21		T33	21
wkup[10]	200	1		T2	30		T38	26		T33	21
wkup[11]	346	1		T2	21		T11	15		T32	30
wkup[12]	186	1		T19	15		T179	21		T167	15
wkup[13]	239	1		T32	42		T119	15		T179	21
wkup[14]	227	1		T2	21		T20	21		T32	42
wkup[15]	324	1		T6	35		T11	26		T28	21
wkup[16]	490	1		T29	21		T30	51		T31	42
wkup[17]	295	1		T30	26		T32	42		T156	35
wkup[18]	305	1		T2	21		T47	40		T130	15
wkup[19]	259	1		T28	21		T110	24		T46	15
wkup[20]	334	1		T28	21		T32	21		T126	26
wkup[21]	344	1		T28	21		T38	21		T33	21
wkup[22]	323	1		T5	21		T17	39		T79	21
wkup[23]	383	1		T2	21		T174	15		T33	26
wkup[24]	177	1		T2	15		T30	21		T115	26
wkup[25]	338	1		T6	26		T28	21		T32	21
wkup[26]	162	1		T33	21		T134	21		T140	21
wkup[27]	346	1		T2	30		T3	21		T6	30
wkup[28]	255	1		T5	21		T33	8		T110	21
wkup[29]	227	1		T5	26		T156	21		T126	21
wkup[30]	176	1		T2	56		T30	21		T47	21
wkup[31]	365	1		T2	21		T28	21		T32	21
wkup[32]	259	1		T1	15		T30	39		T32	21
wkup[33]	191	1		T47	21		T156	21		T151	15
wkup[34]	268	1		T46	21		T151	51		T83	21
wkup[35]	343	1		T2	59		T5	21		T6	21
wkup[36]	199	1		T77	15		T122	21		T126	43
wkup[37]	298	1		T6	21		T32	35		T39	21
wkup[38]	252	1		T30	42		T47	34		T102	15
wkup[39]	99	1		T30	21		T142	21		T160	21
wkup[40]	156	1		T14	21		T30	21		T122	21
wkup[41]	265	1		T5	21		T30	21		T33	21
wkup[42]	269	1		T2	35		T3	21		T149	21
wkup[43]	168	1		T2	42		T6	21		T131	21
wkup[44]	161	1		T47	21		T120	15		T173	15
wkup[45]	473	1		T7	15		T32	21		T33	30
wkup[46]	430	1		T2	26		T3	21		T33	21
wkup[47]	263	1		T2	21		T6	21		T79	21
wkup[48]	239	1		T5	21		T32	21		T183	15
wkup[49]	217	1		T20	30		T31	21		T32	21
wkup[50]	194	1		T30	21		T50	21		T139	21
wkup[51]	263	1		T10	15		T30	15		T31	30
wkup[52]	414	1		T28	47		T31	51		T107	15
wkup[53]	211	1		T28	15		T122	26		T81	21
wkup[54]	337	1		T28	21		T134	21		T43	21
wkup[55]	437	1		T2	21		T14	26		T28	30
wkup[56]	372	1		T2	26		T31	21		T33	26
wkup[57]	337	1		T5	21		T17	39		T31	21
wkup[58]	242	1		T14	21		T20	21		T40	21
wkup[59]	329	1		T11	21		T115	21		T33	21
wkup[60]	351	1		T5	21		T28	16		T75	15
wkup[61]	325	1		T6	30		T11	21		T40	21
wkup[62]	126	1		T2	6		T39	21		T142	21
wkup[63]	266	1		T2	21		T38	21		T33	47
wkup_0	3692	1		T1	5		T2	97		T3	5