Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.86 99.33 93.67 100.00 98.40 99.51 48.29


Total test records in report: 423
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T285 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.583305512 Jul 29 07:09:42 PM PDT 24 Jul 29 07:09:42 PM PDT 24 359764978 ps
T21 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2490566882 Jul 29 07:09:44 PM PDT 24 Jul 29 07:09:45 PM PDT 24 408211398 ps
T22 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3770384400 Jul 29 07:10:21 PM PDT 24 Jul 29 07:10:22 PM PDT 24 444998477 ps
T23 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1968814884 Jul 29 07:09:56 PM PDT 24 Jul 29 07:09:58 PM PDT 24 3688418295 ps
T286 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2056857414 Jul 29 07:09:43 PM PDT 24 Jul 29 07:09:44 PM PDT 24 368482542 ps
T25 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2711266 Jul 29 07:10:22 PM PDT 24 Jul 29 07:10:30 PM PDT 24 4340571710 ps
T287 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1595528908 Jul 29 07:09:45 PM PDT 24 Jul 29 07:09:47 PM PDT 24 554451297 ps
T288 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3297843277 Jul 29 07:10:27 PM PDT 24 Jul 29 07:10:27 PM PDT 24 479623496 ps
T51 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1876927800 Jul 29 07:09:44 PM PDT 24 Jul 29 07:09:45 PM PDT 24 493929172 ps
T289 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2032684800 Jul 29 07:09:53 PM PDT 24 Jul 29 07:09:54 PM PDT 24 470762992 ps
T67 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.568342962 Jul 29 07:09:50 PM PDT 24 Jul 29 07:09:52 PM PDT 24 1419270962 ps
T290 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3522979513 Jul 29 07:10:28 PM PDT 24 Jul 29 07:10:29 PM PDT 24 344013687 ps
T291 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3909712572 Jul 29 07:10:26 PM PDT 24 Jul 29 07:10:27 PM PDT 24 358550509 ps
T292 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3504624218 Jul 29 07:10:26 PM PDT 24 Jul 29 07:10:26 PM PDT 24 406787842 ps
T52 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1844357319 Jul 29 07:09:54 PM PDT 24 Jul 29 07:09:55 PM PDT 24 509612168 ps
T53 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2739265575 Jul 29 07:09:51 PM PDT 24 Jul 29 07:09:52 PM PDT 24 1112797164 ps
T26 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1150903829 Jul 29 07:09:54 PM PDT 24 Jul 29 07:10:00 PM PDT 24 7767008965 ps
T293 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2541006230 Jul 29 07:09:55 PM PDT 24 Jul 29 07:09:56 PM PDT 24 476617323 ps
T294 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2363392253 Jul 29 07:10:21 PM PDT 24 Jul 29 07:10:22 PM PDT 24 343149148 ps
T194 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3949800039 Jul 29 07:10:24 PM PDT 24 Jul 29 07:10:26 PM PDT 24 3872473233 ps
T68 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.428522985 Jul 29 07:09:54 PM PDT 24 Jul 29 07:09:56 PM PDT 24 986799065 ps
T197 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.775086262 Jul 29 07:09:54 PM PDT 24 Jul 29 07:09:56 PM PDT 24 4532263838 ps
T295 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1112072909 Jul 29 07:09:50 PM PDT 24 Jul 29 07:09:51 PM PDT 24 298752420 ps
T296 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.807629023 Jul 29 07:09:54 PM PDT 24 Jul 29 07:09:56 PM PDT 24 437845940 ps
T297 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.4125086725 Jul 29 07:10:28 PM PDT 24 Jul 29 07:10:29 PM PDT 24 300780724 ps
T298 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.356334088 Jul 29 07:10:27 PM PDT 24 Jul 29 07:10:28 PM PDT 24 440465456 ps
T54 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3373592648 Jul 29 07:09:54 PM PDT 24 Jul 29 07:10:01 PM PDT 24 13899364037 ps
T55 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2581442465 Jul 29 07:10:21 PM PDT 24 Jul 29 07:10:22 PM PDT 24 374152220 ps
T69 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2986726700 Jul 29 07:09:55 PM PDT 24 Jul 29 07:09:57 PM PDT 24 1267987054 ps
T299 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2925711833 Jul 29 07:10:26 PM PDT 24 Jul 29 07:10:27 PM PDT 24 440798460 ps
T70 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2217267623 Jul 29 07:09:55 PM PDT 24 Jul 29 07:09:58 PM PDT 24 2607301796 ps
T198 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.280441599 Jul 29 07:09:56 PM PDT 24 Jul 29 07:10:04 PM PDT 24 8030565770 ps
T300 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3665240585 Jul 29 07:09:46 PM PDT 24 Jul 29 07:09:48 PM PDT 24 395382558 ps
T71 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2737889886 Jul 29 07:09:52 PM PDT 24 Jul 29 07:09:55 PM PDT 24 2515516452 ps
T301 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1083388874 Jul 29 07:09:47 PM PDT 24 Jul 29 07:09:47 PM PDT 24 480205181 ps
T302 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1294546972 Jul 29 07:09:46 PM PDT 24 Jul 29 07:09:48 PM PDT 24 511700527 ps
T303 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1394244219 Jul 29 07:09:56 PM PDT 24 Jul 29 07:09:58 PM PDT 24 335852310 ps
T304 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1495441125 Jul 29 07:10:29 PM PDT 24 Jul 29 07:10:30 PM PDT 24 504564782 ps
T305 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.579499999 Jul 29 07:10:19 PM PDT 24 Jul 29 07:10:20 PM PDT 24 272454855 ps
T195 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3749435106 Jul 29 07:09:54 PM PDT 24 Jul 29 07:09:58 PM PDT 24 8444810194 ps
T56 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3407259297 Jul 29 07:09:46 PM PDT 24 Jul 29 07:09:48 PM PDT 24 519673816 ps
T306 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1502988894 Jul 29 07:10:20 PM PDT 24 Jul 29 07:10:22 PM PDT 24 539426691 ps
T307 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3502013767 Jul 29 07:10:30 PM PDT 24 Jul 29 07:10:31 PM PDT 24 293585764 ps
T308 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1907948246 Jul 29 07:10:22 PM PDT 24 Jul 29 07:10:24 PM PDT 24 8011900140 ps
T309 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2471859075 Jul 29 07:10:23 PM PDT 24 Jul 29 07:10:30 PM PDT 24 4188710335 ps
T310 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1577452029 Jul 29 07:09:53 PM PDT 24 Jul 29 07:09:54 PM PDT 24 536266789 ps
T311 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3165429371 Jul 29 07:10:30 PM PDT 24 Jul 29 07:10:31 PM PDT 24 462356091 ps
T312 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.995896693 Jul 29 07:09:54 PM PDT 24 Jul 29 07:10:02 PM PDT 24 4177881600 ps
T313 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1147018421 Jul 29 07:10:28 PM PDT 24 Jul 29 07:10:30 PM PDT 24 411330543 ps
T314 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2503950273 Jul 29 07:09:45 PM PDT 24 Jul 29 07:09:48 PM PDT 24 4182244068 ps
T315 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.89610561 Jul 29 07:09:53 PM PDT 24 Jul 29 07:09:55 PM PDT 24 539596670 ps
T57 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1980439177 Jul 29 07:09:44 PM PDT 24 Jul 29 07:09:45 PM PDT 24 285390797 ps
T316 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1380423839 Jul 29 07:09:46 PM PDT 24 Jul 29 07:09:47 PM PDT 24 517007839 ps
T317 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.4146391679 Jul 29 07:09:56 PM PDT 24 Jul 29 07:09:57 PM PDT 24 279759117 ps
T61 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3471395720 Jul 29 07:09:47 PM PDT 24 Jul 29 07:09:48 PM PDT 24 519702656 ps
T318 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1391173969 Jul 29 07:10:22 PM PDT 24 Jul 29 07:10:24 PM PDT 24 355955975 ps
T72 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.99168292 Jul 29 07:10:24 PM PDT 24 Jul 29 07:10:26 PM PDT 24 1733619568 ps
T319 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3128251854 Jul 29 07:09:46 PM PDT 24 Jul 29 07:09:47 PM PDT 24 389160403 ps
T73 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1219437260 Jul 29 07:09:52 PM PDT 24 Jul 29 07:09:53 PM PDT 24 2344082261 ps
T320 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3085457492 Jul 29 07:09:44 PM PDT 24 Jul 29 07:09:45 PM PDT 24 285850550 ps
T321 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.806468263 Jul 29 07:10:28 PM PDT 24 Jul 29 07:10:29 PM PDT 24 303401839 ps
T322 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.4117268272 Jul 29 07:09:46 PM PDT 24 Jul 29 07:09:47 PM PDT 24 502929406 ps
T323 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.605529341 Jul 29 07:09:46 PM PDT 24 Jul 29 07:09:51 PM PDT 24 2114366825 ps
T324 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3479044657 Jul 29 07:10:20 PM PDT 24 Jul 29 07:10:23 PM PDT 24 1246189367 ps
T325 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1679494498 Jul 29 07:10:29 PM PDT 24 Jul 29 07:10:30 PM PDT 24 361684425 ps
T65 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3014397819 Jul 29 07:09:50 PM PDT 24 Jul 29 07:09:51 PM PDT 24 331845436 ps
T326 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.938838235 Jul 29 07:09:53 PM PDT 24 Jul 29 07:09:54 PM PDT 24 468637653 ps
T327 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1463377045 Jul 29 07:10:24 PM PDT 24 Jul 29 07:10:26 PM PDT 24 758515905 ps
T328 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2255379074 Jul 29 07:09:53 PM PDT 24 Jul 29 07:09:55 PM PDT 24 487515804 ps
T329 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1994125639 Jul 29 07:09:46 PM PDT 24 Jul 29 07:09:47 PM PDT 24 370550394 ps
T62 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.822108936 Jul 29 07:09:55 PM PDT 24 Jul 29 07:09:56 PM PDT 24 478962685 ps
T63 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.4012602837 Jul 29 07:09:50 PM PDT 24 Jul 29 07:10:00 PM PDT 24 6489482447 ps
T330 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3784398243 Jul 29 07:09:54 PM PDT 24 Jul 29 07:09:59 PM PDT 24 8543265728 ps
T331 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2229983177 Jul 29 07:10:23 PM PDT 24 Jul 29 07:10:24 PM PDT 24 502096465 ps
T332 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3158048548 Jul 29 07:10:24 PM PDT 24 Jul 29 07:10:25 PM PDT 24 449277630 ps
T333 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3310844380 Jul 29 07:09:52 PM PDT 24 Jul 29 07:09:53 PM PDT 24 514748332 ps
T334 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1564407603 Jul 29 07:09:46 PM PDT 24 Jul 29 07:09:48 PM PDT 24 451480705 ps
T335 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1061648383 Jul 29 07:10:23 PM PDT 24 Jul 29 07:10:24 PM PDT 24 1178806381 ps
T336 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3407877109 Jul 29 07:09:44 PM PDT 24 Jul 29 07:09:46 PM PDT 24 1785963527 ps
T337 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2710864273 Jul 29 07:10:21 PM PDT 24 Jul 29 07:10:29 PM PDT 24 2595052043 ps
T338 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2472267845 Jul 29 07:09:45 PM PDT 24 Jul 29 07:09:48 PM PDT 24 390263801 ps
T339 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2822227983 Jul 29 07:09:46 PM PDT 24 Jul 29 07:09:47 PM PDT 24 393785262 ps
T66 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1267661381 Jul 29 07:09:45 PM PDT 24 Jul 29 07:09:47 PM PDT 24 1168283266 ps
T340 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3124175831 Jul 29 07:10:19 PM PDT 24 Jul 29 07:10:20 PM PDT 24 372122713 ps
T341 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.4176743148 Jul 29 07:10:21 PM PDT 24 Jul 29 07:10:22 PM PDT 24 376345308 ps
T342 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1316833585 Jul 29 07:09:54 PM PDT 24 Jul 29 07:09:56 PM PDT 24 671712778 ps
T343 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3863694258 Jul 29 07:10:27 PM PDT 24 Jul 29 07:10:28 PM PDT 24 371921623 ps
T344 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2128553169 Jul 29 07:09:55 PM PDT 24 Jul 29 07:09:57 PM PDT 24 310043054 ps
T345 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1758230444 Jul 29 07:09:54 PM PDT 24 Jul 29 07:09:56 PM PDT 24 1450058556 ps
T346 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3917696841 Jul 29 07:09:53 PM PDT 24 Jul 29 07:09:55 PM PDT 24 377074882 ps
T347 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3738377443 Jul 29 07:09:54 PM PDT 24 Jul 29 07:09:56 PM PDT 24 537196680 ps
T348 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2246510799 Jul 29 07:09:46 PM PDT 24 Jul 29 07:09:47 PM PDT 24 393742811 ps
T196 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1590770006 Jul 29 07:10:22 PM PDT 24 Jul 29 07:10:34 PM PDT 24 8255665276 ps
T349 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3183368943 Jul 29 07:10:20 PM PDT 24 Jul 29 07:10:21 PM PDT 24 305319725 ps
T350 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.4086092481 Jul 29 07:09:45 PM PDT 24 Jul 29 07:09:46 PM PDT 24 467927206 ps
T58 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.4033345052 Jul 29 07:09:54 PM PDT 24 Jul 29 07:09:56 PM PDT 24 563762986 ps
T351 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3554729552 Jul 29 07:10:19 PM PDT 24 Jul 29 07:10:21 PM PDT 24 576187336 ps
T352 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.964615551 Jul 29 07:10:28 PM PDT 24 Jul 29 07:10:29 PM PDT 24 297550045 ps
T353 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2226005588 Jul 29 07:10:20 PM PDT 24 Jul 29 07:10:21 PM PDT 24 478424668 ps
T354 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2635881906 Jul 29 07:09:54 PM PDT 24 Jul 29 07:09:56 PM PDT 24 525784578 ps
T199 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1687145008 Jul 29 07:09:56 PM PDT 24 Jul 29 07:09:59 PM PDT 24 3971115727 ps
T355 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.4053399884 Jul 29 07:09:54 PM PDT 24 Jul 29 07:09:55 PM PDT 24 502528568 ps
T64 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3427095416 Jul 29 07:10:18 PM PDT 24 Jul 29 07:10:19 PM PDT 24 348119848 ps
T356 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2093411366 Jul 29 07:10:21 PM PDT 24 Jul 29 07:10:25 PM PDT 24 1778642846 ps
T357 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3913998117 Jul 29 07:09:52 PM PDT 24 Jul 29 07:09:53 PM PDT 24 471452712 ps
T358 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2763410361 Jul 29 07:10:20 PM PDT 24 Jul 29 07:10:21 PM PDT 24 408512934 ps
T59 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.198129064 Jul 29 07:09:54 PM PDT 24 Jul 29 07:09:55 PM PDT 24 445834596 ps
T359 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3320190320 Jul 29 07:09:56 PM PDT 24 Jul 29 07:09:57 PM PDT 24 529666387 ps
T360 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.476620816 Jul 29 07:09:53 PM PDT 24 Jul 29 07:09:54 PM PDT 24 562721308 ps
T361 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3882667691 Jul 29 07:09:54 PM PDT 24 Jul 29 07:09:56 PM PDT 24 8724589945 ps
T362 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2835754784 Jul 29 07:10:26 PM PDT 24 Jul 29 07:10:27 PM PDT 24 336052909 ps
T363 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1039200694 Jul 29 07:10:27 PM PDT 24 Jul 29 07:10:28 PM PDT 24 507010959 ps
T364 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2495139390 Jul 29 07:09:53 PM PDT 24 Jul 29 07:09:54 PM PDT 24 455832696 ps
T365 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3783481403 Jul 29 07:09:52 PM PDT 24 Jul 29 07:09:53 PM PDT 24 520197423 ps
T366 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2897453909 Jul 29 07:10:29 PM PDT 24 Jul 29 07:10:30 PM PDT 24 378529369 ps
T367 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.764581234 Jul 29 07:10:24 PM PDT 24 Jul 29 07:10:25 PM PDT 24 378727533 ps
T368 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1124221180 Jul 29 07:09:54 PM PDT 24 Jul 29 07:09:55 PM PDT 24 515738214 ps
T369 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.346481018 Jul 29 07:09:45 PM PDT 24 Jul 29 07:09:46 PM PDT 24 453551253 ps
T370 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3031602866 Jul 29 07:10:09 PM PDT 24 Jul 29 07:10:10 PM PDT 24 1015294367 ps
T371 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3676300526 Jul 29 07:09:47 PM PDT 24 Jul 29 07:09:51 PM PDT 24 7940477888 ps
T372 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1566095902 Jul 29 07:10:27 PM PDT 24 Jul 29 07:10:28 PM PDT 24 525794273 ps
T373 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1704373923 Jul 29 07:10:23 PM PDT 24 Jul 29 07:10:26 PM PDT 24 1854307369 ps
T374 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.569645551 Jul 29 07:09:46 PM PDT 24 Jul 29 07:09:47 PM PDT 24 369605390 ps
T375 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1323985249 Jul 29 07:10:28 PM PDT 24 Jul 29 07:10:29 PM PDT 24 455590997 ps
T376 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.217183596 Jul 29 07:09:47 PM PDT 24 Jul 29 07:09:48 PM PDT 24 388695945 ps
T377 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1936043254 Jul 29 07:10:22 PM PDT 24 Jul 29 07:10:24 PM PDT 24 499772384 ps
T378 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2420817456 Jul 29 07:10:22 PM PDT 24 Jul 29 07:10:25 PM PDT 24 745167125 ps
T379 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2817765043 Jul 29 07:10:27 PM PDT 24 Jul 29 07:10:28 PM PDT 24 383104523 ps
T380 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3670306250 Jul 29 07:09:50 PM PDT 24 Jul 29 07:09:51 PM PDT 24 508355597 ps
T381 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1265888012 Jul 29 07:10:21 PM PDT 24 Jul 29 07:10:22 PM PDT 24 306555462 ps
T382 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.4249255148 Jul 29 07:10:29 PM PDT 24 Jul 29 07:10:30 PM PDT 24 319995966 ps
T383 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1566337695 Jul 29 07:10:25 PM PDT 24 Jul 29 07:10:27 PM PDT 24 502890626 ps
T384 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.860306208 Jul 29 07:10:21 PM PDT 24 Jul 29 07:10:34 PM PDT 24 8363511674 ps
T385 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3207740047 Jul 29 07:09:54 PM PDT 24 Jul 29 07:09:56 PM PDT 24 625799345 ps
T386 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1067963609 Jul 29 07:09:55 PM PDT 24 Jul 29 07:09:56 PM PDT 24 383027134 ps
T387 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1231847682 Jul 29 07:10:20 PM PDT 24 Jul 29 07:10:21 PM PDT 24 478056970 ps
T388 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1357525508 Jul 29 07:09:49 PM PDT 24 Jul 29 07:09:52 PM PDT 24 7200208577 ps
T389 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2231376921 Jul 29 07:09:54 PM PDT 24 Jul 29 07:09:55 PM PDT 24 441144645 ps
T390 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2664202485 Jul 29 07:09:47 PM PDT 24 Jul 29 07:09:54 PM PDT 24 4498209123 ps
T391 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.384263936 Jul 29 07:10:21 PM PDT 24 Jul 29 07:10:22 PM PDT 24 456424520 ps
T392 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2810432032 Jul 29 07:09:53 PM PDT 24 Jul 29 07:09:56 PM PDT 24 1183660188 ps
T393 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1235459289 Jul 29 07:09:56 PM PDT 24 Jul 29 07:09:59 PM PDT 24 612835897 ps
T394 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2737151595 Jul 29 07:09:50 PM PDT 24 Jul 29 07:09:53 PM PDT 24 500530077 ps
T395 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2736674084 Jul 29 07:09:53 PM PDT 24 Jul 29 07:09:56 PM PDT 24 1383529476 ps
T396 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.866773169 Jul 29 07:09:50 PM PDT 24 Jul 29 07:09:51 PM PDT 24 329124748 ps
T397 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3274272015 Jul 29 07:09:52 PM PDT 24 Jul 29 07:09:55 PM PDT 24 928090753 ps
T398 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.495120140 Jul 29 07:10:18 PM PDT 24 Jul 29 07:10:21 PM PDT 24 379923284 ps
T399 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.4003832521 Jul 29 07:09:43 PM PDT 24 Jul 29 07:10:01 PM PDT 24 6953268362 ps
T400 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.649490322 Jul 29 07:09:46 PM PDT 24 Jul 29 07:09:48 PM PDT 24 2413341558 ps
T401 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2090989989 Jul 29 07:09:54 PM PDT 24 Jul 29 07:10:07 PM PDT 24 7870227778 ps
T402 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2809052326 Jul 29 07:09:53 PM PDT 24 Jul 29 07:09:55 PM PDT 24 559226875 ps
T403 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3202980463 Jul 29 07:10:29 PM PDT 24 Jul 29 07:10:30 PM PDT 24 349661517 ps
T404 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3726917063 Jul 29 07:09:53 PM PDT 24 Jul 29 07:09:54 PM PDT 24 464231279 ps
T405 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.862072653 Jul 29 07:09:45 PM PDT 24 Jul 29 07:09:47 PM PDT 24 4344913633 ps
T60 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1240905843 Jul 29 07:10:20 PM PDT 24 Jul 29 07:10:21 PM PDT 24 488417903 ps
T406 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.338125846 Jul 29 07:09:54 PM PDT 24 Jul 29 07:09:55 PM PDT 24 384045830 ps
T407 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.643902362 Jul 29 07:10:29 PM PDT 24 Jul 29 07:10:30 PM PDT 24 323834174 ps
T408 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1605376518 Jul 29 07:09:43 PM PDT 24 Jul 29 07:09:44 PM PDT 24 330319766 ps
T409 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1736542013 Jul 29 07:09:56 PM PDT 24 Jul 29 07:09:58 PM PDT 24 538537258 ps
T410 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1313893462 Jul 29 07:09:53 PM PDT 24 Jul 29 07:09:55 PM PDT 24 2875443873 ps
T411 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1128488909 Jul 29 07:09:46 PM PDT 24 Jul 29 07:09:47 PM PDT 24 615192384 ps
T412 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2218847734 Jul 29 07:10:20 PM PDT 24 Jul 29 07:10:23 PM PDT 24 1581387398 ps
T413 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3589374806 Jul 29 07:10:24 PM PDT 24 Jul 29 07:10:25 PM PDT 24 310078941 ps
T414 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.79208096 Jul 29 07:10:22 PM PDT 24 Jul 29 07:10:24 PM PDT 24 365086059 ps
T415 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3064735870 Jul 29 07:09:49 PM PDT 24 Jul 29 07:09:50 PM PDT 24 368511906 ps
T416 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2563554469 Jul 29 07:09:53 PM PDT 24 Jul 29 07:09:54 PM PDT 24 456146953 ps
T417 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2547391210 Jul 29 07:10:23 PM PDT 24 Jul 29 07:10:25 PM PDT 24 452295614 ps
T418 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3352347731 Jul 29 07:09:46 PM PDT 24 Jul 29 07:09:47 PM PDT 24 515620877 ps
T419 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1203739056 Jul 29 07:10:19 PM PDT 24 Jul 29 07:10:20 PM PDT 24 464086711 ps
T420 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3732124325 Jul 29 07:09:54 PM PDT 24 Jul 29 07:09:56 PM PDT 24 376806468 ps
T421 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.915264897 Jul 29 07:09:56 PM PDT 24 Jul 29 07:09:57 PM PDT 24 527051300 ps
T422 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1693136458 Jul 29 07:10:25 PM PDT 24 Jul 29 07:10:26 PM PDT 24 422656583 ps
T423 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1334120034 Jul 29 07:09:50 PM PDT 24 Jul 29 07:09:52 PM PDT 24 339675231 ps

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1242940225
Short name T2
Test name
Test status
Simulation time 94171076259 ps
CPU time 952.96 seconds
Started Jul 29 05:38:28 PM PDT 24
Finished Jul 29 05:54:21 PM PDT 24
Peak memory 214820 kb
Host smart-561ffa10-77de-46b4-907b-5db7a56d6bee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242940225 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1242940225
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.4258447026
Short name T11
Test name
Test status
Simulation time 271103591206 ps
CPU time 57.26 seconds
Started Jul 29 05:38:09 PM PDT 24
Finished Jul 29 05:39:06 PM PDT 24
Peak memory 198104 kb
Host smart-6dbaba58-c039-406e-b473-35ec922b5dbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258447026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.4258447026
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.868390476
Short name T47
Test name
Test status
Simulation time 1113470532796 ps
CPU time 681.46 seconds
Started Jul 29 05:38:05 PM PDT 24
Finished Jul 29 05:49:27 PM PDT 24
Peak memory 205812 kb
Host smart-34697b62-1d98-4901-9d0c-24a21bd36849
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868390476 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.868390476
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2711266
Short name T25
Test name
Test status
Simulation time 4340571710 ps
CPU time 7.61 seconds
Started Jul 29 07:10:22 PM PDT 24
Finished Jul 29 07:10:30 PM PDT 24
Peak memory 198024 kb
Host smart-257cc823-cf06-4adf-b43a-e94bf1281e1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_i
ntg_err.2711266
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2861585293
Short name T97
Test name
Test status
Simulation time 63066664987 ps
CPU time 675.13 seconds
Started Jul 29 05:37:58 PM PDT 24
Finished Jul 29 05:49:14 PM PDT 24
Peak memory 212776 kb
Host smart-0540ed2d-1724-45af-9a82-093332bd5777
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861585293 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2861585293
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.563699764
Short name T40
Test name
Test status
Simulation time 16938050651 ps
CPU time 131.05 seconds
Started Jul 29 05:38:24 PM PDT 24
Finished Jul 29 05:40:35 PM PDT 24
Peak memory 198400 kb
Host smart-f5d6e80a-4d32-444c-96d4-1724279a5740
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563699764 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.563699764
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.4035095660
Short name T32
Test name
Test status
Simulation time 298912924183 ps
CPU time 636.45 seconds
Started Jul 29 05:37:50 PM PDT 24
Finished Jul 29 05:48:27 PM PDT 24
Peak memory 213428 kb
Host smart-9f26ad33-0e3b-4989-8781-f64d78729841
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035095660 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.4035095660
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.335191874
Short name T83
Test name
Test status
Simulation time 376863904632 ps
CPU time 704.41 seconds
Started Jul 29 05:38:38 PM PDT 24
Finished Jul 29 05:50:22 PM PDT 24
Peak memory 206188 kb
Host smart-dfd0f1df-7b43-4b28-87cf-2e6754438f52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335191874 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.335191874
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.1032575340
Short name T87
Test name
Test status
Simulation time 285543994922 ps
CPU time 560.79 seconds
Started Jul 29 05:38:33 PM PDT 24
Finished Jul 29 05:47:54 PM PDT 24
Peak memory 214692 kb
Host smart-12a57628-7d3e-4007-a50a-604adcdaff75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032575340 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.1032575340
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.993348054
Short name T103
Test name
Test status
Simulation time 61550287512 ps
CPU time 26 seconds
Started Jul 29 05:38:32 PM PDT 24
Finished Jul 29 05:38:58 PM PDT 24
Peak memory 184496 kb
Host smart-c582294d-734e-453d-9ecc-77f65fd3d516
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993348054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_a
ll.993348054
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.2234122256
Short name T88
Test name
Test status
Simulation time 80314015328 ps
CPU time 287.51 seconds
Started Jul 29 05:38:10 PM PDT 24
Finished Jul 29 05:42:58 PM PDT 24
Peak memory 208888 kb
Host smart-9d1a59bc-70f4-400f-8ad5-12155b469713
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234122256 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.2234122256
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.3398580290
Short name T4
Test name
Test status
Simulation time 7987474343 ps
CPU time 3.85 seconds
Started Jul 29 05:37:51 PM PDT 24
Finished Jul 29 05:37:55 PM PDT 24
Peak memory 215668 kb
Host smart-051c0d35-4eef-44ca-a287-d6f560b2a91a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398580290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.3398580290
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.523710913
Short name T100
Test name
Test status
Simulation time 144443713664 ps
CPU time 225.46 seconds
Started Jul 29 05:38:27 PM PDT 24
Finished Jul 29 05:42:13 PM PDT 24
Peak memory 198200 kb
Host smart-d08f55c1-6559-41c7-955f-b1e5e47f2db5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523710913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_a
ll.523710913
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.3347128639
Short name T137
Test name
Test status
Simulation time 60943017037 ps
CPU time 248.28 seconds
Started Jul 29 05:38:24 PM PDT 24
Finished Jul 29 05:42:33 PM PDT 24
Peak memory 207112 kb
Host smart-65b269a6-1ed7-493d-bc55-d2ac735de412
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347128639 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.3347128639
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.2744136780
Short name T109
Test name
Test status
Simulation time 178567205062 ps
CPU time 249.71 seconds
Started Jul 29 05:37:59 PM PDT 24
Finished Jul 29 05:42:09 PM PDT 24
Peak memory 184284 kb
Host smart-bdd4e2b7-c407-4a0f-8243-5fc2568f6975
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744136780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.2744136780
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.1655398604
Short name T33
Test name
Test status
Simulation time 224674067624 ps
CPU time 163.31 seconds
Started Jul 29 05:38:18 PM PDT 24
Finished Jul 29 05:41:01 PM PDT 24
Peak memory 199740 kb
Host smart-d6464dfa-268f-45c6-bd23-ad03309137b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655398604 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.1655398604
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.4185790374
Short name T84
Test name
Test status
Simulation time 301236964417 ps
CPU time 348.32 seconds
Started Jul 29 05:38:37 PM PDT 24
Finished Jul 29 05:44:25 PM PDT 24
Peak memory 201316 kb
Host smart-c1b37e20-73a7-421f-89a6-11361c448eea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185790374 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.4185790374
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.606117155
Short name T98
Test name
Test status
Simulation time 443597724867 ps
CPU time 163.47 seconds
Started Jul 29 05:37:52 PM PDT 24
Finished Jul 29 05:40:36 PM PDT 24
Peak memory 191892 kb
Host smart-22f9bcab-7fb6-4c3f-9a72-0368e73fabe7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606117155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_al
l.606117155
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.4005080486
Short name T85
Test name
Test status
Simulation time 96292174855 ps
CPU time 469.85 seconds
Started Jul 29 05:38:05 PM PDT 24
Finished Jul 29 05:45:55 PM PDT 24
Peak memory 206588 kb
Host smart-c62022b6-227d-4e0b-b662-479f277ca844
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005080486 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.4005080486
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1844357319
Short name T52
Test name
Test status
Simulation time 509612168 ps
CPU time 0.94 seconds
Started Jul 29 07:09:54 PM PDT 24
Finished Jul 29 07:09:55 PM PDT 24
Peak memory 193080 kb
Host smart-18651cf4-1485-4859-ad40-0dba3e0eb60a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844357319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1844357319
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.1267581855
Short name T112
Test name
Test status
Simulation time 72121113416 ps
CPU time 31.2 seconds
Started Jul 29 05:38:05 PM PDT 24
Finished Jul 29 05:38:36 PM PDT 24
Peak memory 184064 kb
Host smart-a07ba7f5-4b16-4d07-9a22-82aca317a2b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267581855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.1267581855
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1786386634
Short name T89
Test name
Test status
Simulation time 84046065015 ps
CPU time 332.18 seconds
Started Jul 29 05:37:57 PM PDT 24
Finished Jul 29 05:43:30 PM PDT 24
Peak memory 201568 kb
Host smart-ea79afb1-f9de-43d5-9ab3-60c0174b83af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786386634 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1786386634
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2848244507
Short name T139
Test name
Test status
Simulation time 101517659551 ps
CPU time 539.23 seconds
Started Jul 29 05:38:02 PM PDT 24
Finished Jul 29 05:47:01 PM PDT 24
Peak memory 204628 kb
Host smart-d32f1dee-261f-42e1-9177-48772e0d73d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848244507 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2848244507
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3256711129
Short name T38
Test name
Test status
Simulation time 375290354895 ps
CPU time 128.17 seconds
Started Jul 29 05:38:15 PM PDT 24
Finished Jul 29 05:40:23 PM PDT 24
Peak memory 192404 kb
Host smart-2ef6765f-b4e8-481b-af85-2afc3110e1e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256711129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3256711129
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.1844648798
Short name T118
Test name
Test status
Simulation time 70765447994 ps
CPU time 74 seconds
Started Jul 29 05:37:56 PM PDT 24
Finished Jul 29 05:39:10 PM PDT 24
Peak memory 191892 kb
Host smart-9c5a9737-9e92-4e7e-9623-12a7a8184f39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844648798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.1844648798
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.2175159149
Short name T126
Test name
Test status
Simulation time 361401065995 ps
CPU time 824.16 seconds
Started Jul 29 05:38:35 PM PDT 24
Finished Jul 29 05:52:19 PM PDT 24
Peak memory 214796 kb
Host smart-3ac18df8-c792-453e-80a6-0e94c1d888f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175159149 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.2175159149
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.4226142011
Short name T121
Test name
Test status
Simulation time 22164956799 ps
CPU time 231.46 seconds
Started Jul 29 05:38:32 PM PDT 24
Finished Jul 29 05:42:24 PM PDT 24
Peak memory 198404 kb
Host smart-8ebd72ae-53bf-4a87-ab19-d0342638f635
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226142011 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.4226142011
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.2762436553
Short name T160
Test name
Test status
Simulation time 101925526901 ps
CPU time 262.05 seconds
Started Jul 29 05:37:57 PM PDT 24
Finished Jul 29 05:42:20 PM PDT 24
Peak memory 213964 kb
Host smart-7402f539-3da0-45c6-af76-1e0ba4afef78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762436553 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2762436553
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.2731694565
Short name T127
Test name
Test status
Simulation time 418068469195 ps
CPU time 661.45 seconds
Started Jul 29 05:38:02 PM PDT 24
Finished Jul 29 05:49:03 PM PDT 24
Peak memory 197988 kb
Host smart-44f9d32d-0f1d-4859-8e95-205abdd4a5dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731694565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.2731694565
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1903617913
Short name T156
Test name
Test status
Simulation time 587022379799 ps
CPU time 665.67 seconds
Started Jul 29 05:37:56 PM PDT 24
Finished Jul 29 05:49:02 PM PDT 24
Peak memory 214348 kb
Host smart-bc10e829-0707-4600-9461-be1920f48199
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903617913 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1903617913
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.2118779135
Short name T108
Test name
Test status
Simulation time 63691984316 ps
CPU time 674.83 seconds
Started Jul 29 05:38:05 PM PDT 24
Finished Jul 29 05:49:20 PM PDT 24
Peak memory 213176 kb
Host smart-9a3bfd58-cc9e-4c09-8e9a-36baf1dcd721
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118779135 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.2118779135
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.740359340
Short name T104
Test name
Test status
Simulation time 151103829392 ps
CPU time 78.16 seconds
Started Jul 29 05:38:13 PM PDT 24
Finished Jul 29 05:39:32 PM PDT 24
Peak memory 198348 kb
Host smart-e9bc6ad4-b396-4387-a680-4c9a51cca38f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740359340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a
ll.740359340
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.3373182196
Short name T3
Test name
Test status
Simulation time 226540555968 ps
CPU time 352.91 seconds
Started Jul 29 05:37:55 PM PDT 24
Finished Jul 29 05:43:48 PM PDT 24
Peak memory 192948 kb
Host smart-1b6e429c-c9ee-4089-829c-45d0ef757006
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373182196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.3373182196
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.1704210479
Short name T155
Test name
Test status
Simulation time 98091562523 ps
CPU time 520.99 seconds
Started Jul 29 05:38:00 PM PDT 24
Finished Jul 29 05:46:41 PM PDT 24
Peak memory 212648 kb
Host smart-f4a35b80-a56a-4e79-8b66-a49089145bff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704210479 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.1704210479
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.4046273117
Short name T31
Test name
Test status
Simulation time 705058109429 ps
CPU time 546.58 seconds
Started Jul 29 05:38:06 PM PDT 24
Finished Jul 29 05:47:13 PM PDT 24
Peak memory 203748 kb
Host smart-5c1466c7-ee17-4715-b053-5591bec2492c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046273117 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.4046273117
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2652702879
Short name T140
Test name
Test status
Simulation time 168668196285 ps
CPU time 120.52 seconds
Started Jul 29 05:38:23 PM PDT 24
Finished Jul 29 05:40:24 PM PDT 24
Peak memory 192984 kb
Host smart-1ccd6766-4292-48f1-9ec4-93711e765614
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652702879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2652702879
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.2343582609
Short name T30
Test name
Test status
Simulation time 37010334156 ps
CPU time 291.98 seconds
Started Jul 29 05:38:31 PM PDT 24
Finished Jul 29 05:43:23 PM PDT 24
Peak memory 214004 kb
Host smart-eb012c6a-4266-466e-8706-7a359f7718db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343582609 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.2343582609
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.1257113909
Short name T96
Test name
Test status
Simulation time 30134865920 ps
CPU time 12.79 seconds
Started Jul 29 05:38:31 PM PDT 24
Finished Jul 29 05:38:44 PM PDT 24
Peak memory 192936 kb
Host smart-87853cbc-5e3d-43e6-b13a-9e7834b90feb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257113909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.1257113909
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.3347670454
Short name T147
Test name
Test status
Simulation time 467416005575 ps
CPU time 179.36 seconds
Started Jul 29 05:37:57 PM PDT 24
Finished Jul 29 05:40:56 PM PDT 24
Peak memory 192376 kb
Host smart-07b27400-3de3-45e0-9510-35d2976f2f09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347670454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.3347670454
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.2891478150
Short name T42
Test name
Test status
Simulation time 344435408527 ps
CPU time 468.39 seconds
Started Jul 29 05:38:33 PM PDT 24
Finished Jul 29 05:46:21 PM PDT 24
Peak memory 184384 kb
Host smart-65ea2bfa-d645-4d04-ad02-d630b799e843
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891478150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.2891478150
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1581844733
Short name T123
Test name
Test status
Simulation time 41049870673 ps
CPU time 4.54 seconds
Started Jul 29 05:38:38 PM PDT 24
Finished Jul 29 05:38:43 PM PDT 24
Peak memory 192752 kb
Host smart-459dd328-a9fb-49d4-aa8a-7dea96d737ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581844733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1581844733
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.956527654
Short name T131
Test name
Test status
Simulation time 222769604216 ps
CPU time 604.37 seconds
Started Jul 29 05:37:58 PM PDT 24
Finished Jul 29 05:48:03 PM PDT 24
Peak memory 214152 kb
Host smart-94750cb2-89f9-499c-b624-6693dea2d591
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956527654 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.956527654
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.615242729
Short name T19
Test name
Test status
Simulation time 363113355 ps
CPU time 1.05 seconds
Started Jul 29 05:38:34 PM PDT 24
Finished Jul 29 05:38:35 PM PDT 24
Peak memory 196640 kb
Host smart-289c4410-2280-4101-92fd-5934a47a467e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615242729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.615242729
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.1585939808
Short name T148
Test name
Test status
Simulation time 161598093755 ps
CPU time 211.8 seconds
Started Jul 29 05:37:56 PM PDT 24
Finished Jul 29 05:41:28 PM PDT 24
Peak memory 200436 kb
Host smart-27ffa537-c4f6-473e-a471-3b79a8461ef3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585939808 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.1585939808
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2372548095
Short name T82
Test name
Test status
Simulation time 97916045828 ps
CPU time 464.66 seconds
Started Jul 29 05:38:09 PM PDT 24
Finished Jul 29 05:45:54 PM PDT 24
Peak memory 203296 kb
Host smart-7d140017-994b-456f-a8e5-50b537923c96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372548095 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2372548095
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.589874936
Short name T5
Test name
Test status
Simulation time 928802368786 ps
CPU time 534.96 seconds
Started Jul 29 05:38:12 PM PDT 24
Finished Jul 29 05:47:07 PM PDT 24
Peak memory 204208 kb
Host smart-884a3c0c-6330-4b0b-9ee5-f729ddac360d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589874936 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.589874936
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.2528659640
Short name T162
Test name
Test status
Simulation time 484811479159 ps
CPU time 774.09 seconds
Started Jul 29 05:38:22 PM PDT 24
Finished Jul 29 05:51:16 PM PDT 24
Peak memory 192924 kb
Host smart-05495096-60c7-487a-ab94-259461d29d1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528659640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.2528659640
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.394997409
Short name T122
Test name
Test status
Simulation time 165409152231 ps
CPU time 923.87 seconds
Started Jul 29 05:38:32 PM PDT 24
Finished Jul 29 05:53:57 PM PDT 24
Peak memory 209688 kb
Host smart-537ef685-d6fe-4a08-97c9-8f25d9bdc72e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394997409 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.394997409
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.3780472945
Short name T46
Test name
Test status
Simulation time 75839508004 ps
CPU time 120.01 seconds
Started Jul 29 05:37:54 PM PDT 24
Finished Jul 29 05:39:54 PM PDT 24
Peak memory 191876 kb
Host smart-942d21a6-7007-4a35-9840-a1970b16211d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780472945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.3780472945
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.2655122935
Short name T164
Test name
Test status
Simulation time 331941304172 ps
CPU time 910.62 seconds
Started Jul 29 05:38:08 PM PDT 24
Finished Jul 29 05:53:19 PM PDT 24
Peak memory 214812 kb
Host smart-db8fa75a-140d-415c-a225-cfd3a65fee55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655122935 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.2655122935
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.587250563
Short name T92
Test name
Test status
Simulation time 46134329728 ps
CPU time 369.23 seconds
Started Jul 29 05:38:14 PM PDT 24
Finished Jul 29 05:44:23 PM PDT 24
Peak memory 214600 kb
Host smart-33094d36-f1d3-4185-a57d-1026e89fb4cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587250563 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.587250563
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.932001182
Short name T105
Test name
Test status
Simulation time 141245686836 ps
CPU time 238.85 seconds
Started Jul 29 05:38:27 PM PDT 24
Finished Jul 29 05:42:26 PM PDT 24
Peak memory 214796 kb
Host smart-4d3b3599-d2c3-46d0-9c3a-d0b2157581ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932001182 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.932001182
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.4094852649
Short name T44
Test name
Test status
Simulation time 137179233472 ps
CPU time 198.19 seconds
Started Jul 29 05:38:25 PM PDT 24
Finished Jul 29 05:41:44 PM PDT 24
Peak memory 192936 kb
Host smart-6ea1b5da-8135-47d0-9ba7-b3b34a704ab0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094852649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.4094852649
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.3853826763
Short name T95
Test name
Test status
Simulation time 138626610049 ps
CPU time 50.99 seconds
Started Jul 29 05:38:24 PM PDT 24
Finished Jul 29 05:39:15 PM PDT 24
Peak memory 192824 kb
Host smart-36bd7b84-c713-4fd1-98ee-42f0cb1f8565
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853826763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.3853826763
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.3759389172
Short name T129
Test name
Test status
Simulation time 155754347216 ps
CPU time 97.47 seconds
Started Jul 29 05:38:28 PM PDT 24
Finished Jul 29 05:40:06 PM PDT 24
Peak memory 198240 kb
Host smart-a80b6b41-9f8e-4b44-baae-db9278c245cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759389172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.3759389172
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1730330630
Short name T116
Test name
Test status
Simulation time 145579533947 ps
CPU time 14.22 seconds
Started Jul 29 05:38:12 PM PDT 24
Finished Jul 29 05:38:26 PM PDT 24
Peak memory 191808 kb
Host smart-3e1ba75a-8852-4e98-a879-450927d0d30e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730330630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1730330630
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3769033248
Short name T136
Test name
Test status
Simulation time 112671482646 ps
CPU time 20.19 seconds
Started Jul 29 05:38:34 PM PDT 24
Finished Jul 29 05:38:55 PM PDT 24
Peak memory 191764 kb
Host smart-665a95f0-f207-46af-aa1f-3797e3af0a0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769033248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3769033248
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.1523767155
Short name T115
Test name
Test status
Simulation time 104899732020 ps
CPU time 33.38 seconds
Started Jul 29 05:38:34 PM PDT 24
Finished Jul 29 05:39:07 PM PDT 24
Peak memory 191828 kb
Host smart-3ee07b35-1ae3-44d9-b2c2-ebf04f24e738
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523767155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.1523767155
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3643832861
Short name T144
Test name
Test status
Simulation time 80136257663 ps
CPU time 33.11 seconds
Started Jul 29 05:38:36 PM PDT 24
Finished Jul 29 05:39:09 PM PDT 24
Peak memory 191848 kb
Host smart-91b4af0f-75c4-4de6-aedf-23f4f28bcbe7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643832861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3643832861
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3978341155
Short name T179
Test name
Test status
Simulation time 343803036894 ps
CPU time 82.06 seconds
Started Jul 29 05:38:12 PM PDT 24
Finished Jul 29 05:39:34 PM PDT 24
Peak memory 191904 kb
Host smart-14fa469e-7cc9-4fc2-902e-b12d628b9e47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978341155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3978341155
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.623895192
Short name T128
Test name
Test status
Simulation time 54545280653 ps
CPU time 419.32 seconds
Started Jul 29 05:38:17 PM PDT 24
Finished Jul 29 05:45:17 PM PDT 24
Peak memory 200884 kb
Host smart-d669bc1d-bce4-4600-a95b-5ea2d4590917
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623895192 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.623895192
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.1961939261
Short name T151
Test name
Test status
Simulation time 97187422448 ps
CPU time 63.54 seconds
Started Jul 29 05:38:30 PM PDT 24
Finished Jul 29 05:39:34 PM PDT 24
Peak memory 192956 kb
Host smart-d444f044-1ba1-4e04-ac24-e4bd5765e7a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961939261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.1961939261
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.1924285957
Short name T110
Test name
Test status
Simulation time 78199009793 ps
CPU time 106.69 seconds
Started Jul 29 05:38:33 PM PDT 24
Finished Jul 29 05:40:20 PM PDT 24
Peak memory 192832 kb
Host smart-4c977357-0af2-463d-bd9e-98331b5c5da2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924285957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.1924285957
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.1191456912
Short name T142
Test name
Test status
Simulation time 94534085587 ps
CPU time 32.2 seconds
Started Jul 29 05:38:38 PM PDT 24
Finished Jul 29 05:39:10 PM PDT 24
Peak memory 192940 kb
Host smart-13c671a2-c49d-427a-87bf-c41925e4234d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191456912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.1191456912
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_jump.316499649
Short name T114
Test name
Test status
Simulation time 442249879 ps
CPU time 0.74 seconds
Started Jul 29 05:37:55 PM PDT 24
Finished Jul 29 05:37:56 PM PDT 24
Peak memory 196720 kb
Host smart-4206acaf-29b1-4d4c-8004-f7a82d753e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316499649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.316499649
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.2099376373
Short name T117
Test name
Test status
Simulation time 141546355392 ps
CPU time 200.3 seconds
Started Jul 29 05:38:05 PM PDT 24
Finished Jul 29 05:41:26 PM PDT 24
Peak memory 191860 kb
Host smart-488afc65-0b42-476a-8dae-553e1883ddd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099376373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.2099376373
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.1794822196
Short name T134
Test name
Test status
Simulation time 19338167063 ps
CPU time 208.66 seconds
Started Jul 29 05:38:15 PM PDT 24
Finished Jul 29 05:41:44 PM PDT 24
Peak memory 198364 kb
Host smart-9ad8a7e6-fbaa-4869-88f1-596b42400f5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794822196 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.1794822196
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.69322222
Short name T163
Test name
Test status
Simulation time 26334305135 ps
CPU time 275.58 seconds
Started Jul 29 05:38:22 PM PDT 24
Finished Jul 29 05:42:58 PM PDT 24
Peak memory 198636 kb
Host smart-b5c3babc-0a21-47aa-aea3-a6d05fdd3366
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69322222 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.69322222
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.674104107
Short name T99
Test name
Test status
Simulation time 368640896 ps
CPU time 0.83 seconds
Started Jul 29 05:38:31 PM PDT 24
Finished Jul 29 05:38:32 PM PDT 24
Peak memory 196596 kb
Host smart-557a7e05-ca75-4b81-9f84-4d221c39611e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674104107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.674104107
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.295499110
Short name T28
Test name
Test status
Simulation time 514112754654 ps
CPU time 791.71 seconds
Started Jul 29 05:38:41 PM PDT 24
Finished Jul 29 05:51:53 PM PDT 24
Peak memory 214820 kb
Host smart-bc3fd273-663c-4ff0-bb01-bca125b50f05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295499110 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.295499110
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.4148796290
Short name T106
Test name
Test status
Simulation time 218628228311 ps
CPU time 313.42 seconds
Started Jul 29 05:37:56 PM PDT 24
Finished Jul 29 05:43:10 PM PDT 24
Peak memory 198184 kb
Host smart-bbbce566-47e6-472f-acab-d8821b6c0236
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148796290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.4148796290
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2198070891
Short name T101
Test name
Test status
Simulation time 118273905060 ps
CPU time 187.48 seconds
Started Jul 29 05:38:00 PM PDT 24
Finished Jul 29 05:41:07 PM PDT 24
Peak memory 191728 kb
Host smart-c61be88d-7ab9-4b19-bd30-04b0944ebb3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198070891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2198070891
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3114628492
Short name T107
Test name
Test status
Simulation time 534727476 ps
CPU time 1.26 seconds
Started Jul 29 05:37:59 PM PDT 24
Finished Jul 29 05:38:00 PM PDT 24
Peak memory 196520 kb
Host smart-4aa1b135-e699-42c2-9525-cf96f3c36320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114628492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3114628492
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2675076585
Short name T124
Test name
Test status
Simulation time 519162400 ps
CPU time 1.33 seconds
Started Jul 29 05:38:23 PM PDT 24
Finished Jul 29 05:38:25 PM PDT 24
Peak memory 196640 kb
Host smart-e19f3015-4642-4d16-8f54-af34c6d09fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675076585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2675076585
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3951357288
Short name T145
Test name
Test status
Simulation time 392583279571 ps
CPU time 244.01 seconds
Started Jul 29 05:38:25 PM PDT 24
Finished Jul 29 05:42:29 PM PDT 24
Peak memory 191808 kb
Host smart-6864befd-11e0-43d1-b5cc-e1800aadf254
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951357288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3951357288
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.1986574075
Short name T165
Test name
Test status
Simulation time 312048806199 ps
CPU time 238.63 seconds
Started Jul 29 05:38:27 PM PDT 24
Finished Jul 29 05:42:26 PM PDT 24
Peak memory 191836 kb
Host smart-8bce7302-ac1a-48b7-abcf-19bd39d18283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986574075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.1986574075
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_jump.356615594
Short name T135
Test name
Test status
Simulation time 565622780 ps
CPU time 0.67 seconds
Started Jul 29 05:38:30 PM PDT 24
Finished Jul 29 05:38:31 PM PDT 24
Peak memory 196660 kb
Host smart-b8866cd6-2f74-403e-ad32-04b70e02f178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356615594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.356615594
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.2881531663
Short name T20
Test name
Test status
Simulation time 96842768879 ps
CPU time 38.3 seconds
Started Jul 29 05:38:34 PM PDT 24
Finished Jul 29 05:39:13 PM PDT 24
Peak memory 192948 kb
Host smart-9c839875-f173-44ed-a1cb-63db6e69bc51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881531663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.2881531663
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3851216864
Short name T125
Test name
Test status
Simulation time 342551841 ps
CPU time 0.86 seconds
Started Jul 29 05:38:34 PM PDT 24
Finished Jul 29 05:38:35 PM PDT 24
Peak memory 196716 kb
Host smart-668bf84e-472a-40d8-8d95-2c449369bea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851216864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3851216864
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.4073040721
Short name T113
Test name
Test status
Simulation time 398196025 ps
CPU time 0.83 seconds
Started Jul 29 05:38:37 PM PDT 24
Finished Jul 29 05:38:38 PM PDT 24
Peak memory 196688 kb
Host smart-15104fae-5e8b-4b08-9c8b-618124b3297e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073040721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.4073040721
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.101275221
Short name T79
Test name
Test status
Simulation time 114400741772 ps
CPU time 175.05 seconds
Started Jul 29 05:38:11 PM PDT 24
Finished Jul 29 05:41:07 PM PDT 24
Peak memory 192748 kb
Host smart-e8de3d09-6c06-4eb3-80ab-7112abc9e86c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101275221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_a
ll.101275221
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_jump.1891430431
Short name T141
Test name
Test status
Simulation time 550781156 ps
CPU time 0.71 seconds
Started Jul 29 05:38:13 PM PDT 24
Finished Jul 29 05:38:14 PM PDT 24
Peak memory 196600 kb
Host smart-b5a6085a-f70b-444b-8673-167c61a5e53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891430431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1891430431
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.2352539491
Short name T149
Test name
Test status
Simulation time 58719905643 ps
CPU time 66.69 seconds
Started Jul 29 05:38:25 PM PDT 24
Finished Jul 29 05:39:32 PM PDT 24
Peak memory 191876 kb
Host smart-37475e16-b184-4444-a730-4255684e02b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352539491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.2352539491
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1005400732
Short name T138
Test name
Test status
Simulation time 234248136036 ps
CPU time 305.26 seconds
Started Jul 29 05:38:24 PM PDT 24
Finished Jul 29 05:43:29 PM PDT 24
Peak memory 198160 kb
Host smart-e70b2bf4-e575-40a1-9d19-725be962ca00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005400732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1005400732
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_jump.325826938
Short name T130
Test name
Test status
Simulation time 403330263 ps
CPU time 0.64 seconds
Started Jul 29 05:38:28 PM PDT 24
Finished Jul 29 05:38:29 PM PDT 24
Peak memory 196624 kb
Host smart-b50ea831-4c1c-40be-bd68-43b6d71735dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325826938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.325826938
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2341831875
Short name T111
Test name
Test status
Simulation time 458129057 ps
CPU time 0.95 seconds
Started Jul 29 05:38:37 PM PDT 24
Finished Jul 29 05:38:38 PM PDT 24
Peak memory 196688 kb
Host smart-f904846a-47c5-4a91-b120-d2f90ba77291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341831875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2341831875
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.2069599491
Short name T10
Test name
Test status
Simulation time 605989336 ps
CPU time 0.82 seconds
Started Jul 29 05:38:11 PM PDT 24
Finished Jul 29 05:38:12 PM PDT 24
Peak memory 196684 kb
Host smart-59fe629e-c02e-40a8-8a24-0fcf9a931b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069599491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2069599491
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.300330694
Short name T159
Test name
Test status
Simulation time 73987469544 ps
CPU time 27.52 seconds
Started Jul 29 05:38:24 PM PDT 24
Finished Jul 29 05:38:52 PM PDT 24
Peak memory 191860 kb
Host smart-e654261e-5224-4ea7-baf8-e57b928c9f10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300330694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_a
ll.300330694
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.3529842482
Short name T102
Test name
Test status
Simulation time 38221288302 ps
CPU time 419.52 seconds
Started Jul 29 05:38:22 PM PDT 24
Finished Jul 29 05:45:21 PM PDT 24
Peak memory 206656 kb
Host smart-c6535e08-fb63-4180-807e-71f65f05c585
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529842482 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.3529842482
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.2162685081
Short name T75
Test name
Test status
Simulation time 565008588 ps
CPU time 0.81 seconds
Started Jul 29 05:38:23 PM PDT 24
Finished Jul 29 05:38:24 PM PDT 24
Peak memory 196644 kb
Host smart-686687a8-2cab-444e-ab20-5d246ce3552c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162685081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.2162685081
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.148430137
Short name T50
Test name
Test status
Simulation time 10848401967 ps
CPU time 71.42 seconds
Started Jul 29 05:38:28 PM PDT 24
Finished Jul 29 05:39:39 PM PDT 24
Peak memory 198420 kb
Host smart-c8705206-b638-40df-aba5-afcc79ad0f00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148430137 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.148430137
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.2987841979
Short name T6
Test name
Test status
Simulation time 25419328586 ps
CPU time 208.58 seconds
Started Jul 29 05:38:32 PM PDT 24
Finished Jul 29 05:42:01 PM PDT 24
Peak memory 214064 kb
Host smart-d9a5a4a2-a38a-4190-ba96-189a1a39674c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987841979 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.2987841979
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.1766916806
Short name T119
Test name
Test status
Simulation time 409246832 ps
CPU time 0.75 seconds
Started Jul 29 05:37:55 PM PDT 24
Finished Jul 29 05:37:56 PM PDT 24
Peak memory 196644 kb
Host smart-0cfad4d9-bb09-49fd-bea3-65594113c4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766916806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1766916806
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.1898695904
Short name T90
Test name
Test status
Simulation time 111033617808 ps
CPU time 245.02 seconds
Started Jul 29 05:37:58 PM PDT 24
Finished Jul 29 05:42:03 PM PDT 24
Peak memory 208956 kb
Host smart-cefeb8c1-2ff9-4179-9bfa-d39ddc295956
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898695904 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.1898695904
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3432184623
Short name T133
Test name
Test status
Simulation time 556324846 ps
CPU time 1.43 seconds
Started Jul 29 05:38:06 PM PDT 24
Finished Jul 29 05:38:07 PM PDT 24
Peak memory 196644 kb
Host smart-59875ca9-11c5-4b8c-866f-a96b13886025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432184623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3432184623
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.2701154986
Short name T173
Test name
Test status
Simulation time 101655009543 ps
CPU time 137.26 seconds
Started Jul 29 05:38:03 PM PDT 24
Finished Jul 29 05:40:21 PM PDT 24
Peak memory 198128 kb
Host smart-b14dbc09-194e-4dca-bdb0-486adb51ed24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701154986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.2701154986
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_jump.3777269352
Short name T132
Test name
Test status
Simulation time 508318591 ps
CPU time 0.79 seconds
Started Jul 29 05:38:11 PM PDT 24
Finished Jul 29 05:38:12 PM PDT 24
Peak memory 196612 kb
Host smart-068692f8-5806-4673-a15d-5bc40024759e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777269352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3777269352
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.4274323957
Short name T175
Test name
Test status
Simulation time 158205914063 ps
CPU time 90.29 seconds
Started Jul 29 05:38:35 PM PDT 24
Finished Jul 29 05:40:05 PM PDT 24
Peak memory 192796 kb
Host smart-58654147-6410-4fda-97ea-e14a049e3eb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274323957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.4274323957
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1024633295
Short name T143
Test name
Test status
Simulation time 169172107887 ps
CPU time 48.93 seconds
Started Jul 29 05:38:34 PM PDT 24
Finished Jul 29 05:39:23 PM PDT 24
Peak memory 192684 kb
Host smart-e90f32d9-c11d-4399-946e-2c86f3b27aa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024633295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1024633295
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2507813515
Short name T49
Test name
Test status
Simulation time 496535647 ps
CPU time 1.38 seconds
Started Jul 29 05:37:56 PM PDT 24
Finished Jul 29 05:37:58 PM PDT 24
Peak memory 196652 kb
Host smart-bc7b692c-13ae-41f4-a730-196e35b26b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507813515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2507813515
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.906471997
Short name T120
Test name
Test status
Simulation time 572205315 ps
CPU time 1.43 seconds
Started Jul 29 05:38:37 PM PDT 24
Finished Jul 29 05:38:38 PM PDT 24
Peak memory 196540 kb
Host smart-e7ff43af-eedf-4d33-9e89-1d65c4c1c9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906471997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.906471997
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1590770006
Short name T196
Test name
Test status
Simulation time 8255665276 ps
CPU time 11.6 seconds
Started Jul 29 07:10:22 PM PDT 24
Finished Jul 29 07:10:34 PM PDT 24
Peak memory 198332 kb
Host smart-49302d53-14ba-4ace-a857-bb70d9adaff4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590770006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.1590770006
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.aon_timer_jump.1666542048
Short name T167
Test name
Test status
Simulation time 483987311 ps
CPU time 0.79 seconds
Started Jul 29 05:37:58 PM PDT 24
Finished Jul 29 05:37:59 PM PDT 24
Peak memory 196672 kb
Host smart-5e858a5d-f635-46f3-84a4-83cd337fb815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666542048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1666542048
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_jump.780839745
Short name T168
Test name
Test status
Simulation time 434689578 ps
CPU time 1.24 seconds
Started Jul 29 05:38:01 PM PDT 24
Finished Jul 29 05:38:02 PM PDT 24
Peak memory 196572 kb
Host smart-287c105d-d0a8-45f6-8699-433c6d6571b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780839745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.780839745
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.1312668122
Short name T39
Test name
Test status
Simulation time 201359141158 ps
CPU time 149.96 seconds
Started Jul 29 05:38:05 PM PDT 24
Finished Jul 29 05:40:36 PM PDT 24
Peak memory 198224 kb
Host smart-34a3f1d9-6959-4609-97cc-4bc8eadf03cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312668122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.1312668122
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2023172563
Short name T158
Test name
Test status
Simulation time 99676242645 ps
CPU time 63.89 seconds
Started Jul 29 05:38:03 PM PDT 24
Finished Jul 29 05:39:07 PM PDT 24
Peak memory 191660 kb
Host smart-ac77f87a-f19f-4b41-a5d2-8e41421a6fc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023172563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2023172563
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_jump.407877643
Short name T185
Test name
Test status
Simulation time 549769377 ps
CPU time 1.05 seconds
Started Jul 29 05:38:04 PM PDT 24
Finished Jul 29 05:38:05 PM PDT 24
Peak memory 196708 kb
Host smart-5d8ad353-8eda-400a-aef4-b7c6b7e81388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407877643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.407877643
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.3617741935
Short name T181
Test name
Test status
Simulation time 420193395 ps
CPU time 0.75 seconds
Started Jul 29 05:38:09 PM PDT 24
Finished Jul 29 05:38:10 PM PDT 24
Peak memory 196816 kb
Host smart-6d15cb40-2608-4d34-be6d-93a5ca4d13a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617741935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.3617741935
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.361062758
Short name T191
Test name
Test status
Simulation time 475878670 ps
CPU time 0.84 seconds
Started Jul 29 05:38:17 PM PDT 24
Finished Jul 29 05:38:18 PM PDT 24
Peak memory 196572 kb
Host smart-f86a213d-91f7-4d19-94cd-3bab0c81bbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361062758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.361062758
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.2960294962
Short name T169
Test name
Test status
Simulation time 572897197 ps
CPU time 0.76 seconds
Started Jul 29 05:38:23 PM PDT 24
Finished Jul 29 05:38:24 PM PDT 24
Peak memory 196680 kb
Host smart-4348e023-7613-4d4c-ad0e-8ad491f0eab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960294962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2960294962
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.2661699882
Short name T178
Test name
Test status
Simulation time 590696623 ps
CPU time 0.71 seconds
Started Jul 29 05:38:27 PM PDT 24
Finished Jul 29 05:38:27 PM PDT 24
Peak memory 196576 kb
Host smart-953aca88-838e-4ec7-a342-5554fabb4e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661699882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.2661699882
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.2387392798
Short name T177
Test name
Test status
Simulation time 622654450 ps
CPU time 1.06 seconds
Started Jul 29 05:38:33 PM PDT 24
Finished Jul 29 05:38:34 PM PDT 24
Peak memory 196624 kb
Host smart-7276bbd5-4426-403a-9e22-29972fd8a2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387392798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.2387392798
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.2646296098
Short name T29
Test name
Test status
Simulation time 43188479196 ps
CPU time 320.75 seconds
Started Jul 29 05:38:38 PM PDT 24
Finished Jul 29 05:43:59 PM PDT 24
Peak memory 206776 kb
Host smart-b58d4913-654e-4143-98a2-8b9173939022
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646296098 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.2646296098
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3275140077
Short name T150
Test name
Test status
Simulation time 98202273487 ps
CPU time 53.12 seconds
Started Jul 29 05:38:01 PM PDT 24
Finished Jul 29 05:38:54 PM PDT 24
Peak memory 198184 kb
Host smart-95ae2c9e-9e51-41bf-8c00-c4ac1ccb3dd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275140077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3275140077
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_jump.1065774520
Short name T184
Test name
Test status
Simulation time 525121173 ps
CPU time 0.78 seconds
Started Jul 29 05:37:53 PM PDT 24
Finished Jul 29 05:37:53 PM PDT 24
Peak memory 196676 kb
Host smart-f563dc54-ddde-42ec-a74c-11ea547105af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065774520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.1065774520
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.3065198178
Short name T77
Test name
Test status
Simulation time 490718420 ps
CPU time 0.95 seconds
Started Jul 29 05:38:08 PM PDT 24
Finished Jul 29 05:38:09 PM PDT 24
Peak memory 196596 kb
Host smart-eb65c932-d828-4a30-833b-7fb6cb063c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065198178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3065198178
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3197996245
Short name T176
Test name
Test status
Simulation time 427176406 ps
CPU time 1.2 seconds
Started Jul 29 05:38:22 PM PDT 24
Finished Jul 29 05:38:23 PM PDT 24
Peak memory 196596 kb
Host smart-a82da90a-4dc8-4a05-97ea-9a9458068205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197996245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3197996245
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.677228356
Short name T161
Test name
Test status
Simulation time 442569543 ps
CPU time 0.69 seconds
Started Jul 29 05:38:12 PM PDT 24
Finished Jul 29 05:38:13 PM PDT 24
Peak memory 196556 kb
Host smart-44800699-94da-4a2c-b01f-bbb66808c477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677228356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.677228356
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.368225830
Short name T14
Test name
Test status
Simulation time 377953392414 ps
CPU time 548.46 seconds
Started Jul 29 05:38:15 PM PDT 24
Finished Jul 29 05:47:24 PM PDT 24
Peak memory 192816 kb
Host smart-0b70ae70-c321-458c-83a0-d2fb596d7b87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368225830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.368225830
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_jump.1747075334
Short name T183
Test name
Test status
Simulation time 400479725 ps
CPU time 0.76 seconds
Started Jul 29 05:38:22 PM PDT 24
Finished Jul 29 05:38:23 PM PDT 24
Peak memory 196600 kb
Host smart-ba757160-cfb5-4a8a-b341-60a4813eb084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747075334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.1747075334
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.2556474989
Short name T1
Test name
Test status
Simulation time 438107703 ps
CPU time 0.89 seconds
Started Jul 29 05:38:31 PM PDT 24
Finished Jul 29 05:38:32 PM PDT 24
Peak memory 196572 kb
Host smart-826e0959-6f56-4eb2-8022-f091669c3b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556474989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2556474989
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.871316191
Short name T171
Test name
Test status
Simulation time 146660806863 ps
CPU time 422.88 seconds
Started Jul 29 05:38:30 PM PDT 24
Finished Jul 29 05:45:33 PM PDT 24
Peak memory 211344 kb
Host smart-34d7f29e-68bb-4e7e-b4e6-7062410d4fec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871316191 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.871316191
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.3537275301
Short name T170
Test name
Test status
Simulation time 46826473129 ps
CPU time 37.56 seconds
Started Jul 29 05:38:33 PM PDT 24
Finished Jul 29 05:39:11 PM PDT 24
Peak memory 191840 kb
Host smart-3090b77b-c309-46f1-bcce-d2c8df78432b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537275301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.3537275301
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3831715881
Short name T48
Test name
Test status
Simulation time 490143942 ps
CPU time 1.23 seconds
Started Jul 29 05:37:58 PM PDT 24
Finished Jul 29 05:38:00 PM PDT 24
Peak memory 196556 kb
Host smart-3d77bbbc-3124-420a-952b-c4ddf78bf416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831715881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3831715881
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_jump.753936903
Short name T182
Test name
Test status
Simulation time 562168216 ps
CPU time 0.78 seconds
Started Jul 29 05:37:52 PM PDT 24
Finished Jul 29 05:37:53 PM PDT 24
Peak memory 196560 kb
Host smart-f3d52964-d63b-43ce-b4f6-f36387cbf163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753936903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.753936903
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.1450049013
Short name T190
Test name
Test status
Simulation time 494895926 ps
CPU time 0.97 seconds
Started Jul 29 05:38:04 PM PDT 24
Finished Jul 29 05:38:05 PM PDT 24
Peak memory 196580 kb
Host smart-2de2109f-ca8d-4872-a0bf-f6e8911ab5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450049013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1450049013
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.524934915
Short name T193
Test name
Test status
Simulation time 142473542660 ps
CPU time 213.54 seconds
Started Jul 29 05:38:11 PM PDT 24
Finished Jul 29 05:41:45 PM PDT 24
Peak memory 193700 kb
Host smart-90b79493-9369-46f6-a7ea-957405f40718
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524934915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_a
ll.524934915
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.254914097
Short name T17
Test name
Test status
Simulation time 126133052434 ps
CPU time 83.66 seconds
Started Jul 29 05:37:54 PM PDT 24
Finished Jul 29 05:39:18 PM PDT 24
Peak memory 192564 kb
Host smart-df42e60c-c136-4961-bf43-c591fdd0dab3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254914097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_al
l.254914097
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2569071973
Short name T81
Test name
Test status
Simulation time 85085055008 ps
CPU time 247.04 seconds
Started Jul 29 05:37:58 PM PDT 24
Finished Jul 29 05:42:05 PM PDT 24
Peak memory 208756 kb
Host smart-997aaeab-bf1e-4533-9a6f-afb77bcbe1dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569071973 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2569071973
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.4155078548
Short name T172
Test name
Test status
Simulation time 438705584 ps
CPU time 0.84 seconds
Started Jul 29 05:38:11 PM PDT 24
Finished Jul 29 05:38:12 PM PDT 24
Peak memory 196508 kb
Host smart-4798c4ad-739e-480f-8d58-42b74f76d01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155078548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.4155078548
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.3872555835
Short name T43
Test name
Test status
Simulation time 104511114392 ps
CPU time 139.69 seconds
Started Jul 29 05:38:26 PM PDT 24
Finished Jul 29 05:40:45 PM PDT 24
Peak memory 198212 kb
Host smart-22d9bf02-cd1f-45cf-888a-38b6eeea3c50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872555835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.3872555835
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_jump.1674507224
Short name T146
Test name
Test status
Simulation time 453016363 ps
CPU time 1.21 seconds
Started Jul 29 05:38:17 PM PDT 24
Finished Jul 29 05:38:18 PM PDT 24
Peak memory 196512 kb
Host smart-91364e4f-3441-434f-8de6-3c89e015d506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674507224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.1674507224
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1642165507
Short name T174
Test name
Test status
Simulation time 549779658 ps
CPU time 0.78 seconds
Started Jul 29 05:37:56 PM PDT 24
Finished Jul 29 05:37:57 PM PDT 24
Peak memory 196576 kb
Host smart-daec3b0d-f697-4d03-86ae-7829fe3149e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642165507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1642165507
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.944701195
Short name T34
Test name
Test status
Simulation time 95253681554 ps
CPU time 1018.39 seconds
Started Jul 29 05:38:25 PM PDT 24
Finished Jul 29 05:55:23 PM PDT 24
Peak memory 214848 kb
Host smart-6c262661-56b0-47b1-9d8b-8dc63129d360
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944701195 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.944701195
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.1437185342
Short name T189
Test name
Test status
Simulation time 360274746 ps
CPU time 0.86 seconds
Started Jul 29 05:38:25 PM PDT 24
Finished Jul 29 05:38:26 PM PDT 24
Peak memory 196612 kb
Host smart-c5909f40-723a-490b-b560-933fd0c64796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437185342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.1437185342
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.485639851
Short name T166
Test name
Test status
Simulation time 550904726 ps
CPU time 1.46 seconds
Started Jul 29 05:38:27 PM PDT 24
Finished Jul 29 05:38:29 PM PDT 24
Peak memory 196480 kb
Host smart-c887027f-e72a-457b-862c-9ae87cb09795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485639851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.485639851
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.2447905864
Short name T153
Test name
Test status
Simulation time 573300434 ps
CPU time 1.46 seconds
Started Jul 29 05:38:32 PM PDT 24
Finished Jul 29 05:38:33 PM PDT 24
Peak memory 196668 kb
Host smart-bf51a1b9-39b5-4b06-801f-03d5c6578b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447905864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2447905864
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.102103370
Short name T7
Test name
Test status
Simulation time 615681358 ps
CPU time 0.7 seconds
Started Jul 29 05:38:37 PM PDT 24
Finished Jul 29 05:38:38 PM PDT 24
Peak memory 196464 kb
Host smart-e12a4fcc-0c52-4095-8f90-0008eae7e59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102103370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.102103370
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.665899605
Short name T91
Test name
Test status
Simulation time 123389522621 ps
CPU time 445.52 seconds
Started Jul 29 05:38:35 PM PDT 24
Finished Jul 29 05:46:00 PM PDT 24
Peak memory 212824 kb
Host smart-db8ba062-5f15-4a62-9736-e2f436bf35eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665899605 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.665899605
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.346481018
Short name T369
Test name
Test status
Simulation time 453551253 ps
CPU time 0.83 seconds
Started Jul 29 07:09:45 PM PDT 24
Finished Jul 29 07:09:46 PM PDT 24
Peak memory 183732 kb
Host smart-33d2dda2-79d9-471e-a5ef-1ca307519674
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346481018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_al
iasing.346481018
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.4003832521
Short name T399
Test name
Test status
Simulation time 6953268362 ps
CPU time 17.86 seconds
Started Jul 29 07:09:43 PM PDT 24
Finished Jul 29 07:10:01 PM PDT 24
Peak memory 196760 kb
Host smart-b9fc33ff-8bf5-485f-8425-92d79ad80d22
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003832521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.4003832521
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3031602866
Short name T370
Test name
Test status
Simulation time 1015294367 ps
CPU time 0.9 seconds
Started Jul 29 07:10:09 PM PDT 24
Finished Jul 29 07:10:10 PM PDT 24
Peak memory 192180 kb
Host smart-f69ee033-5b13-457a-b15e-630daeda4ceb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031602866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.3031602866
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1564407603
Short name T334
Test name
Test status
Simulation time 451480705 ps
CPU time 1.26 seconds
Started Jul 29 07:09:46 PM PDT 24
Finished Jul 29 07:09:48 PM PDT 24
Peak memory 195704 kb
Host smart-22418aad-4b9e-40ab-b37f-e0d71b46a508
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564407603 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1564407603
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1876927800
Short name T51
Test name
Test status
Simulation time 493929172 ps
CPU time 1.19 seconds
Started Jul 29 07:09:44 PM PDT 24
Finished Jul 29 07:09:45 PM PDT 24
Peak memory 192064 kb
Host smart-2ba00a17-457c-4c52-a531-774656a5c9b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876927800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1876927800
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.217183596
Short name T376
Test name
Test status
Simulation time 388695945 ps
CPU time 1.15 seconds
Started Jul 29 07:09:47 PM PDT 24
Finished Jul 29 07:09:48 PM PDT 24
Peak memory 183764 kb
Host smart-434b8fd1-97f6-4123-be73-1b5c95aa224d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217183596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.217183596
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.583305512
Short name T285
Test name
Test status
Simulation time 359764978 ps
CPU time 0.67 seconds
Started Jul 29 07:09:42 PM PDT 24
Finished Jul 29 07:09:42 PM PDT 24
Peak memory 183672 kb
Host smart-93ff8e34-3686-4a55-a828-3e69c0c2cbe1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583305512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_ti
mer_mem_partial_access.583305512
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2822227983
Short name T339
Test name
Test status
Simulation time 393785262 ps
CPU time 1.12 seconds
Started Jul 29 07:09:46 PM PDT 24
Finished Jul 29 07:09:47 PM PDT 24
Peak memory 183696 kb
Host smart-1b724296-af93-4194-a9b0-0a63214d3f50
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822227983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2822227983
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.649490322
Short name T400
Test name
Test status
Simulation time 2413341558 ps
CPU time 2.11 seconds
Started Jul 29 07:09:46 PM PDT 24
Finished Jul 29 07:09:48 PM PDT 24
Peak memory 194068 kb
Host smart-5eb979f6-e1d6-4c4e-9d43-1de9c8160530
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649490322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.649490322
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3352347731
Short name T418
Test name
Test status
Simulation time 515620877 ps
CPU time 1.52 seconds
Started Jul 29 07:09:46 PM PDT 24
Finished Jul 29 07:09:47 PM PDT 24
Peak memory 198608 kb
Host smart-fbaddfe0-b05f-4d70-a4a8-b569ee0660cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352347731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3352347731
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.862072653
Short name T405
Test name
Test status
Simulation time 4344913633 ps
CPU time 1.57 seconds
Started Jul 29 07:09:45 PM PDT 24
Finished Jul 29 07:09:47 PM PDT 24
Peak memory 196856 kb
Host smart-2b862e79-cfbb-44c4-91b5-53f4ddcc4d04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862072653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_
intg_err.862072653
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2490566882
Short name T21
Test name
Test status
Simulation time 408211398 ps
CPU time 1.33 seconds
Started Jul 29 07:09:44 PM PDT 24
Finished Jul 29 07:09:45 PM PDT 24
Peak memory 193276 kb
Host smart-0f18d4c7-8a36-4d1f-86de-01def1ead3a6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490566882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.2490566882
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3407259297
Short name T56
Test name
Test status
Simulation time 519673816 ps
CPU time 2 seconds
Started Jul 29 07:09:46 PM PDT 24
Finished Jul 29 07:09:48 PM PDT 24
Peak memory 195932 kb
Host smart-1b877a9e-64f3-4504-9dab-a50d1b96d2f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407259297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.3407259297
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1267661381
Short name T66
Test name
Test status
Simulation time 1168283266 ps
CPU time 1.36 seconds
Started Jul 29 07:09:45 PM PDT 24
Finished Jul 29 07:09:47 PM PDT 24
Peak memory 193012 kb
Host smart-e2d0b565-3447-4b74-8506-532d0f3b6b5d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267661381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.1267661381
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3128251854
Short name T319
Test name
Test status
Simulation time 389160403 ps
CPU time 1.05 seconds
Started Jul 29 07:09:46 PM PDT 24
Finished Jul 29 07:09:47 PM PDT 24
Peak memory 196220 kb
Host smart-78115530-63fb-4578-9123-abf87d0742cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128251854 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3128251854
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1980439177
Short name T57
Test name
Test status
Simulation time 285390797 ps
CPU time 0.97 seconds
Started Jul 29 07:09:44 PM PDT 24
Finished Jul 29 07:09:45 PM PDT 24
Peak memory 193036 kb
Host smart-eee5725d-8466-43e0-b0e4-8882853bd112
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980439177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1980439177
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.4117268272
Short name T322
Test name
Test status
Simulation time 502929406 ps
CPU time 0.88 seconds
Started Jul 29 07:09:46 PM PDT 24
Finished Jul 29 07:09:47 PM PDT 24
Peak memory 183776 kb
Host smart-64b6ae61-08eb-4fc6-a1c5-6cc5c9ef01c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117268272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.4117268272
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.569645551
Short name T374
Test name
Test status
Simulation time 369605390 ps
CPU time 1.03 seconds
Started Jul 29 07:09:46 PM PDT 24
Finished Jul 29 07:09:47 PM PDT 24
Peak memory 183684 kb
Host smart-1570c158-c44e-49e1-a468-ad2479609049
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569645551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_ti
mer_mem_partial_access.569645551
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2056857414
Short name T286
Test name
Test status
Simulation time 368482542 ps
CPU time 1.08 seconds
Started Jul 29 07:09:43 PM PDT 24
Finished Jul 29 07:09:44 PM PDT 24
Peak memory 183692 kb
Host smart-40b951ac-4953-4bd6-a035-19fcd292ce3b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056857414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.2056857414
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3407877109
Short name T336
Test name
Test status
Simulation time 1785963527 ps
CPU time 1.59 seconds
Started Jul 29 07:09:44 PM PDT 24
Finished Jul 29 07:09:46 PM PDT 24
Peak memory 193024 kb
Host smart-4ab0f093-9b17-44a1-a0cb-6f5021e3a049
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407877109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.3407877109
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1294546972
Short name T302
Test name
Test status
Simulation time 511700527 ps
CPU time 2.22 seconds
Started Jul 29 07:09:46 PM PDT 24
Finished Jul 29 07:09:48 PM PDT 24
Peak memory 198632 kb
Host smart-338d276f-5b77-45c3-b71b-b601a7f64bf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294546972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1294546972
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3676300526
Short name T371
Test name
Test status
Simulation time 7940477888 ps
CPU time 4.19 seconds
Started Jul 29 07:09:47 PM PDT 24
Finished Jul 29 07:09:51 PM PDT 24
Peak memory 198356 kb
Host smart-ba6f37a8-5764-4364-bc02-d4bff91de3b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676300526 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.3676300526
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.4053399884
Short name T355
Test name
Test status
Simulation time 502528568 ps
CPU time 0.86 seconds
Started Jul 29 07:09:54 PM PDT 24
Finished Jul 29 07:09:55 PM PDT 24
Peak memory 195140 kb
Host smart-d5b3ce16-9858-4d3f-ba67-652b15b55052
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053399884 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.4053399884
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1124221180
Short name T368
Test name
Test status
Simulation time 515738214 ps
CPU time 0.68 seconds
Started Jul 29 07:09:54 PM PDT 24
Finished Jul 29 07:09:55 PM PDT 24
Peak memory 194044 kb
Host smart-7f720db8-a23c-49ac-bb2b-aa6f3b0dc3ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124221180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1124221180
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2563554469
Short name T416
Test name
Test status
Simulation time 456146953 ps
CPU time 1.17 seconds
Started Jul 29 07:09:53 PM PDT 24
Finished Jul 29 07:09:54 PM PDT 24
Peak memory 193196 kb
Host smart-513473c2-aa13-4119-8410-d82c98a65a5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563554469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2563554469
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.428522985
Short name T68
Test name
Test status
Simulation time 986799065 ps
CPU time 1.76 seconds
Started Jul 29 07:09:54 PM PDT 24
Finished Jul 29 07:09:56 PM PDT 24
Peak memory 183884 kb
Host smart-13c69100-9fe4-45ce-a004-04122c83f3af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428522985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon
_timer_same_csr_outstanding.428522985
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.89610561
Short name T315
Test name
Test status
Simulation time 539596670 ps
CPU time 1.9 seconds
Started Jul 29 07:09:53 PM PDT 24
Finished Jul 29 07:09:55 PM PDT 24
Peak memory 198776 kb
Host smart-1f725128-c39c-47e4-9be8-85f74517edc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89610561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.89610561
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1150903829
Short name T26
Test name
Test status
Simulation time 7767008965 ps
CPU time 5.93 seconds
Started Jul 29 07:09:54 PM PDT 24
Finished Jul 29 07:10:00 PM PDT 24
Peak memory 198248 kb
Host smart-4ee85301-d377-4f26-90f7-303b27d85939
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150903829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.1150903829
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3738377443
Short name T347
Test name
Test status
Simulation time 537196680 ps
CPU time 1.51 seconds
Started Jul 29 07:09:54 PM PDT 24
Finished Jul 29 07:09:56 PM PDT 24
Peak memory 196172 kb
Host smart-8fc3f031-9b2e-4c44-a2a2-9ad0a5669e9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738377443 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.3738377443
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2197327621
Short name T27
Test name
Test status
Simulation time 476459077 ps
CPU time 0.72 seconds
Started Jul 29 07:09:54 PM PDT 24
Finished Jul 29 07:09:55 PM PDT 24
Peak memory 192940 kb
Host smart-7c6b6bdd-f61f-47b3-b66b-8e9ca0d24702
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197327621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2197327621
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3726917063
Short name T404
Test name
Test status
Simulation time 464231279 ps
CPU time 0.63 seconds
Started Jul 29 07:09:53 PM PDT 24
Finished Jul 29 07:09:54 PM PDT 24
Peak memory 183700 kb
Host smart-70c7c56f-ac7a-4189-a2d5-068616de22b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726917063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.3726917063
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.568342962
Short name T67
Test name
Test status
Simulation time 1419270962 ps
CPU time 2.41 seconds
Started Jul 29 07:09:50 PM PDT 24
Finished Jul 29 07:09:52 PM PDT 24
Peak memory 193332 kb
Host smart-fa8b21fb-5ffe-4edc-93e8-cc9da2e35afb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568342962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon
_timer_same_csr_outstanding.568342962
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2635881906
Short name T354
Test name
Test status
Simulation time 525784578 ps
CPU time 2.25 seconds
Started Jul 29 07:09:54 PM PDT 24
Finished Jul 29 07:09:56 PM PDT 24
Peak memory 198812 kb
Host smart-aad2f01d-1cbf-45b8-9bbe-431d2103e996
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635881906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2635881906
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3784398243
Short name T330
Test name
Test status
Simulation time 8543265728 ps
CPU time 4.3 seconds
Started Jul 29 07:09:54 PM PDT 24
Finished Jul 29 07:09:59 PM PDT 24
Peak memory 198340 kb
Host smart-c0566352-2220-4846-aa3f-981a46d9516f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784398243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3784398243
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2255379074
Short name T328
Test name
Test status
Simulation time 487515804 ps
CPU time 1.33 seconds
Started Jul 29 07:09:53 PM PDT 24
Finished Jul 29 07:09:55 PM PDT 24
Peak memory 196888 kb
Host smart-83d6fb60-a507-40ea-8f9a-b109939c42e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255379074 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.2255379074
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2231376921
Short name T389
Test name
Test status
Simulation time 441144645 ps
CPU time 0.95 seconds
Started Jul 29 07:09:54 PM PDT 24
Finished Jul 29 07:09:55 PM PDT 24
Peak memory 193184 kb
Host smart-690d730b-fd59-460e-9eca-98ae131743bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231376921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2231376921
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.915264897
Short name T421
Test name
Test status
Simulation time 527051300 ps
CPU time 0.69 seconds
Started Jul 29 07:09:56 PM PDT 24
Finished Jul 29 07:09:57 PM PDT 24
Peak memory 193016 kb
Host smart-53281678-7544-48d1-bf30-1cd9bd5a8c1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915264897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.915264897
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2217267623
Short name T70
Test name
Test status
Simulation time 2607301796 ps
CPU time 3.2 seconds
Started Jul 29 07:09:55 PM PDT 24
Finished Jul 29 07:09:58 PM PDT 24
Peak memory 194640 kb
Host smart-bbde53c6-da94-4277-8dc0-4d3563003b85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217267623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.2217267623
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3732124325
Short name T420
Test name
Test status
Simulation time 376806468 ps
CPU time 1.75 seconds
Started Jul 29 07:09:54 PM PDT 24
Finished Jul 29 07:09:56 PM PDT 24
Peak memory 198356 kb
Host smart-80dd4513-bd5b-40c7-8ebf-2a23e91441f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732124325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3732124325
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.995896693
Short name T312
Test name
Test status
Simulation time 4177881600 ps
CPU time 6.8 seconds
Started Jul 29 07:09:54 PM PDT 24
Finished Jul 29 07:10:02 PM PDT 24
Peak memory 197836 kb
Host smart-43a2f498-aa1b-4cc4-b732-8a785d8d5051
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995896693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl
_intg_err.995896693
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.384263936
Short name T391
Test name
Test status
Simulation time 456424520 ps
CPU time 0.9 seconds
Started Jul 29 07:10:21 PM PDT 24
Finished Jul 29 07:10:22 PM PDT 24
Peak memory 196916 kb
Host smart-8e490cbf-7fff-4a16-ae2f-a4db0182b41d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384263936 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.384263936
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3670306250
Short name T380
Test name
Test status
Simulation time 508355597 ps
CPU time 1.05 seconds
Started Jul 29 07:09:50 PM PDT 24
Finished Jul 29 07:09:51 PM PDT 24
Peak memory 194052 kb
Host smart-ca31668b-c853-443a-845b-966a2c287e1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670306250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.3670306250
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.338125846
Short name T406
Test name
Test status
Simulation time 384045830 ps
CPU time 0.56 seconds
Started Jul 29 07:09:54 PM PDT 24
Finished Jul 29 07:09:55 PM PDT 24
Peak memory 183772 kb
Host smart-ef3171c3-b383-4b51-94e4-b5ca0cc2f18e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338125846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.338125846
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2218847734
Short name T412
Test name
Test status
Simulation time 1581387398 ps
CPU time 2.45 seconds
Started Jul 29 07:10:20 PM PDT 24
Finished Jul 29 07:10:23 PM PDT 24
Peak memory 193316 kb
Host smart-1aff4e1a-34ec-412b-b7bb-0cc42d442dae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218847734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.2218847734
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2128553169
Short name T344
Test name
Test status
Simulation time 310043054 ps
CPU time 2.23 seconds
Started Jul 29 07:09:55 PM PDT 24
Finished Jul 29 07:09:57 PM PDT 24
Peak memory 198620 kb
Host smart-9fc725c5-b460-429b-90cd-b2a39f880a8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128553169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2128553169
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1687145008
Short name T199
Test name
Test status
Simulation time 3971115727 ps
CPU time 3.49 seconds
Started Jul 29 07:09:56 PM PDT 24
Finished Jul 29 07:09:59 PM PDT 24
Peak memory 197512 kb
Host smart-886a1179-4ff5-4a69-a19a-2515973caaed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687145008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.1687145008
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1936043254
Short name T377
Test name
Test status
Simulation time 499772384 ps
CPU time 1.46 seconds
Started Jul 29 07:10:22 PM PDT 24
Finished Jul 29 07:10:24 PM PDT 24
Peak memory 196576 kb
Host smart-24f38ee5-a34a-46fa-a270-5047a87dfea1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936043254 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1936043254
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1231847682
Short name T387
Test name
Test status
Simulation time 478056970 ps
CPU time 1.24 seconds
Started Jul 29 07:10:20 PM PDT 24
Finished Jul 29 07:10:21 PM PDT 24
Peak memory 192992 kb
Host smart-ab04ae67-76f0-40dd-88f7-c341d2da987e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231847682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1231847682
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3183368943
Short name T349
Test name
Test status
Simulation time 305319725 ps
CPU time 0.63 seconds
Started Jul 29 07:10:20 PM PDT 24
Finished Jul 29 07:10:21 PM PDT 24
Peak memory 183760 kb
Host smart-e3c91d2b-c3a8-41e5-b604-1f3e2e3380e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183368943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.3183368943
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2710864273
Short name T337
Test name
Test status
Simulation time 2595052043 ps
CPU time 7.91 seconds
Started Jul 29 07:10:21 PM PDT 24
Finished Jul 29 07:10:29 PM PDT 24
Peak memory 195140 kb
Host smart-3c5157f7-61a5-48c9-b2a0-94c73bdc41d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710864273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2710864273
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.495120140
Short name T398
Test name
Test status
Simulation time 379923284 ps
CPU time 2.65 seconds
Started Jul 29 07:10:18 PM PDT 24
Finished Jul 29 07:10:21 PM PDT 24
Peak memory 198652 kb
Host smart-d449d71a-01a6-4566-a5c2-adf5efc2ff7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495120140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.495120140
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.860306208
Short name T384
Test name
Test status
Simulation time 8363511674 ps
CPU time 12.81 seconds
Started Jul 29 07:10:21 PM PDT 24
Finished Jul 29 07:10:34 PM PDT 24
Peak memory 198476 kb
Host smart-72f04dc3-612d-4f1e-a9ba-87304dcfb621
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860306208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.860306208
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1203739056
Short name T419
Test name
Test status
Simulation time 464086711 ps
CPU time 0.77 seconds
Started Jul 29 07:10:19 PM PDT 24
Finished Jul 29 07:10:20 PM PDT 24
Peak memory 195564 kb
Host smart-48c4f166-bdac-4769-bba1-246af7ae4d48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203739056 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1203739056
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1502988894
Short name T306
Test name
Test status
Simulation time 539426691 ps
CPU time 1.34 seconds
Started Jul 29 07:10:20 PM PDT 24
Finished Jul 29 07:10:22 PM PDT 24
Peak memory 192064 kb
Host smart-fe294a2c-6581-4abd-bad4-16cba4c1702d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502988894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1502988894
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2363392253
Short name T294
Test name
Test status
Simulation time 343149148 ps
CPU time 0.8 seconds
Started Jul 29 07:10:21 PM PDT 24
Finished Jul 29 07:10:22 PM PDT 24
Peak memory 183688 kb
Host smart-7e529f63-753a-4665-855b-8239c86b5d8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363392253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2363392253
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1704373923
Short name T373
Test name
Test status
Simulation time 1854307369 ps
CPU time 2.98 seconds
Started Jul 29 07:10:23 PM PDT 24
Finished Jul 29 07:10:26 PM PDT 24
Peak memory 193800 kb
Host smart-ab9cfd42-aa06-4cfe-9258-f266bad4ff05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704373923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1704373923
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.79208096
Short name T414
Test name
Test status
Simulation time 365086059 ps
CPU time 2.32 seconds
Started Jul 29 07:10:22 PM PDT 24
Finished Jul 29 07:10:24 PM PDT 24
Peak memory 198632 kb
Host smart-33f3fb85-2bea-4d05-bd8c-5469852de487
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79208096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.79208096
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1907948246
Short name T308
Test name
Test status
Simulation time 8011900140 ps
CPU time 2.62 seconds
Started Jul 29 07:10:22 PM PDT 24
Finished Jul 29 07:10:24 PM PDT 24
Peak memory 198620 kb
Host smart-2605e66e-e7b4-45ea-93b5-2da6ba2a4030
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907948246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.1907948246
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2547391210
Short name T417
Test name
Test status
Simulation time 452295614 ps
CPU time 1.38 seconds
Started Jul 29 07:10:23 PM PDT 24
Finished Jul 29 07:10:25 PM PDT 24
Peak memory 196596 kb
Host smart-60288f9a-87c2-4405-9588-1959e718f3d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547391210 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.2547391210
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3770384400
Short name T22
Test name
Test status
Simulation time 444998477 ps
CPU time 1.17 seconds
Started Jul 29 07:10:21 PM PDT 24
Finished Jul 29 07:10:22 PM PDT 24
Peak memory 193032 kb
Host smart-2d4b335a-b9c6-45c6-803c-3bc346fec481
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770384400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.3770384400
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.4176743148
Short name T341
Test name
Test status
Simulation time 376345308 ps
CPU time 0.88 seconds
Started Jul 29 07:10:21 PM PDT 24
Finished Jul 29 07:10:22 PM PDT 24
Peak memory 183792 kb
Host smart-dccc5c46-dc6a-46c1-bd87-177746f1393a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176743148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.4176743148
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1061648383
Short name T335
Test name
Test status
Simulation time 1178806381 ps
CPU time 0.99 seconds
Started Jul 29 07:10:23 PM PDT 24
Finished Jul 29 07:10:24 PM PDT 24
Peak memory 193320 kb
Host smart-1de9690a-06c6-420f-828f-bbe3cfc51c4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061648383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.1061648383
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1463377045
Short name T327
Test name
Test status
Simulation time 758515905 ps
CPU time 2.64 seconds
Started Jul 29 07:10:24 PM PDT 24
Finished Jul 29 07:10:26 PM PDT 24
Peak memory 198564 kb
Host smart-cae4b1c4-880a-4e32-beb4-bfa66f6b4b71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463377045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.1463377045
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2471859075
Short name T309
Test name
Test status
Simulation time 4188710335 ps
CPU time 6.69 seconds
Started Jul 29 07:10:23 PM PDT 24
Finished Jul 29 07:10:30 PM PDT 24
Peak memory 197872 kb
Host smart-611dc102-4c60-491c-9d88-4081dd8c2242
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471859075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.2471859075
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2229983177
Short name T331
Test name
Test status
Simulation time 502096465 ps
CPU time 0.89 seconds
Started Jul 29 07:10:23 PM PDT 24
Finished Jul 29 07:10:24 PM PDT 24
Peak memory 196516 kb
Host smart-9453157a-e2d8-447f-88f7-4ecb2a79b1c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229983177 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.2229983177
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1240905843
Short name T60
Test name
Test status
Simulation time 488417903 ps
CPU time 0.74 seconds
Started Jul 29 07:10:20 PM PDT 24
Finished Jul 29 07:10:21 PM PDT 24
Peak memory 193420 kb
Host smart-62231216-9fdf-4b67-ad25-b11d2969b63f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240905843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.1240905843
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.579499999
Short name T305
Test name
Test status
Simulation time 272454855 ps
CPU time 0.9 seconds
Started Jul 29 07:10:19 PM PDT 24
Finished Jul 29 07:10:20 PM PDT 24
Peak memory 193032 kb
Host smart-04580e04-9c79-412f-9e72-afbdafd055e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579499999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.579499999
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2093411366
Short name T356
Test name
Test status
Simulation time 1778642846 ps
CPU time 3.31 seconds
Started Jul 29 07:10:21 PM PDT 24
Finished Jul 29 07:10:25 PM PDT 24
Peak memory 193528 kb
Host smart-8191d14a-7d87-41ff-93a0-ccef7482a37a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093411366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.2093411366
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1391173969
Short name T318
Test name
Test status
Simulation time 355955975 ps
CPU time 1.91 seconds
Started Jul 29 07:10:22 PM PDT 24
Finished Jul 29 07:10:24 PM PDT 24
Peak memory 198572 kb
Host smart-2459ed90-9cbe-45dd-ab88-eda31b9fd6c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391173969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1391173969
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2226005588
Short name T353
Test name
Test status
Simulation time 478424668 ps
CPU time 0.96 seconds
Started Jul 29 07:10:20 PM PDT 24
Finished Jul 29 07:10:21 PM PDT 24
Peak memory 195572 kb
Host smart-2398d761-a6c2-42da-bc80-18d4a4cd5abb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226005588 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2226005588
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3427095416
Short name T64
Test name
Test status
Simulation time 348119848 ps
CPU time 0.66 seconds
Started Jul 29 07:10:18 PM PDT 24
Finished Jul 29 07:10:19 PM PDT 24
Peak memory 192140 kb
Host smart-9779a535-74a6-4540-b662-e5e720c0424e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427095416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3427095416
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2763410361
Short name T358
Test name
Test status
Simulation time 408512934 ps
CPU time 0.59 seconds
Started Jul 29 07:10:20 PM PDT 24
Finished Jul 29 07:10:21 PM PDT 24
Peak memory 183752 kb
Host smart-f2b6a7c8-9bfd-4f12-8d59-0a58d0ead3e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763410361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2763410361
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.99168292
Short name T72
Test name
Test status
Simulation time 1733619568 ps
CPU time 1.69 seconds
Started Jul 29 07:10:24 PM PDT 24
Finished Jul 29 07:10:26 PM PDT 24
Peak memory 191932 kb
Host smart-10c2afe3-ef84-4050-b820-58c257528fd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99168292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_
timer_same_csr_outstanding.99168292
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2420817456
Short name T378
Test name
Test status
Simulation time 745167125 ps
CPU time 2.19 seconds
Started Jul 29 07:10:22 PM PDT 24
Finished Jul 29 07:10:25 PM PDT 24
Peak memory 198612 kb
Host smart-57405554-2889-4336-9298-274899de72ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420817456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2420817456
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3949800039
Short name T194
Test name
Test status
Simulation time 3872473233 ps
CPU time 2.39 seconds
Started Jul 29 07:10:24 PM PDT 24
Finished Jul 29 07:10:26 PM PDT 24
Peak memory 197972 kb
Host smart-cd516b57-b97d-400f-93a5-581577164a09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949800039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3949800039
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3124175831
Short name T340
Test name
Test status
Simulation time 372122713 ps
CPU time 0.88 seconds
Started Jul 29 07:10:19 PM PDT 24
Finished Jul 29 07:10:20 PM PDT 24
Peak memory 195840 kb
Host smart-e0f10067-cc17-442e-8f67-2231ec485596
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124175831 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3124175831
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2581442465
Short name T55
Test name
Test status
Simulation time 374152220 ps
CPU time 0.82 seconds
Started Jul 29 07:10:21 PM PDT 24
Finished Jul 29 07:10:22 PM PDT 24
Peak memory 192984 kb
Host smart-820be0fb-43c9-4de3-a238-4a19cfa9637e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581442465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2581442465
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1265888012
Short name T381
Test name
Test status
Simulation time 306555462 ps
CPU time 0.84 seconds
Started Jul 29 07:10:21 PM PDT 24
Finished Jul 29 07:10:22 PM PDT 24
Peak memory 192952 kb
Host smart-e36d07bd-9468-4670-8836-07d4d1727ea2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265888012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.1265888012
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3479044657
Short name T324
Test name
Test status
Simulation time 1246189367 ps
CPU time 2.44 seconds
Started Jul 29 07:10:20 PM PDT 24
Finished Jul 29 07:10:23 PM PDT 24
Peak memory 193408 kb
Host smart-09a9488f-b99d-4d20-8521-4cc9a5a1c0c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479044657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.3479044657
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3554729552
Short name T351
Test name
Test status
Simulation time 576187336 ps
CPU time 1.65 seconds
Started Jul 29 07:10:19 PM PDT 24
Finished Jul 29 07:10:21 PM PDT 24
Peak memory 198644 kb
Host smart-1329f0a2-e685-4fcd-905d-0c6a2bf4a8c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554729552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3554729552
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3471395720
Short name T61
Test name
Test status
Simulation time 519702656 ps
CPU time 1.44 seconds
Started Jul 29 07:09:47 PM PDT 24
Finished Jul 29 07:09:48 PM PDT 24
Peak memory 194328 kb
Host smart-bb5659e1-5f0c-4192-8ac4-14a6a900597b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471395720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.3471395720
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1357525508
Short name T388
Test name
Test status
Simulation time 7200208577 ps
CPU time 3.58 seconds
Started Jul 29 07:09:49 PM PDT 24
Finished Jul 29 07:09:52 PM PDT 24
Peak memory 184132 kb
Host smart-596100df-2ac9-4805-b35e-23ce7ceb6485
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357525508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1357525508
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1128488909
Short name T411
Test name
Test status
Simulation time 615192384 ps
CPU time 0.8 seconds
Started Jul 29 07:09:46 PM PDT 24
Finished Jul 29 07:09:47 PM PDT 24
Peak memory 192076 kb
Host smart-bd272002-2d37-485e-b21d-dbb5f49d1ef8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128488909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.1128488909
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3665240585
Short name T300
Test name
Test status
Simulation time 395382558 ps
CPU time 1.3 seconds
Started Jul 29 07:09:46 PM PDT 24
Finished Jul 29 07:09:48 PM PDT 24
Peak memory 196588 kb
Host smart-dceac146-1489-4e8e-93d2-1d5693908ec8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665240585 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3665240585
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1605376518
Short name T408
Test name
Test status
Simulation time 330319766 ps
CPU time 1.04 seconds
Started Jul 29 07:09:43 PM PDT 24
Finished Jul 29 07:09:44 PM PDT 24
Peak memory 193216 kb
Host smart-a676b4b5-b333-4a35-bf29-d870c6b7ca4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605376518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1605376518
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2246510799
Short name T348
Test name
Test status
Simulation time 393742811 ps
CPU time 0.82 seconds
Started Jul 29 07:09:46 PM PDT 24
Finished Jul 29 07:09:47 PM PDT 24
Peak memory 183772 kb
Host smart-ed99027f-a14e-4156-b0db-5b68f570f402
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246510799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2246510799
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.4086092481
Short name T350
Test name
Test status
Simulation time 467927206 ps
CPU time 0.57 seconds
Started Jul 29 07:09:45 PM PDT 24
Finished Jul 29 07:09:46 PM PDT 24
Peak memory 183740 kb
Host smart-74966cdc-2b67-46e8-a5a7-451828148f12
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086092481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.4086092481
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1083388874
Short name T301
Test name
Test status
Simulation time 480205181 ps
CPU time 0.65 seconds
Started Jul 29 07:09:47 PM PDT 24
Finished Jul 29 07:09:47 PM PDT 24
Peak memory 183660 kb
Host smart-9b56cfba-8aa7-455b-ae08-58b7c6a42074
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083388874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1083388874
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.605529341
Short name T323
Test name
Test status
Simulation time 2114366825 ps
CPU time 5.11 seconds
Started Jul 29 07:09:46 PM PDT 24
Finished Jul 29 07:09:51 PM PDT 24
Peak memory 191992 kb
Host smart-064fdc17-cf5e-4551-b450-326ed5c8c6b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605529341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_
timer_same_csr_outstanding.605529341
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1595528908
Short name T287
Test name
Test status
Simulation time 554451297 ps
CPU time 1.47 seconds
Started Jul 29 07:09:45 PM PDT 24
Finished Jul 29 07:09:47 PM PDT 24
Peak memory 198648 kb
Host smart-fb468be5-a67b-4938-80ad-fd51df56906f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595528908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1595528908
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2503950273
Short name T314
Test name
Test status
Simulation time 4182244068 ps
CPU time 3.18 seconds
Started Jul 29 07:09:45 PM PDT 24
Finished Jul 29 07:09:48 PM PDT 24
Peak memory 197792 kb
Host smart-9b6f6eb3-7737-4fad-a0b3-4398b09c926c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503950273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2503950273
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3158048548
Short name T332
Test name
Test status
Simulation time 449277630 ps
CPU time 0.76 seconds
Started Jul 29 07:10:24 PM PDT 24
Finished Jul 29 07:10:25 PM PDT 24
Peak memory 183724 kb
Host smart-cde18233-f61a-4816-a6ff-d634c14dfbb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158048548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3158048548
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3589374806
Short name T413
Test name
Test status
Simulation time 310078941 ps
CPU time 0.63 seconds
Started Jul 29 07:10:24 PM PDT 24
Finished Jul 29 07:10:25 PM PDT 24
Peak memory 192944 kb
Host smart-b539a79f-a420-4d68-bb0f-6b937bc8efce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589374806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.3589374806
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1147018421
Short name T313
Test name
Test status
Simulation time 411330543 ps
CPU time 1.16 seconds
Started Jul 29 07:10:28 PM PDT 24
Finished Jul 29 07:10:30 PM PDT 24
Peak memory 192908 kb
Host smart-b966727c-5043-457e-9610-65bb66d47a6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147018421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1147018421
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.660565771
Short name T284
Test name
Test status
Simulation time 299488064 ps
CPU time 0.95 seconds
Started Jul 29 07:10:27 PM PDT 24
Finished Jul 29 07:10:28 PM PDT 24
Peak memory 183796 kb
Host smart-5a2b894f-3cbf-4ead-bc83-cefd7b5ea247
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660565771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.660565771
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3504624218
Short name T292
Test name
Test status
Simulation time 406787842 ps
CPU time 0.58 seconds
Started Jul 29 07:10:26 PM PDT 24
Finished Jul 29 07:10:26 PM PDT 24
Peak memory 193056 kb
Host smart-c7da04b3-6c19-403e-87c0-532f6b096f25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504624218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3504624218
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2925711833
Short name T299
Test name
Test status
Simulation time 440798460 ps
CPU time 0.85 seconds
Started Jul 29 07:10:26 PM PDT 24
Finished Jul 29 07:10:27 PM PDT 24
Peak memory 183784 kb
Host smart-a2e85bce-9f7f-4eae-8694-d0d90307ad6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925711833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2925711833
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3863694258
Short name T343
Test name
Test status
Simulation time 371921623 ps
CPU time 0.78 seconds
Started Jul 29 07:10:27 PM PDT 24
Finished Jul 29 07:10:28 PM PDT 24
Peak memory 183732 kb
Host smart-c597bbd3-5bea-48d0-9dd6-fb255f951d46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863694258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3863694258
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.643902362
Short name T407
Test name
Test status
Simulation time 323834174 ps
CPU time 0.77 seconds
Started Jul 29 07:10:29 PM PDT 24
Finished Jul 29 07:10:30 PM PDT 24
Peak memory 183796 kb
Host smart-180d88b1-48b3-4da9-9187-b79b762081c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643902362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.643902362
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.4249255148
Short name T382
Test name
Test status
Simulation time 319995966 ps
CPU time 0.75 seconds
Started Jul 29 07:10:29 PM PDT 24
Finished Jul 29 07:10:30 PM PDT 24
Peak memory 183784 kb
Host smart-3070e02b-24ad-4bfe-9b3b-b1c083267c4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249255148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.4249255148
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.356334088
Short name T298
Test name
Test status
Simulation time 440465456 ps
CPU time 1.17 seconds
Started Jul 29 07:10:27 PM PDT 24
Finished Jul 29 07:10:28 PM PDT 24
Peak memory 183884 kb
Host smart-da963eb1-bbc3-4662-94dc-b2b1d0ab8a1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356334088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.356334088
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3207740047
Short name T385
Test name
Test status
Simulation time 625799345 ps
CPU time 0.99 seconds
Started Jul 29 07:09:54 PM PDT 24
Finished Jul 29 07:09:56 PM PDT 24
Peak memory 194676 kb
Host smart-a77d2fe3-4eb0-475a-8b10-752259e210ad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207740047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.3207740047
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.4012602837
Short name T63
Test name
Test status
Simulation time 6489482447 ps
CPU time 9.91 seconds
Started Jul 29 07:09:50 PM PDT 24
Finished Jul 29 07:10:00 PM PDT 24
Peak memory 196332 kb
Host smart-1e07b3f5-39a3-41fe-9642-e3977ddb03b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012602837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.4012602837
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3274272015
Short name T397
Test name
Test status
Simulation time 928090753 ps
CPU time 2.1 seconds
Started Jul 29 07:09:52 PM PDT 24
Finished Jul 29 07:09:55 PM PDT 24
Peak memory 183744 kb
Host smart-661695b0-f88a-418b-bdaf-52356c149159
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274272015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.3274272015
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1334120034
Short name T423
Test name
Test status
Simulation time 339675231 ps
CPU time 1.21 seconds
Started Jul 29 07:09:50 PM PDT 24
Finished Jul 29 07:09:52 PM PDT 24
Peak memory 195960 kb
Host smart-0a2e60fa-b21e-4295-87c4-7bfac5c034eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334120034 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1334120034
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3014397819
Short name T65
Test name
Test status
Simulation time 331845436 ps
CPU time 0.7 seconds
Started Jul 29 07:09:50 PM PDT 24
Finished Jul 29 07:09:51 PM PDT 24
Peak memory 193144 kb
Host smart-035f5d3b-1ede-4486-8460-d1b083b2e12d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014397819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.3014397819
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1994125639
Short name T329
Test name
Test status
Simulation time 370550394 ps
CPU time 0.66 seconds
Started Jul 29 07:09:46 PM PDT 24
Finished Jul 29 07:09:47 PM PDT 24
Peak memory 183772 kb
Host smart-3d7b0f32-4b21-4de9-938b-fdcbbca98369
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994125639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1994125639
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3085457492
Short name T320
Test name
Test status
Simulation time 285850550 ps
CPU time 0.62 seconds
Started Jul 29 07:09:44 PM PDT 24
Finished Jul 29 07:09:45 PM PDT 24
Peak memory 183788 kb
Host smart-35285d96-df7d-4559-9e42-d18886ea8c7d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085457492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.3085457492
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1380423839
Short name T316
Test name
Test status
Simulation time 517007839 ps
CPU time 1.16 seconds
Started Jul 29 07:09:46 PM PDT 24
Finished Jul 29 07:09:47 PM PDT 24
Peak memory 183704 kb
Host smart-6ffed559-273f-4962-9362-fbb38e94c737
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380423839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.1380423839
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2737889886
Short name T71
Test name
Test status
Simulation time 2515516452 ps
CPU time 2.82 seconds
Started Jul 29 07:09:52 PM PDT 24
Finished Jul 29 07:09:55 PM PDT 24
Peak memory 195168 kb
Host smart-6cca691a-a2ce-46e6-aa27-f500dd731fef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737889886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.2737889886
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2472267845
Short name T338
Test name
Test status
Simulation time 390263801 ps
CPU time 2.53 seconds
Started Jul 29 07:09:45 PM PDT 24
Finished Jul 29 07:09:48 PM PDT 24
Peak memory 198624 kb
Host smart-58b5270e-6b49-49c9-9b54-b71c3315d5bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472267845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2472267845
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2664202485
Short name T390
Test name
Test status
Simulation time 4498209123 ps
CPU time 7.31 seconds
Started Jul 29 07:09:47 PM PDT 24
Finished Jul 29 07:09:54 PM PDT 24
Peak memory 197888 kb
Host smart-bddbe899-0915-4614-bd06-f10b9f31bdf7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664202485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.2664202485
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.964615551
Short name T352
Test name
Test status
Simulation time 297550045 ps
CPU time 0.71 seconds
Started Jul 29 07:10:28 PM PDT 24
Finished Jul 29 07:10:29 PM PDT 24
Peak memory 183776 kb
Host smart-1848cd70-a5db-49c8-a7f3-964f20e154df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964615551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.964615551
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3165429371
Short name T311
Test name
Test status
Simulation time 462356091 ps
CPU time 0.63 seconds
Started Jul 29 07:10:30 PM PDT 24
Finished Jul 29 07:10:31 PM PDT 24
Peak memory 183780 kb
Host smart-292acc4e-e25b-475e-95cc-bc7c13e10fdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165429371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3165429371
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3297843277
Short name T288
Test name
Test status
Simulation time 479623496 ps
CPU time 0.67 seconds
Started Jul 29 07:10:27 PM PDT 24
Finished Jul 29 07:10:27 PM PDT 24
Peak memory 183724 kb
Host smart-37a8bb07-f35e-40f4-8d48-1670c5935e32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297843277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3297843277
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1566337695
Short name T383
Test name
Test status
Simulation time 502890626 ps
CPU time 1.22 seconds
Started Jul 29 07:10:25 PM PDT 24
Finished Jul 29 07:10:27 PM PDT 24
Peak memory 183836 kb
Host smart-2e39c272-7d83-4910-8e45-6d96ab1c934c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566337695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.1566337695
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3909712572
Short name T291
Test name
Test status
Simulation time 358550509 ps
CPU time 0.69 seconds
Started Jul 29 07:10:26 PM PDT 24
Finished Jul 29 07:10:27 PM PDT 24
Peak memory 193040 kb
Host smart-893cbac5-21b0-4432-815e-98a66bf9aa33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909712572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.3909712572
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.764581234
Short name T367
Test name
Test status
Simulation time 378727533 ps
CPU time 0.66 seconds
Started Jul 29 07:10:24 PM PDT 24
Finished Jul 29 07:10:25 PM PDT 24
Peak memory 183812 kb
Host smart-7d8231f1-b694-44ee-b10d-93ee63d92503
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764581234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.764581234
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.806468263
Short name T321
Test name
Test status
Simulation time 303401839 ps
CPU time 0.61 seconds
Started Jul 29 07:10:28 PM PDT 24
Finished Jul 29 07:10:29 PM PDT 24
Peak memory 183764 kb
Host smart-bae66d9c-0949-4a49-b2df-4fbdcd4a94ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806468263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.806468263
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2897453909
Short name T366
Test name
Test status
Simulation time 378529369 ps
CPU time 1.15 seconds
Started Jul 29 07:10:29 PM PDT 24
Finished Jul 29 07:10:30 PM PDT 24
Peak memory 183804 kb
Host smart-a5d7bd28-9f11-4dbb-bbec-46dc32b3193b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897453909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2897453909
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2835754784
Short name T362
Test name
Test status
Simulation time 336052909 ps
CPU time 1.06 seconds
Started Jul 29 07:10:26 PM PDT 24
Finished Jul 29 07:10:27 PM PDT 24
Peak memory 183832 kb
Host smart-ad727546-df86-437d-a195-f3e51161928f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835754784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.2835754784
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1039200694
Short name T363
Test name
Test status
Simulation time 507010959 ps
CPU time 0.94 seconds
Started Jul 29 07:10:27 PM PDT 24
Finished Jul 29 07:10:28 PM PDT 24
Peak memory 183724 kb
Host smart-1ef09517-3d33-4e58-b582-a59e88ee96c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039200694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1039200694
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.4033345052
Short name T58
Test name
Test status
Simulation time 563762986 ps
CPU time 1.6 seconds
Started Jul 29 07:09:54 PM PDT 24
Finished Jul 29 07:09:56 PM PDT 24
Peak memory 193228 kb
Host smart-7502c279-3d64-48b4-bcd0-e8a922abc82c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033345052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.4033345052
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3373592648
Short name T54
Test name
Test status
Simulation time 13899364037 ps
CPU time 6.37 seconds
Started Jul 29 07:09:54 PM PDT 24
Finished Jul 29 07:10:01 PM PDT 24
Peak memory 192200 kb
Host smart-4f16af26-3fc7-4138-909a-6e2f952684eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373592648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.3373592648
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2739265575
Short name T53
Test name
Test status
Simulation time 1112797164 ps
CPU time 1 seconds
Started Jul 29 07:09:51 PM PDT 24
Finished Jul 29 07:09:52 PM PDT 24
Peak memory 193268 kb
Host smart-30b5e8dd-220b-430c-8cc7-5f4c1674c89f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739265575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.2739265575
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.476620816
Short name T360
Test name
Test status
Simulation time 562721308 ps
CPU time 0.94 seconds
Started Jul 29 07:09:53 PM PDT 24
Finished Jul 29 07:09:54 PM PDT 24
Peak memory 197476 kb
Host smart-3404b395-5ec5-4ed6-a051-45e74cdbf351
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476620816 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.476620816
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.866773169
Short name T396
Test name
Test status
Simulation time 329124748 ps
CPU time 0.85 seconds
Started Jul 29 07:09:50 PM PDT 24
Finished Jul 29 07:09:51 PM PDT 24
Peak memory 193320 kb
Host smart-5cd1cc82-ec25-4f3f-b1aa-a7ed9968d8f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866773169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.866773169
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1112072909
Short name T295
Test name
Test status
Simulation time 298752420 ps
CPU time 0.74 seconds
Started Jul 29 07:09:50 PM PDT 24
Finished Jul 29 07:09:51 PM PDT 24
Peak memory 193016 kb
Host smart-a22efb4b-2300-4743-851c-c6579b6cdcf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112072909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1112072909
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2032684800
Short name T289
Test name
Test status
Simulation time 470762992 ps
CPU time 1.17 seconds
Started Jul 29 07:09:53 PM PDT 24
Finished Jul 29 07:09:54 PM PDT 24
Peak memory 183688 kb
Host smart-98cbb65c-e6e5-49ca-b84d-99429a557aac
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032684800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.2032684800
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3064735870
Short name T415
Test name
Test status
Simulation time 368511906 ps
CPU time 0.63 seconds
Started Jul 29 07:09:49 PM PDT 24
Finished Jul 29 07:09:50 PM PDT 24
Peak memory 183680 kb
Host smart-aeb40291-e181-4db1-a465-3de5c6d48917
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064735870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.3064735870
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2986726700
Short name T69
Test name
Test status
Simulation time 1267987054 ps
CPU time 2.19 seconds
Started Jul 29 07:09:55 PM PDT 24
Finished Jul 29 07:09:57 PM PDT 24
Peak memory 193024 kb
Host smart-38aa7b77-3b0e-4d71-bc2b-1f38bf7195fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986726700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.2986726700
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3913998117
Short name T357
Test name
Test status
Simulation time 471452712 ps
CPU time 1.29 seconds
Started Jul 29 07:09:52 PM PDT 24
Finished Jul 29 07:09:53 PM PDT 24
Peak memory 198400 kb
Host smart-6d89b63f-b755-4cd9-b49c-df7cc3445327
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913998117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3913998117
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3749435106
Short name T195
Test name
Test status
Simulation time 8444810194 ps
CPU time 4.3 seconds
Started Jul 29 07:09:54 PM PDT 24
Finished Jul 29 07:09:58 PM PDT 24
Peak memory 198236 kb
Host smart-550ed920-3f1d-41e9-9c05-d1d18a9df63e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749435106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3749435106
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3522979513
Short name T290
Test name
Test status
Simulation time 344013687 ps
CPU time 0.63 seconds
Started Jul 29 07:10:28 PM PDT 24
Finished Jul 29 07:10:29 PM PDT 24
Peak memory 183792 kb
Host smart-8ecc9457-e744-47a4-ae11-571a915e405f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522979513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3522979513
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3202980463
Short name T403
Test name
Test status
Simulation time 349661517 ps
CPU time 0.83 seconds
Started Jul 29 07:10:29 PM PDT 24
Finished Jul 29 07:10:30 PM PDT 24
Peak memory 183784 kb
Host smart-857c0e5b-4f2e-4bba-91c9-6de99d0b7bd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202980463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.3202980463
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1566095902
Short name T372
Test name
Test status
Simulation time 525794273 ps
CPU time 0.73 seconds
Started Jul 29 07:10:27 PM PDT 24
Finished Jul 29 07:10:28 PM PDT 24
Peak memory 183784 kb
Host smart-83548f0a-6e1f-4ca9-8d54-7ff00a4d503b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566095902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1566095902
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1679494498
Short name T325
Test name
Test status
Simulation time 361684425 ps
CPU time 1.04 seconds
Started Jul 29 07:10:29 PM PDT 24
Finished Jul 29 07:10:30 PM PDT 24
Peak memory 193000 kb
Host smart-463ee6a3-e725-4918-83d3-2a7c673d5187
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679494498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1679494498
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1495441125
Short name T304
Test name
Test status
Simulation time 504564782 ps
CPU time 1.22 seconds
Started Jul 29 07:10:29 PM PDT 24
Finished Jul 29 07:10:30 PM PDT 24
Peak memory 183764 kb
Host smart-932429ad-f942-410f-8241-fbf60f8c401f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495441125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1495441125
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1693136458
Short name T422
Test name
Test status
Simulation time 422656583 ps
CPU time 0.64 seconds
Started Jul 29 07:10:25 PM PDT 24
Finished Jul 29 07:10:26 PM PDT 24
Peak memory 193016 kb
Host smart-25d17048-5cd1-4dee-8727-8a9aaa98b297
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693136458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1693136458
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1323985249
Short name T375
Test name
Test status
Simulation time 455590997 ps
CPU time 0.72 seconds
Started Jul 29 07:10:28 PM PDT 24
Finished Jul 29 07:10:29 PM PDT 24
Peak memory 183804 kb
Host smart-9aa22327-0db6-4035-b3f9-629bbe5f76de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323985249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1323985249
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2817765043
Short name T379
Test name
Test status
Simulation time 383104523 ps
CPU time 0.63 seconds
Started Jul 29 07:10:27 PM PDT 24
Finished Jul 29 07:10:28 PM PDT 24
Peak memory 192984 kb
Host smart-ef293d33-d2fa-4acb-855c-c1ed68b940b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817765043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.2817765043
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3502013767
Short name T307
Test name
Test status
Simulation time 293585764 ps
CPU time 0.64 seconds
Started Jul 29 07:10:30 PM PDT 24
Finished Jul 29 07:10:31 PM PDT 24
Peak memory 192980 kb
Host smart-3105a90b-a076-4e69-a7d3-286c79f91765
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502013767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3502013767
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.4125086725
Short name T297
Test name
Test status
Simulation time 300780724 ps
CPU time 0.61 seconds
Started Jul 29 07:10:28 PM PDT 24
Finished Jul 29 07:10:29 PM PDT 24
Peak memory 192984 kb
Host smart-844a74ee-e2fd-4bcb-bdc6-b27807a9d3e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125086725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.4125086725
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2809052326
Short name T402
Test name
Test status
Simulation time 559226875 ps
CPU time 1.58 seconds
Started Jul 29 07:09:53 PM PDT 24
Finished Jul 29 07:09:55 PM PDT 24
Peak memory 196552 kb
Host smart-fb3a53d2-04f3-4945-bc5e-d438aa7ead82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809052326 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.2809052326
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3310844380
Short name T333
Test name
Test status
Simulation time 514748332 ps
CPU time 1.28 seconds
Started Jul 29 07:09:52 PM PDT 24
Finished Jul 29 07:09:53 PM PDT 24
Peak memory 183728 kb
Host smart-5941c1ad-c523-4a0e-ae21-4285116f17e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310844380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3310844380
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1219437260
Short name T73
Test name
Test status
Simulation time 2344082261 ps
CPU time 1.21 seconds
Started Jul 29 07:09:52 PM PDT 24
Finished Jul 29 07:09:53 PM PDT 24
Peak memory 193964 kb
Host smart-06f4e810-afde-4f8b-ae0f-ecce95e31033
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219437260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.1219437260
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1394244219
Short name T303
Test name
Test status
Simulation time 335852310 ps
CPU time 1.99 seconds
Started Jul 29 07:09:56 PM PDT 24
Finished Jul 29 07:09:58 PM PDT 24
Peak memory 198660 kb
Host smart-43a18031-380c-4ce4-9cf6-90a3e5e194cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394244219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1394244219
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.280441599
Short name T198
Test name
Test status
Simulation time 8030565770 ps
CPU time 7.88 seconds
Started Jul 29 07:09:56 PM PDT 24
Finished Jul 29 07:10:04 PM PDT 24
Peak memory 198376 kb
Host smart-1835b812-617b-449b-88db-6b43e95291f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280441599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.280441599
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3917696841
Short name T346
Test name
Test status
Simulation time 377074882 ps
CPU time 0.98 seconds
Started Jul 29 07:09:53 PM PDT 24
Finished Jul 29 07:09:55 PM PDT 24
Peak memory 197120 kb
Host smart-3fe9245b-baae-448f-b611-cefb5b20d81b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917696841 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3917696841
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1067963609
Short name T386
Test name
Test status
Simulation time 383027134 ps
CPU time 1.09 seconds
Started Jul 29 07:09:55 PM PDT 24
Finished Jul 29 07:09:56 PM PDT 24
Peak memory 194044 kb
Host smart-bfd56150-71c1-43d2-84a1-173b27be5369
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067963609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1067963609
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3783481403
Short name T365
Test name
Test status
Simulation time 520197423 ps
CPU time 0.74 seconds
Started Jul 29 07:09:52 PM PDT 24
Finished Jul 29 07:09:53 PM PDT 24
Peak memory 183752 kb
Host smart-6b490f71-0cb2-4962-a5d1-f010f786b88a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783481403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3783481403
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2736674084
Short name T395
Test name
Test status
Simulation time 1383529476 ps
CPU time 2.42 seconds
Started Jul 29 07:09:53 PM PDT 24
Finished Jul 29 07:09:56 PM PDT 24
Peak memory 193856 kb
Host smart-07e02bab-4933-4847-833b-c63324ff9c9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736674084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2736674084
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1736542013
Short name T409
Test name
Test status
Simulation time 538537258 ps
CPU time 2.08 seconds
Started Jul 29 07:09:56 PM PDT 24
Finished Jul 29 07:09:58 PM PDT 24
Peak memory 198628 kb
Host smart-c0bafa21-e542-4cde-9ef6-402f09aa7614
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736542013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1736542013
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1968814884
Short name T23
Test name
Test status
Simulation time 3688418295 ps
CPU time 2.35 seconds
Started Jul 29 07:09:56 PM PDT 24
Finished Jul 29 07:09:58 PM PDT 24
Peak memory 197900 kb
Host smart-25015de9-1f9d-4a65-8e4e-2775f46fa0ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968814884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.1968814884
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2495139390
Short name T364
Test name
Test status
Simulation time 455832696 ps
CPU time 1.29 seconds
Started Jul 29 07:09:53 PM PDT 24
Finished Jul 29 07:09:54 PM PDT 24
Peak memory 196300 kb
Host smart-e34ede30-438f-4463-8aac-af355edd3fd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495139390 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.2495139390
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.822108936
Short name T62
Test name
Test status
Simulation time 478962685 ps
CPU time 0.85 seconds
Started Jul 29 07:09:55 PM PDT 24
Finished Jul 29 07:09:56 PM PDT 24
Peak memory 193420 kb
Host smart-7c60cefb-5343-4493-a799-1dd367db69d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822108936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.822108936
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.4146391679
Short name T317
Test name
Test status
Simulation time 279759117 ps
CPU time 0.74 seconds
Started Jul 29 07:09:56 PM PDT 24
Finished Jul 29 07:09:57 PM PDT 24
Peak memory 183768 kb
Host smart-49a80296-8e6b-4968-bb88-c5093c05681c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146391679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.4146391679
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1758230444
Short name T345
Test name
Test status
Simulation time 1450058556 ps
CPU time 1.61 seconds
Started Jul 29 07:09:54 PM PDT 24
Finished Jul 29 07:09:56 PM PDT 24
Peak memory 193480 kb
Host smart-85110f9e-07e5-4db8-b252-d8473b4d201e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758230444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.1758230444
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1235459289
Short name T393
Test name
Test status
Simulation time 612835897 ps
CPU time 3.07 seconds
Started Jul 29 07:09:56 PM PDT 24
Finished Jul 29 07:09:59 PM PDT 24
Peak memory 198672 kb
Host smart-eea1f085-32ef-430b-a0f6-c21dc1a59ece
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235459289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.1235459289
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3882667691
Short name T361
Test name
Test status
Simulation time 8724589945 ps
CPU time 2.14 seconds
Started Jul 29 07:09:54 PM PDT 24
Finished Jul 29 07:09:56 PM PDT 24
Peak memory 198288 kb
Host smart-3269c17d-f9f3-4ff2-b845-038e8b95ad96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882667691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.3882667691
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.938838235
Short name T326
Test name
Test status
Simulation time 468637653 ps
CPU time 0.78 seconds
Started Jul 29 07:09:53 PM PDT 24
Finished Jul 29 07:09:54 PM PDT 24
Peak memory 196916 kb
Host smart-f40a7955-5144-48c8-bca8-52694f9138e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938838235 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.938838235
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1577452029
Short name T310
Test name
Test status
Simulation time 536266789 ps
CPU time 0.97 seconds
Started Jul 29 07:09:53 PM PDT 24
Finished Jul 29 07:09:54 PM PDT 24
Peak memory 193004 kb
Host smart-f8b319dd-c46b-44ca-a49c-a673c09910dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577452029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1577452029
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.807629023
Short name T296
Test name
Test status
Simulation time 437845940 ps
CPU time 1.23 seconds
Started Jul 29 07:09:54 PM PDT 24
Finished Jul 29 07:09:56 PM PDT 24
Peak memory 192956 kb
Host smart-1f27304a-c1bd-40c8-8535-7bf1021f38b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807629023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.807629023
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2810432032
Short name T392
Test name
Test status
Simulation time 1183660188 ps
CPU time 2.33 seconds
Started Jul 29 07:09:53 PM PDT 24
Finished Jul 29 07:09:56 PM PDT 24
Peak memory 191956 kb
Host smart-262516f6-74ec-4280-bb79-3f87386d1741
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810432032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.2810432032
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2737151595
Short name T394
Test name
Test status
Simulation time 500530077 ps
CPU time 2.69 seconds
Started Jul 29 07:09:50 PM PDT 24
Finished Jul 29 07:09:53 PM PDT 24
Peak memory 198676 kb
Host smart-e86c57fd-eb83-468c-9bec-87d0847cebd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737151595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2737151595
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.775086262
Short name T197
Test name
Test status
Simulation time 4532263838 ps
CPU time 2.51 seconds
Started Jul 29 07:09:54 PM PDT 24
Finished Jul 29 07:09:56 PM PDT 24
Peak memory 196852 kb
Host smart-bd90c003-5588-4974-8749-b42a0e06311b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775086262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_
intg_err.775086262
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2541006230
Short name T293
Test name
Test status
Simulation time 476617323 ps
CPU time 0.79 seconds
Started Jul 29 07:09:55 PM PDT 24
Finished Jul 29 07:09:56 PM PDT 24
Peak memory 195724 kb
Host smart-3d406a7e-71e6-44b4-bd02-1c87e2589d85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541006230 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.2541006230
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.198129064
Short name T59
Test name
Test status
Simulation time 445834596 ps
CPU time 0.67 seconds
Started Jul 29 07:09:54 PM PDT 24
Finished Jul 29 07:09:55 PM PDT 24
Peak memory 193332 kb
Host smart-ba60b7a4-2963-4d19-b1e6-bcd0e2041b91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198129064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.198129064
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3320190320
Short name T359
Test name
Test status
Simulation time 529666387 ps
CPU time 0.61 seconds
Started Jul 29 07:09:56 PM PDT 24
Finished Jul 29 07:09:57 PM PDT 24
Peak memory 183808 kb
Host smart-027c0ca1-5bac-4b90-ab91-2a37d2ef3aa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320190320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3320190320
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1313893462
Short name T410
Test name
Test status
Simulation time 2875443873 ps
CPU time 1.66 seconds
Started Jul 29 07:09:53 PM PDT 24
Finished Jul 29 07:09:55 PM PDT 24
Peak memory 194164 kb
Host smart-2085776a-8328-43e7-8cfd-f8b03031d69e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313893462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.1313893462
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1316833585
Short name T342
Test name
Test status
Simulation time 671712778 ps
CPU time 1.75 seconds
Started Jul 29 07:09:54 PM PDT 24
Finished Jul 29 07:09:56 PM PDT 24
Peak memory 198636 kb
Host smart-21bf962a-6736-443d-ac56-def10a08915c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316833585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1316833585
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2090989989
Short name T401
Test name
Test status
Simulation time 7870227778 ps
CPU time 12.33 seconds
Started Jul 29 07:09:54 PM PDT 24
Finished Jul 29 07:10:07 PM PDT 24
Peak memory 198264 kb
Host smart-0b4b3ed3-5f5b-47de-9f0f-08527f9420d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090989989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2090989989
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.1830691724
Short name T36
Test name
Test status
Simulation time 8865881963 ps
CPU time 4.04 seconds
Started Jul 29 05:37:49 PM PDT 24
Finished Jul 29 05:37:54 PM PDT 24
Peak memory 191760 kb
Host smart-6bcbfd3f-8883-4191-9e9e-fbdc98c4a9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830691724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1830691724
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.124504458
Short name T262
Test name
Test status
Simulation time 376791964 ps
CPU time 1.1 seconds
Started Jul 29 05:37:50 PM PDT 24
Finished Jul 29 05:37:52 PM PDT 24
Peak memory 191788 kb
Host smart-1be89ca4-e68b-4366-854c-781db4170935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124504458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.124504458
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.4144247141
Short name T242
Test name
Test status
Simulation time 40647661311 ps
CPU time 23.63 seconds
Started Jul 29 05:37:50 PM PDT 24
Finished Jul 29 05:38:14 PM PDT 24
Peak memory 191840 kb
Host smart-69f728d0-4d67-4cf9-b837-57a965b7298e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144247141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.4144247141
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3056770345
Short name T15
Test name
Test status
Simulation time 8125514451 ps
CPU time 13.24 seconds
Started Jul 29 05:37:55 PM PDT 24
Finished Jul 29 05:38:08 PM PDT 24
Peak memory 215608 kb
Host smart-565d64b9-f47f-499b-b95c-9e4351926594
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056770345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3056770345
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.3367147782
Short name T241
Test name
Test status
Simulation time 602486398 ps
CPU time 1.11 seconds
Started Jul 29 05:37:52 PM PDT 24
Finished Jul 29 05:37:53 PM PDT 24
Peak memory 191612 kb
Host smart-c7236383-0e92-44fa-a34e-ec78175bed82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367147782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.3367147782
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.4087687561
Short name T247
Test name
Test status
Simulation time 35782834052 ps
CPU time 55.22 seconds
Started Jul 29 05:38:00 PM PDT 24
Finished Jul 29 05:38:56 PM PDT 24
Peak memory 192036 kb
Host smart-306b6ae8-eb46-4bb0-87bc-63aa6cd9d19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087687561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.4087687561
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.302586256
Short name T230
Test name
Test status
Simulation time 405024642 ps
CPU time 0.69 seconds
Started Jul 29 05:37:58 PM PDT 24
Finished Jul 29 05:37:59 PM PDT 24
Peak memory 196512 kb
Host smart-af394bb8-753a-47b0-9e51-cfdbace21435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302586256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.302586256
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.152677292
Short name T282
Test name
Test status
Simulation time 48941894465 ps
CPU time 17.57 seconds
Started Jul 29 05:38:01 PM PDT 24
Finished Jul 29 05:38:19 PM PDT 24
Peak memory 191756 kb
Host smart-52c0eb01-1714-4c6f-bfd5-26130a1ed745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152677292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.152677292
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.912660647
Short name T281
Test name
Test status
Simulation time 482584283 ps
CPU time 0.93 seconds
Started Jul 29 05:38:01 PM PDT 24
Finished Jul 29 05:38:02 PM PDT 24
Peak memory 191772 kb
Host smart-6eb942e5-2452-4582-961b-f99ebf822365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912660647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.912660647
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_jump.3862592840
Short name T152
Test name
Test status
Simulation time 411031359 ps
CPU time 1.14 seconds
Started Jul 29 05:38:03 PM PDT 24
Finished Jul 29 05:38:05 PM PDT 24
Peak memory 196808 kb
Host smart-878ce16b-d429-4749-abf0-fa5f45088c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862592840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3862592840
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.3302505486
Short name T80
Test name
Test status
Simulation time 10778504195 ps
CPU time 8.87 seconds
Started Jul 29 05:38:09 PM PDT 24
Finished Jul 29 05:38:17 PM PDT 24
Peak memory 191820 kb
Host smart-85d4ef51-9c41-4b21-9f9f-63ebc6ece172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302505486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.3302505486
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.8831454
Short name T272
Test name
Test status
Simulation time 542306768 ps
CPU time 1.44 seconds
Started Jul 29 05:38:03 PM PDT 24
Finished Jul 29 05:38:05 PM PDT 24
Peak memory 191700 kb
Host smart-9ce42860-3d28-48d3-ab61-09ad4e33bbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8831454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.8831454
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.4157740561
Short name T253
Test name
Test status
Simulation time 18615909845 ps
CPU time 6.76 seconds
Started Jul 29 05:38:05 PM PDT 24
Finished Jul 29 05:38:12 PM PDT 24
Peak memory 191800 kb
Host smart-629c17fb-bc64-4b90-bf94-182edab25d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157740561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.4157740561
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.3905712842
Short name T222
Test name
Test status
Simulation time 511710164 ps
CPU time 0.76 seconds
Started Jul 29 05:38:05 PM PDT 24
Finished Jul 29 05:38:06 PM PDT 24
Peak memory 191756 kb
Host smart-73df965b-aa65-478d-9e79-f99872e7cee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905712842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3905712842
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3456683690
Short name T86
Test name
Test status
Simulation time 32562243406 ps
CPU time 47.54 seconds
Started Jul 29 05:38:04 PM PDT 24
Finished Jul 29 05:38:51 PM PDT 24
Peak memory 191728 kb
Host smart-f2b2a140-ac33-415f-953f-ba02368dff93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456683690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3456683690
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3627065971
Short name T258
Test name
Test status
Simulation time 489433687 ps
CPU time 0.79 seconds
Started Jul 29 05:38:04 PM PDT 24
Finished Jul 29 05:38:05 PM PDT 24
Peak memory 196592 kb
Host smart-e60e1fa9-2660-4ac5-b285-9abdc8ed7ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627065971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3627065971
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1758022431
Short name T249
Test name
Test status
Simulation time 34446204602 ps
CPU time 27.17 seconds
Started Jul 29 05:38:05 PM PDT 24
Finished Jul 29 05:38:32 PM PDT 24
Peak memory 196724 kb
Host smart-54a4b16b-6140-4f85-8e2a-672fabf73c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758022431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1758022431
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2974575194
Short name T235
Test name
Test status
Simulation time 578511479 ps
CPU time 0.74 seconds
Started Jul 29 05:38:06 PM PDT 24
Finished Jul 29 05:38:07 PM PDT 24
Peak memory 191788 kb
Host smart-6029460c-a4bf-4317-a9cd-372d43476e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974575194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2974575194
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.335297473
Short name T248
Test name
Test status
Simulation time 25351452841 ps
CPU time 27.36 seconds
Started Jul 29 05:38:05 PM PDT 24
Finished Jul 29 05:38:33 PM PDT 24
Peak memory 196816 kb
Host smart-b81b3844-1015-42af-bb39-0bd56acbb3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335297473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.335297473
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3135161761
Short name T271
Test name
Test status
Simulation time 563862085 ps
CPU time 0.96 seconds
Started Jul 29 05:38:04 PM PDT 24
Finished Jul 29 05:38:05 PM PDT 24
Peak memory 196648 kb
Host smart-327b4e96-f8d4-4338-944a-54209d3a8494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135161761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3135161761
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.4159746605
Short name T273
Test name
Test status
Simulation time 20909835955 ps
CPU time 10.72 seconds
Started Jul 29 05:38:12 PM PDT 24
Finished Jul 29 05:38:23 PM PDT 24
Peak memory 196856 kb
Host smart-97cc1636-37a6-4aed-be49-81ec74c33173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159746605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.4159746605
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.260088547
Short name T94
Test name
Test status
Simulation time 385941368 ps
CPU time 0.69 seconds
Started Jul 29 05:38:12 PM PDT 24
Finished Jul 29 05:38:13 PM PDT 24
Peak memory 196612 kb
Host smart-41976c03-a2b3-4e48-b479-018dc9fd6fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260088547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.260088547
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.389976783
Short name T277
Test name
Test status
Simulation time 36450428007 ps
CPU time 54.79 seconds
Started Jul 29 05:38:09 PM PDT 24
Finished Jul 29 05:39:04 PM PDT 24
Peak memory 196788 kb
Host smart-e2996a50-fd68-4648-99b1-8b9306870400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389976783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.389976783
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.1446333077
Short name T260
Test name
Test status
Simulation time 360105402 ps
CPU time 0.86 seconds
Started Jul 29 05:38:09 PM PDT 24
Finished Jul 29 05:38:10 PM PDT 24
Peak memory 196608 kb
Host smart-bb425340-24a6-47d2-853a-e3170c51b402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446333077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1446333077
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1838204846
Short name T41
Test name
Test status
Simulation time 35560651679 ps
CPU time 45.64 seconds
Started Jul 29 05:38:10 PM PDT 24
Finished Jul 29 05:38:55 PM PDT 24
Peak memory 196844 kb
Host smart-12f852a3-8df1-468b-8e80-0607f7e88f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838204846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1838204846
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.2383538657
Short name T229
Test name
Test status
Simulation time 469694557 ps
CPU time 1.25 seconds
Started Jul 29 05:38:10 PM PDT 24
Finished Jul 29 05:38:12 PM PDT 24
Peak memory 196620 kb
Host smart-8aa5416a-f36d-4d1b-94e3-436243b34e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383538657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2383538657
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.648753029
Short name T256
Test name
Test status
Simulation time 34604662780 ps
CPU time 50.51 seconds
Started Jul 29 05:37:55 PM PDT 24
Finished Jul 29 05:38:45 PM PDT 24
Peak memory 191824 kb
Host smart-fc79370d-a4f4-46ca-ace6-e802ebd1ce30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648753029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.648753029
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.2191470903
Short name T16
Test name
Test status
Simulation time 4046938985 ps
CPU time 6.93 seconds
Started Jul 29 05:37:56 PM PDT 24
Finished Jul 29 05:38:03 PM PDT 24
Peak memory 215324 kb
Host smart-525dac47-9bf0-4a50-9017-486e055b9a5a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191470903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.2191470903
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1483691547
Short name T255
Test name
Test status
Simulation time 522528793 ps
CPU time 0.77 seconds
Started Jul 29 05:37:55 PM PDT 24
Finished Jul 29 05:37:56 PM PDT 24
Peak memory 191776 kb
Host smart-63c41f46-4a30-4a9a-9ae7-46d684849837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483691547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1483691547
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1364395299
Short name T274
Test name
Test status
Simulation time 33827409423 ps
CPU time 7.36 seconds
Started Jul 29 05:38:08 PM PDT 24
Finished Jul 29 05:38:15 PM PDT 24
Peak memory 196844 kb
Host smart-b7472506-2673-43c0-b7de-47b06c58525c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364395299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1364395299
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2008543152
Short name T236
Test name
Test status
Simulation time 557458496 ps
CPU time 0.78 seconds
Started Jul 29 05:38:11 PM PDT 24
Finished Jul 29 05:38:12 PM PDT 24
Peak memory 191772 kb
Host smart-c6db77a7-43fe-4956-a45a-e21a63c6e7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008543152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2008543152
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.2005065665
Short name T205
Test name
Test status
Simulation time 11888808485 ps
CPU time 3.89 seconds
Started Jul 29 05:38:08 PM PDT 24
Finished Jul 29 05:38:12 PM PDT 24
Peak memory 191840 kb
Host smart-b0f63535-54f9-4444-bab6-6e75d929e8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005065665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.2005065665
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.2725755365
Short name T238
Test name
Test status
Simulation time 529640184 ps
CPU time 0.78 seconds
Started Jul 29 05:38:12 PM PDT 24
Finished Jul 29 05:38:13 PM PDT 24
Peak memory 191788 kb
Host smart-f55c7947-3e52-4106-baee-b1ed31bf5173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725755365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.2725755365
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.1249489018
Short name T37
Test name
Test status
Simulation time 51522568826 ps
CPU time 16.64 seconds
Started Jul 29 05:38:22 PM PDT 24
Finished Jul 29 05:38:39 PM PDT 24
Peak memory 191824 kb
Host smart-5c86daa1-4afe-44a7-addc-bfd807d0b226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249489018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1249489018
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.854931136
Short name T223
Test name
Test status
Simulation time 563458311 ps
CPU time 0.77 seconds
Started Jul 29 05:38:16 PM PDT 24
Finished Jul 29 05:38:17 PM PDT 24
Peak memory 196596 kb
Host smart-1c7f5e7a-199c-411f-b085-f88dad85b28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854931136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.854931136
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.1743352070
Short name T74
Test name
Test status
Simulation time 61502551841 ps
CPU time 87.54 seconds
Started Jul 29 05:38:22 PM PDT 24
Finished Jul 29 05:39:50 PM PDT 24
Peak memory 196848 kb
Host smart-07423e36-168a-4a58-b099-a556b857b193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743352070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1743352070
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.1614052969
Short name T9
Test name
Test status
Simulation time 609344409 ps
CPU time 0.8 seconds
Started Jul 29 05:38:14 PM PDT 24
Finished Jul 29 05:38:15 PM PDT 24
Peak memory 191768 kb
Host smart-5f3f604a-d0e3-44b0-8365-550b8158cad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614052969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1614052969
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.3016719633
Short name T252
Test name
Test status
Simulation time 31329720759 ps
CPU time 31.75 seconds
Started Jul 29 05:38:23 PM PDT 24
Finished Jul 29 05:38:55 PM PDT 24
Peak memory 191796 kb
Host smart-78468a65-b624-4725-b411-521304ea3ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016719633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3016719633
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.3448983733
Short name T76
Test name
Test status
Simulation time 598422994 ps
CPU time 0.76 seconds
Started Jul 29 05:38:24 PM PDT 24
Finished Jul 29 05:38:25 PM PDT 24
Peak memory 191780 kb
Host smart-6cac29a1-267d-4370-8f07-351231e3d81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448983733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.3448983733
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.4147165191
Short name T244
Test name
Test status
Simulation time 2042861038 ps
CPU time 2.23 seconds
Started Jul 29 05:38:21 PM PDT 24
Finished Jul 29 05:38:24 PM PDT 24
Peak memory 191764 kb
Host smart-7827c1c1-c853-4200-be4d-d680c4d760f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147165191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.4147165191
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.1618122114
Short name T212
Test name
Test status
Simulation time 375649520 ps
CPU time 1.12 seconds
Started Jul 29 05:38:13 PM PDT 24
Finished Jul 29 05:38:14 PM PDT 24
Peak memory 191720 kb
Host smart-02090706-d3d2-48e5-ba85-53e3760d143d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618122114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.1618122114
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.906717072
Short name T234
Test name
Test status
Simulation time 25380888727 ps
CPU time 4.04 seconds
Started Jul 29 05:38:15 PM PDT 24
Finished Jul 29 05:38:19 PM PDT 24
Peak memory 192028 kb
Host smart-d10d171b-ef9e-4c3e-8061-9d5023eedac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906717072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.906717072
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.1826214692
Short name T78
Test name
Test status
Simulation time 371934836 ps
CPU time 1.12 seconds
Started Jul 29 05:38:15 PM PDT 24
Finished Jul 29 05:38:16 PM PDT 24
Peak memory 196656 kb
Host smart-c99848f0-0929-4dce-920e-8a38d055351d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826214692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1826214692
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3962400639
Short name T266
Test name
Test status
Simulation time 34423163708 ps
CPU time 55.77 seconds
Started Jul 29 05:38:24 PM PDT 24
Finished Jul 29 05:39:19 PM PDT 24
Peak memory 191824 kb
Host smart-7b16b316-685f-454e-9e75-486fe87a8929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962400639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3962400639
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.2728092884
Short name T206
Test name
Test status
Simulation time 459505159 ps
CPU time 0.87 seconds
Started Jul 29 05:38:24 PM PDT 24
Finished Jul 29 05:38:25 PM PDT 24
Peak memory 191720 kb
Host smart-0e2c774b-45c7-424e-95d8-2c91121587df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728092884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2728092884
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_jump.1060046442
Short name T154
Test name
Test status
Simulation time 480994477 ps
CPU time 0.74 seconds
Started Jul 29 05:38:24 PM PDT 24
Finished Jul 29 05:38:24 PM PDT 24
Peak memory 196596 kb
Host smart-585d23c6-a8c6-4017-b84e-8f0d50487dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060046442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.1060046442
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.3515101267
Short name T279
Test name
Test status
Simulation time 31722151555 ps
CPU time 22.33 seconds
Started Jul 29 05:38:24 PM PDT 24
Finished Jul 29 05:38:47 PM PDT 24
Peak memory 191840 kb
Host smart-b7e53259-8577-4d91-b5b8-28dce68ac9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515101267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.3515101267
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.2331839901
Short name T254
Test name
Test status
Simulation time 595493919 ps
CPU time 0.98 seconds
Started Jul 29 05:38:28 PM PDT 24
Finished Jul 29 05:38:29 PM PDT 24
Peak memory 191732 kb
Host smart-f7d20c64-4bf9-40c5-8e25-3cead48f5c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331839901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2331839901
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.3044708356
Short name T280
Test name
Test status
Simulation time 14809997657 ps
CPU time 6.33 seconds
Started Jul 29 05:38:26 PM PDT 24
Finished Jul 29 05:38:32 PM PDT 24
Peak memory 191840 kb
Host smart-3d61bc55-d615-4f16-959b-f88ea2559a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044708356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3044708356
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.1345516749
Short name T204
Test name
Test status
Simulation time 478336547 ps
CPU time 0.74 seconds
Started Jul 29 05:38:19 PM PDT 24
Finished Jul 29 05:38:20 PM PDT 24
Peak memory 191808 kb
Host smart-2d6a6112-87dc-4834-a7ec-124ca9322890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345516749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1345516749
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.110187525
Short name T264
Test name
Test status
Simulation time 7697704689 ps
CPU time 5.69 seconds
Started Jul 29 05:37:54 PM PDT 24
Finished Jul 29 05:38:00 PM PDT 24
Peak memory 196868 kb
Host smart-19619cee-b17a-4f59-b3c3-50e96f617634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110187525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.110187525
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2054461888
Short name T13
Test name
Test status
Simulation time 3852616489 ps
CPU time 5.31 seconds
Started Jul 29 05:37:57 PM PDT 24
Finished Jul 29 05:38:02 PM PDT 24
Peak memory 215380 kb
Host smart-029a2863-e40e-43e2-8598-76a8ada80251
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054461888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2054461888
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.3759647360
Short name T208
Test name
Test status
Simulation time 389515488 ps
CPU time 0.79 seconds
Started Jul 29 05:38:00 PM PDT 24
Finished Jul 29 05:38:01 PM PDT 24
Peak memory 191780 kb
Host smart-03985846-05ca-49e3-b168-dc8b9fcc192d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759647360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.3759647360
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1757140412
Short name T218
Test name
Test status
Simulation time 57536265116 ps
CPU time 15.65 seconds
Started Jul 29 05:38:21 PM PDT 24
Finished Jul 29 05:38:37 PM PDT 24
Peak memory 191848 kb
Host smart-e17f36e5-9a6e-4555-8a25-b02016efc007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757140412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1757140412
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.124395761
Short name T216
Test name
Test status
Simulation time 441625764 ps
CPU time 0.92 seconds
Started Jul 29 05:38:17 PM PDT 24
Finished Jul 29 05:38:18 PM PDT 24
Peak memory 191760 kb
Host smart-2aa4e54b-120e-4090-b611-52745cd3e9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124395761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.124395761
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_jump.2869030372
Short name T157
Test name
Test status
Simulation time 449249058 ps
CPU time 0.94 seconds
Started Jul 29 05:38:25 PM PDT 24
Finished Jul 29 05:38:26 PM PDT 24
Peak memory 196556 kb
Host smart-e66499a8-1e83-4a96-b559-53c355eba1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869030372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2869030372
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3742103152
Short name T231
Test name
Test status
Simulation time 26440509005 ps
CPU time 36.72 seconds
Started Jul 29 05:38:25 PM PDT 24
Finished Jul 29 05:39:02 PM PDT 24
Peak memory 191824 kb
Host smart-4f78fd81-bd28-4c36-a601-4f55463237fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742103152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3742103152
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.164948910
Short name T232
Test name
Test status
Simulation time 512978707 ps
CPU time 0.63 seconds
Started Jul 29 05:38:24 PM PDT 24
Finished Jul 29 05:38:25 PM PDT 24
Peak memory 191768 kb
Host smart-3597a095-9b62-4049-83d2-3d7f7c207c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164948910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.164948910
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.89373738
Short name T228
Test name
Test status
Simulation time 36481111831 ps
CPU time 54.24 seconds
Started Jul 29 05:38:25 PM PDT 24
Finished Jul 29 05:39:19 PM PDT 24
Peak memory 191824 kb
Host smart-15d60e09-8859-46ad-8eb6-fddd61ff1017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89373738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.89373738
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.4029916703
Short name T45
Test name
Test status
Simulation time 618311945 ps
CPU time 0.69 seconds
Started Jul 29 05:38:27 PM PDT 24
Finished Jul 29 05:38:28 PM PDT 24
Peak memory 191752 kb
Host smart-0cde6d6a-9f98-4904-bf73-84df6f51e8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029916703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.4029916703
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.729897177
Short name T24
Test name
Test status
Simulation time 20688604380 ps
CPU time 9.53 seconds
Started Jul 29 05:38:23 PM PDT 24
Finished Jul 29 05:38:32 PM PDT 24
Peak memory 196872 kb
Host smart-72d5f05a-5933-4cad-acbf-b5143ce819c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729897177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.729897177
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.689547690
Short name T227
Test name
Test status
Simulation time 553655042 ps
CPU time 0.91 seconds
Started Jul 29 05:38:27 PM PDT 24
Finished Jul 29 05:38:29 PM PDT 24
Peak memory 196588 kb
Host smart-5d9eb00f-2144-4b51-bea3-b644e75aa23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689547690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.689547690
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.119163761
Short name T278
Test name
Test status
Simulation time 27698774244 ps
CPU time 9.99 seconds
Started Jul 29 05:38:25 PM PDT 24
Finished Jul 29 05:38:35 PM PDT 24
Peak memory 191860 kb
Host smart-fe81590b-c27e-4afd-8cd3-27c6269185ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119163761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.119163761
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.2389929143
Short name T210
Test name
Test status
Simulation time 458789692 ps
CPU time 0.87 seconds
Started Jul 29 05:38:28 PM PDT 24
Finished Jul 29 05:38:29 PM PDT 24
Peak memory 196572 kb
Host smart-75598533-3082-46f3-a88a-f79b8692f60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389929143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.2389929143
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1258943307
Short name T187
Test name
Test status
Simulation time 398947040 ps
CPU time 1.15 seconds
Started Jul 29 05:38:27 PM PDT 24
Finished Jul 29 05:38:29 PM PDT 24
Peak memory 196496 kb
Host smart-5e997ce8-033c-4813-adca-99cdb6d382df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258943307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1258943307
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.2311904253
Short name T219
Test name
Test status
Simulation time 9782495101 ps
CPU time 8.03 seconds
Started Jul 29 05:38:23 PM PDT 24
Finished Jul 29 05:38:32 PM PDT 24
Peak memory 191824 kb
Host smart-31fd0e86-bc43-4a26-8c49-212ea631272a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311904253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.2311904253
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.222719212
Short name T18
Test name
Test status
Simulation time 431169182 ps
CPU time 1.13 seconds
Started Jul 29 05:38:23 PM PDT 24
Finished Jul 29 05:38:24 PM PDT 24
Peak memory 196620 kb
Host smart-ecc1f5e5-057f-4869-a629-a03d825de222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222719212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.222719212
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.3264778012
Short name T243
Test name
Test status
Simulation time 29483464664 ps
CPU time 40.46 seconds
Started Jul 29 05:38:27 PM PDT 24
Finished Jul 29 05:39:08 PM PDT 24
Peak memory 191800 kb
Host smart-ee93068c-7841-4d83-8504-a1638453f103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264778012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.3264778012
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.2620746793
Short name T8
Test name
Test status
Simulation time 596277086 ps
CPU time 0.71 seconds
Started Jul 29 05:38:37 PM PDT 24
Finished Jul 29 05:38:37 PM PDT 24
Peak memory 191776 kb
Host smart-a144ec0f-76db-4b3a-9138-25220e74d97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620746793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.2620746793
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.972367949
Short name T259
Test name
Test status
Simulation time 2182726369 ps
CPU time 3.84 seconds
Started Jul 29 05:38:35 PM PDT 24
Finished Jul 29 05:38:39 PM PDT 24
Peak memory 191780 kb
Host smart-4f3160fd-5e68-499c-b818-fbc0c88c8a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972367949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.972367949
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.1869949980
Short name T201
Test name
Test status
Simulation time 412314249 ps
CPU time 0.68 seconds
Started Jul 29 05:38:31 PM PDT 24
Finished Jul 29 05:38:32 PM PDT 24
Peak memory 191772 kb
Host smart-8d7a4176-947d-4e74-b1d7-2cac9eba8691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869949980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1869949980
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.3395379725
Short name T202
Test name
Test status
Simulation time 10490176381 ps
CPU time 4.93 seconds
Started Jul 29 05:38:29 PM PDT 24
Finished Jul 29 05:38:34 PM PDT 24
Peak memory 196840 kb
Host smart-4d54972b-2999-4ff5-b8f6-f9fb8ba14943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395379725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3395379725
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.1067924333
Short name T211
Test name
Test status
Simulation time 429935554 ps
CPU time 1.24 seconds
Started Jul 29 05:38:29 PM PDT 24
Finished Jul 29 05:38:30 PM PDT 24
Peak memory 191736 kb
Host smart-f2ec7b27-367f-4b4d-948e-eab96802166a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067924333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1067924333
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.1356685627
Short name T35
Test name
Test status
Simulation time 11301224038 ps
CPU time 17.03 seconds
Started Jul 29 05:38:28 PM PDT 24
Finished Jul 29 05:38:45 PM PDT 24
Peak memory 191836 kb
Host smart-6850cd7c-49be-45d5-bc90-fb05c1dbd219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356685627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1356685627
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2624324447
Short name T221
Test name
Test status
Simulation time 410062703 ps
CPU time 0.79 seconds
Started Jul 29 05:38:28 PM PDT 24
Finished Jul 29 05:38:29 PM PDT 24
Peak memory 191780 kb
Host smart-65c467df-2e06-4650-9727-cdba3ea7bab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624324447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2624324447
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3016771949
Short name T246
Test name
Test status
Simulation time 48717756711 ps
CPU time 72.78 seconds
Started Jul 29 05:37:55 PM PDT 24
Finished Jul 29 05:39:08 PM PDT 24
Peak memory 196736 kb
Host smart-fb7daaab-76d3-466f-a416-2d2dad8d9753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016771949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3016771949
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2506050350
Short name T12
Test name
Test status
Simulation time 4155634519 ps
CPU time 3.55 seconds
Started Jul 29 05:37:57 PM PDT 24
Finished Jul 29 05:38:00 PM PDT 24
Peak memory 215384 kb
Host smart-b3d21b7f-f6e5-499c-bb5e-a9d17989bb27
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506050350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2506050350
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2282935451
Short name T257
Test name
Test status
Simulation time 440705197 ps
CPU time 0.71 seconds
Started Jul 29 05:37:54 PM PDT 24
Finished Jul 29 05:37:55 PM PDT 24
Peak memory 191776 kb
Host smart-b29e8ce1-b1f4-4bf1-9ba0-e18558cb43dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282935451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2282935451
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.24745414
Short name T239
Test name
Test status
Simulation time 32865202261 ps
CPU time 9.6 seconds
Started Jul 29 05:38:30 PM PDT 24
Finished Jul 29 05:38:40 PM PDT 24
Peak memory 191816 kb
Host smart-0fdc7276-ba70-4a08-bfa6-f46ba86f7504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24745414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.24745414
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.2148846905
Short name T275
Test name
Test status
Simulation time 368603300 ps
CPU time 0.8 seconds
Started Jul 29 05:38:30 PM PDT 24
Finished Jul 29 05:38:31 PM PDT 24
Peak memory 191808 kb
Host smart-3232c9d0-ef76-4e5d-9f41-2b2bf5e6e980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148846905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2148846905
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2369007109
Short name T263
Test name
Test status
Simulation time 11141248029 ps
CPU time 17.74 seconds
Started Jul 29 05:38:32 PM PDT 24
Finished Jul 29 05:38:50 PM PDT 24
Peak memory 191844 kb
Host smart-cadbd6de-396a-497d-aef9-58295cd1d3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369007109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2369007109
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2292001067
Short name T251
Test name
Test status
Simulation time 467950902 ps
CPU time 0.95 seconds
Started Jul 29 05:38:37 PM PDT 24
Finished Jul 29 05:38:38 PM PDT 24
Peak memory 196592 kb
Host smart-e38ab24e-d8d2-4728-b270-c17d316a8ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292001067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2292001067
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1115120223
Short name T233
Test name
Test status
Simulation time 7833197983 ps
CPU time 12.94 seconds
Started Jul 29 05:38:33 PM PDT 24
Finished Jul 29 05:38:46 PM PDT 24
Peak memory 191768 kb
Host smart-1757658c-a780-4cd7-b551-3bd0be384319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115120223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1115120223
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.1063973438
Short name T207
Test name
Test status
Simulation time 373902580 ps
CPU time 1.07 seconds
Started Jul 29 05:38:36 PM PDT 24
Finished Jul 29 05:38:38 PM PDT 24
Peak memory 196536 kb
Host smart-2908a617-f869-4979-96ed-b1b99d849173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063973438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1063973438
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2330402598
Short name T261
Test name
Test status
Simulation time 19987518351 ps
CPU time 6.05 seconds
Started Jul 29 05:38:33 PM PDT 24
Finished Jul 29 05:38:39 PM PDT 24
Peak memory 196836 kb
Host smart-bf97c470-b768-484d-97ef-448f104682a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330402598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2330402598
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.3648720708
Short name T283
Test name
Test status
Simulation time 380361252 ps
CPU time 0.84 seconds
Started Jul 29 05:38:32 PM PDT 24
Finished Jul 29 05:38:33 PM PDT 24
Peak memory 191780 kb
Host smart-b8478fe8-c221-4a91-97af-e99e7dc583e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648720708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3648720708
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_jump.3728039644
Short name T192
Test name
Test status
Simulation time 481041965 ps
CPU time 0.79 seconds
Started Jul 29 05:38:32 PM PDT 24
Finished Jul 29 05:38:33 PM PDT 24
Peak memory 196704 kb
Host smart-56b04106-f4e3-4ff8-8656-c58a67528ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728039644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3728039644
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3112851284
Short name T226
Test name
Test status
Simulation time 5823860801 ps
CPU time 8.36 seconds
Started Jul 29 05:38:32 PM PDT 24
Finished Jul 29 05:38:41 PM PDT 24
Peak memory 196856 kb
Host smart-808de332-5753-4776-8d0d-a70594d1f00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112851284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3112851284
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2039460213
Short name T268
Test name
Test status
Simulation time 519554430 ps
CPU time 1.37 seconds
Started Jul 29 05:38:37 PM PDT 24
Finished Jul 29 05:38:39 PM PDT 24
Peak memory 191560 kb
Host smart-49ec8318-2cb6-430b-ae76-42e8bfe64e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039460213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2039460213
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.1764234161
Short name T240
Test name
Test status
Simulation time 59427507120 ps
CPU time 39.62 seconds
Started Jul 29 05:38:33 PM PDT 24
Finished Jul 29 05:39:13 PM PDT 24
Peak memory 191844 kb
Host smart-3c4fe20d-1aaf-4ecc-99ee-a9b23e81c9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764234161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.1764234161
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.3697977302
Short name T276
Test name
Test status
Simulation time 438740459 ps
CPU time 1.16 seconds
Started Jul 29 05:38:37 PM PDT 24
Finished Jul 29 05:38:38 PM PDT 24
Peak memory 191776 kb
Host smart-36325463-4b9c-434e-bca0-0c4621ea0e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697977302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3697977302
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_jump.1918926895
Short name T188
Test name
Test status
Simulation time 405792393 ps
CPU time 0.84 seconds
Started Jul 29 05:38:37 PM PDT 24
Finished Jul 29 05:38:38 PM PDT 24
Peak memory 196600 kb
Host smart-8e6204e6-1d51-4db7-9110-80ed23d1c992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918926895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1918926895
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.150815420
Short name T265
Test name
Test status
Simulation time 25428884990 ps
CPU time 3.07 seconds
Started Jul 29 05:38:31 PM PDT 24
Finished Jul 29 05:38:34 PM PDT 24
Peak memory 191744 kb
Host smart-388ea0ae-ffc9-4559-912f-aaa97e01f252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150815420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.150815420
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.1908337376
Short name T250
Test name
Test status
Simulation time 494438819 ps
CPU time 1.29 seconds
Started Jul 29 05:38:33 PM PDT 24
Finished Jul 29 05:38:34 PM PDT 24
Peak memory 191756 kb
Host smart-5d8c8ee1-c451-4b1d-bc53-4ae90861e928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908337376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1908337376
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.3230397151
Short name T203
Test name
Test status
Simulation time 31037679199 ps
CPU time 41.61 seconds
Started Jul 29 05:38:36 PM PDT 24
Finished Jul 29 05:39:18 PM PDT 24
Peak memory 191848 kb
Host smart-ccc7c55b-cb16-408e-bdbf-0726fa494b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230397151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3230397151
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.4121885246
Short name T245
Test name
Test status
Simulation time 555803284 ps
CPU time 0.75 seconds
Started Jul 29 05:38:37 PM PDT 24
Finished Jul 29 05:38:38 PM PDT 24
Peak memory 191728 kb
Host smart-1e6640fb-a921-4a3a-9203-4a2026923465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121885246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.4121885246
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1415916380
Short name T237
Test name
Test status
Simulation time 16662466379 ps
CPU time 6.1 seconds
Started Jul 29 05:38:37 PM PDT 24
Finished Jul 29 05:38:43 PM PDT 24
Peak memory 191788 kb
Host smart-c4972cd6-f518-455b-b195-1b1f7e571ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415916380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1415916380
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.3843476603
Short name T225
Test name
Test status
Simulation time 442477249 ps
CPU time 1.19 seconds
Started Jul 29 05:38:37 PM PDT 24
Finished Jul 29 05:38:38 PM PDT 24
Peak memory 196588 kb
Host smart-aa57f564-1288-412e-8b05-c7df5b1b31f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843476603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.3843476603
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1522416644
Short name T214
Test name
Test status
Simulation time 44687718819 ps
CPU time 58.33 seconds
Started Jul 29 05:38:38 PM PDT 24
Finished Jul 29 05:39:36 PM PDT 24
Peak memory 196868 kb
Host smart-90ae4560-9d63-4ff6-a1be-93b3c3d2b739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522416644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1522416644
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.550232569
Short name T224
Test name
Test status
Simulation time 439358954 ps
CPU time 1.13 seconds
Started Jul 29 05:38:38 PM PDT 24
Finished Jul 29 05:38:39 PM PDT 24
Peak memory 191812 kb
Host smart-d0176939-123d-4b48-9de9-8bf7fafc69f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550232569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.550232569
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.1385473094
Short name T269
Test name
Test status
Simulation time 12916641992 ps
CPU time 9.43 seconds
Started Jul 29 05:37:56 PM PDT 24
Finished Jul 29 05:38:05 PM PDT 24
Peak memory 191880 kb
Host smart-108d79a5-d752-48fb-b280-5046896e0235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385473094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.1385473094
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.1425642594
Short name T93
Test name
Test status
Simulation time 561296754 ps
CPU time 0.96 seconds
Started Jul 29 05:37:56 PM PDT 24
Finished Jul 29 05:37:57 PM PDT 24
Peak memory 196588 kb
Host smart-f15e8ad7-8f25-491b-8607-d031f1fde68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425642594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.1425642594
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3566215753
Short name T270
Test name
Test status
Simulation time 16364112045 ps
CPU time 21.25 seconds
Started Jul 29 05:37:59 PM PDT 24
Finished Jul 29 05:38:20 PM PDT 24
Peak memory 196748 kb
Host smart-19e40e30-f591-4266-8759-b284001df577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566215753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3566215753
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.4121419380
Short name T213
Test name
Test status
Simulation time 408443073 ps
CPU time 1.23 seconds
Started Jul 29 05:37:56 PM PDT 24
Finished Jul 29 05:37:58 PM PDT 24
Peak memory 191712 kb
Host smart-2efac7b2-d2a3-47b4-8db6-39423bf8fb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121419380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.4121419380
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3158227698
Short name T215
Test name
Test status
Simulation time 23153384337 ps
CPU time 7.81 seconds
Started Jul 29 05:37:55 PM PDT 24
Finished Jul 29 05:38:03 PM PDT 24
Peak memory 191868 kb
Host smart-bd1295cb-c28b-48f3-891a-63f518e57aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158227698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3158227698
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3250927981
Short name T220
Test name
Test status
Simulation time 566046617 ps
CPU time 1 seconds
Started Jul 29 05:37:57 PM PDT 24
Finished Jul 29 05:37:58 PM PDT 24
Peak memory 191776 kb
Host smart-bf784b87-3e19-4bdb-8d14-7968a8979fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250927981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3250927981
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_jump.3138559627
Short name T186
Test name
Test status
Simulation time 462481717 ps
CPU time 0.72 seconds
Started Jul 29 05:37:59 PM PDT 24
Finished Jul 29 05:38:00 PM PDT 24
Peak memory 196564 kb
Host smart-a1d3c58e-6240-4333-9dad-a0c0d2d6df62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138559627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.3138559627
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.398476408
Short name T209
Test name
Test status
Simulation time 40853827786 ps
CPU time 56.21 seconds
Started Jul 29 05:37:59 PM PDT 24
Finished Jul 29 05:38:56 PM PDT 24
Peak memory 191856 kb
Host smart-ae7b4117-342f-49f4-8e72-9aa0fddbd0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398476408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.398476408
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.2741481445
Short name T267
Test name
Test status
Simulation time 435496226 ps
CPU time 1.22 seconds
Started Jul 29 05:38:02 PM PDT 24
Finished Jul 29 05:38:04 PM PDT 24
Peak memory 191776 kb
Host smart-0e10ca32-6395-4682-ab9e-50aada6413cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741481445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.2741481445
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_jump.3763820117
Short name T180
Test name
Test status
Simulation time 364873878 ps
CPU time 0.99 seconds
Started Jul 29 05:38:01 PM PDT 24
Finished Jul 29 05:38:02 PM PDT 24
Peak memory 196592 kb
Host smart-97a60352-ee87-4607-9277-2248c2ffbfa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763820117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3763820117
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.2568260270
Short name T200
Test name
Test status
Simulation time 30913840077 ps
CPU time 25.15 seconds
Started Jul 29 05:38:01 PM PDT 24
Finished Jul 29 05:38:26 PM PDT 24
Peak memory 191800 kb
Host smart-a9bb28a2-bdd9-4dd2-8f32-d2d0b44150a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568260270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2568260270
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2212777086
Short name T217
Test name
Test status
Simulation time 548245052 ps
CPU time 0.67 seconds
Started Jul 29 05:37:58 PM PDT 24
Finished Jul 29 05:37:59 PM PDT 24
Peak memory 196628 kb
Host smart-86f5194c-9165-4983-9dcb-21c49226d9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212777086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2212777086
Directory /workspace/9.aon_timer_smoke/latest
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