Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	26334	1		T1	377		T2	10		T3	12
bark[1]	501	1		T32	21		T56	14		T105	50
bark[2]	389	1		T13	150		T31	104		T26	21
bark[3]	631	1		T6	123		T144	14		T53	14
bark[4]	141	1		T24	14		T102	21		T109	21
bark[5]	593	1		T42	21		T95	14		T107	26
bark[6]	635	1		T5	141		T43	14		T32	21
bark[7]	611	1		T6	14		T41	119		T54	214
bark[8]	896	1		T8	249		T20	21		T86	21
bark[9]	1140	1		T5	5		T44	38		T120	26
bark[10]	596	1		T137	21		T160	21		T107	42
bark[11]	865	1		T31	21		T137	21		T55	14
bark[12]	252	1		T4	21		T51	21		T23	14
bark[13]	1170	1		T1	35		T32	21		T47	51
bark[14]	642	1		T17	21		T41	7		T175	5
bark[15]	93	1		T47	21		T103	14		T106	21
bark[16]	245	1		T115	14		T133	14		T114	47
bark[17]	327	1		T101	198		T113	14		T147	21
bark[18]	1060	1		T1	74		T114	21		T105	209
bark[19]	637	1		T17	21		T31	71		T163	38
bark[20]	626	1		T105	26		T104	35		T107	21
bark[21]	812	1		T31	21		T101	30		T106	63
bark[22]	962	1		T42	290		T101	21		T146	14
bark[23]	543	1		T8	7		T11	21		T17	21
bark[24]	496	1		T13	31		T44	97		T163	42
bark[25]	313	1		T30	14		T17	21		T31	21
bark[26]	483	1		T5	40		T17	26		T54	128
bark[27]	327	1		T178	14		T48	30		T22	14
bark[28]	1070	1		T8	7		T41	222		T51	283
bark[29]	476	1		T104	21		T145	14		T86	277
bark[30]	320	1		T8	21		T96	14		T152	21
bark[31]	665	1		T31	21		T40	47		T51	243
bark_0	4645	1		T1	69		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	26179	1		T1	373		T2	9		T3	11
bite[1]	1340	1		T17	21		T101	21		T54	213
bite[2]	1006	1		T44	97		T40	46		T41	46
bite[3]	372	1		T17	21		T31	103		T105	50
bite[4]	377	1		T41	6		T80	108		T102	21
bite[5]	502	1		T20	81		T80	26		T86	13
bite[6]	414	1		T13	149		T17	26		T115	13
bite[7]	353	1		T1	35		T47	166		T133	13
bite[8]	1148	1		T4	21		T5	40		T8	248
bite[9]	854	1		T41	221		T101	268		T103	42
bite[10]	576	1		T6	122		T44	21		T95	13
bite[11]	1021	1		T17	21		T41	118		T42	310
bite[12]	488	1		T17	21		T107	21		T125	13
bite[13]	249	1		T6	13		T8	13		T105	21
bite[14]	234	1		T51	21		T114	21		T105	26
bite[15]	179	1		T31	21		T48	21		T21	46
bite[16]	322	1		T11	42		T48	30		T98	13
bite[17]	667	1		T31	21		T178	13		T137	21
bite[18]	291	1		T104	34		T107	26		T26	21
bite[19]	933	1		T8	21		T144	13		T43	13
bite[20]	290	1		T32	21		T31	21		T146	13
bite[21]	703	1		T26	21		T138	30		T118	40
bite[22]	1065	1		T31	70		T120	26		T101	21
bite[23]	444	1		T13	31		T45	13		T101	30
bite[24]	840	1		T1	73		T30	13		T32	21
bite[25]	472	1		T42	21		T51	242		T152	21
bite[26]	511	1		T8	6		T51	21		T175	69
bite[27]	607	1		T5	4		T31	108		T163	38
bite[28]	585	1		T32	21		T101	164		T107	21
bite[29]	468	1		T137	47		T160	21		T23	13
bite[30]	495	1		T101	197		T104	30		T121	42
bite[31]	346	1		T8	6		T31	21		T80	102
bite_0	5165	1		T1	74		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	40993	1		T1	555		T2	17		T3	19
auto[1]	8503	1		T11	20		T29	7		T13	197

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	1408	1		T13	85		T44	35		T31	147
prescale[1]	669	1		T1	19		T31	18		T120	9
prescale[2]	907	1		T32	9		T101	136		T48	19
prescale[3]	947	1		T4	19		T5	2		T8	56
prescale[4]	1050	1		T4	61		T5	2		T44	19
prescale[5]	777	1		T1	36		T6	2		T8	74
prescale[6]	891	1		T4	28		T11	41		T44	19
prescale[7]	789	1		T1	2		T11	19		T32	41
prescale[8]	761	1		T31	19		T40	40		T42	43
prescale[9]	567	1		T32	40		T31	2		T42	4
prescale[10]	603	1		T4	19		T39	9		T42	19
prescale[11]	1137	1		T1	142		T137	19		T47	35
prescale[12]	557	1		T1	28		T5	133		T8	26
prescale[13]	688	1		T13	2		T44	23		T41	21
prescale[14]	721	1		T1	19		T5	2		T31	37
prescale[15]	1217	1		T4	112		T5	19		T8	116
prescale[16]	642	1		T1	2		T4	9		T8	2
prescale[17]	735	1		T8	19		T31	2		T40	4
prescale[18]	1098	1		T31	19		T101	74		T48	209
prescale[19]	562	1		T5	24		T6	23		T8	42
prescale[20]	445	1		T13	2		T38	9		T42	11
prescale[21]	939	1		T8	4		T42	19		T101	57
prescale[22]	537	1		T3	9		T32	74		T51	19
prescale[23]	709	1		T4	23		T44	19		T40	2
prescale[24]	837	1		T1	50		T5	19		T8	64
prescale[25]	789	1		T8	19		T120	40		T101	90
prescale[26]	788	1		T44	19		T137	9		T47	40
prescale[27]	683	1		T32	50		T41	19		T92	9
prescale[28]	442	1		T42	21		T48	23		T51	61
prescale[29]	799	1		T4	53		T5	4		T193	9
prescale[30]	631	1		T8	66		T101	30		T105	9
prescale[31]	885	1		T1	32		T17	32		T31	2
prescale_0	24286	1		T1	225		T2	17		T3	10

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	37002	1		T1	372		T2	17		T3	19
auto[1]	12494	1		T1	183		T4	40		T5	149

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	49496	1		T1	555		T2	17		T3	19

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	28286	1		T1	357		T2	12		T3	14
wkup[1]	139	1		T41	21		T48	30		T136	15
wkup[2]	330	1		T31	21		T48	21		T80	21
wkup[3]	278	1		T8	21		T31	21		T105	21
wkup[4]	329	1		T175	21		T164	21		T80	47
wkup[5]	209	1		T13	31		T42	8		T47	21
wkup[6]	433	1		T1	26		T31	21		T101	72
wkup[7]	279	1		T44	21		T31	21		T101	72
wkup[8]	292	1		T44	21		T31	21		T51	21
wkup[9]	361	1		T4	21		T6	8		T13	35
wkup[10]	189	1		T31	42		T26	21		T113	21
wkup[11]	280	1		T13	56		T31	21		T42	26
wkup[12]	392	1		T8	29		T17	21		T41	21
wkup[13]	285	1		T5	6		T8	21		T40	21
wkup[14]	141	1		T41	21		T48	21		T175	21
wkup[15]	189	1		T1	21		T31	8		T101	21
wkup[16]	252	1		T5	21		T41	8		T101	26
wkup[17]	322	1		T13	30		T17	21		T47	21
wkup[18]	239	1		T31	15		T80	101		T84	21
wkup[19]	322	1		T4	21		T42	21		T51	47
wkup[20]	258	1		T5	21		T13	15		T101	42
wkup[21]	362	1		T8	21		T13	35		T137	21
wkup[22]	187	1		T101	21		T104	15		T86	15
wkup[23]	210	1		T101	21		T51	21		T20	30
wkup[24]	265	1		T31	21		T42	21		T101	21
wkup[25]	280	1		T51	21		T145	15		T22	15
wkup[26]	323	1		T8	20		T11	21		T31	21
wkup[27]	200	1		T4	21		T32	21		T40	21
wkup[28]	248	1		T4	21		T101	21		T21	21
wkup[29]	222	1		T31	31		T21	21		T138	21
wkup[30]	199	1		T144	15		T41	21		T101	21
wkup[31]	447	1		T44	21		T101	53		T51	30
wkup[32]	205	1		T1	35		T101	26		T163	30
wkup[33]	113	1		T41	21		T42	21		T147	26
wkup[34]	168	1		T31	42		T82	21		T147	21
wkup[35]	272	1		T44	21		T45	15		T42	21
wkup[36]	365	1		T32	21		T137	21		T101	47
wkup[37]	237	1		T31	30		T137	26		T101	21
wkup[38]	173	1		T6	21		T54	21		T103	21
wkup[39]	240	1		T6	15		T11	21		T137	21
wkup[40]	214	1		T48	30		T56	15		T80	26
wkup[41]	299	1		T178	15		T115	15		T101	42
wkup[42]	275	1		T101	21		T20	21		T26	21
wkup[43]	305	1		T13	21		T31	39		T40	21
wkup[44]	162	1		T98	15		T82	21		T106	21
wkup[45]	205	1		T8	8		T101	45		T51	21
wkup[46]	478	1		T1	21		T13	21		T17	24
wkup[47]	246	1		T8	21		T51	26		T105	21
wkup[48]	398	1		T17	21		T96	15		T51	21
wkup[49]	355	1		T1	15		T120	21		T101	21
wkup[50]	460	1		T31	21		T101	21		T105	51
wkup[51]	318	1		T13	21		T30	15		T48	21
wkup[52]	364	1		T6	21		T8	15		T48	42
wkup[53]	233	1		T101	21		T105	26		T21	21
wkup[54]	177	1		T42	21		T51	21		T104	21
wkup[55]	367	1		T5	40		T8	21		T120	26
wkup[56]	256	1		T13	21		T101	21		T54	26
wkup[57]	221	1		T1	21		T6	21		T13	26
wkup[58]	347	1		T13	42		T31	44		T41	21
wkup[59]	284	1		T8	21		T101	56		T51	21
wkup[60]	331	1		T43	15		T31	21		T101	42
wkup[61]	236	1		T6	21		T17	21		T101	47
wkup[62]	395	1		T8	21		T13	39		T101	21
wkup[63]	374	1		T4	21		T17	26		T32	21
wkup_0	3675	1		T1	59		T2	5		T3	5