Design Module List
dashboard | hierarchy | modlist | groups | tests | asserts
Total Module Definition Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.94 99.56 95.91 100.00 99.21 100.00


Total modules in report: 36
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
prim_sync_reqack 87.50 100.00 50.00 100.00 100.00
  tlul_rsp_intg_gen 91.67 83.33 100.00
aon_timer 93.33 100.00 66.67 100.00 100.00 100.00
  prim_reg_cdc_arb 98.04 100.00 96.51 95.65 100.00
  prim_reg_cdc 98.33 100.00 93.30 100.00 100.00
tlul_adapter_reg 98.98 100.00 95.92 100.00 100.00
aon_timer_reg_top 99.57 100.00 98.28 100.00 100.00
prim_lc_sync 100.00 100.00 100.00
tlul_data_integ_dec 100.00 100.00
aon_timer_core 100.00 100.00 100.00 100.00
tlul_cmd_intg_chk 100.00 100.00 100.00
prim_alert_sender 100.00 100.00
prim_edge_detector 100.00 100.00 100.00
tlul_assert 100.00 100.00 100.00 100.00
prim_onehot_check 100.00 100.00
  prim_subreg 100.00 100.00 100.00 100.00
aon_timer_csr_assert_fpv 100.00 100.00
prim_secded_inv_39_32_dec 100.00 100.00
prim_generic_buf 100.00 100.00
prim_intr_hw 100.00 100.00 100.00 100.00
prim_pulse_sync 100.00 100.00 100.00 100.00 100.00
  prim_subreg_arb 100.00 100.00 100.00 100.00
prim_subreg_ext 100.00 100.00
prim_secded_inv_39_32_enc 100.00 100.00
tlul_err 100.00 100.00 100.00 100.00 100.00
prim_secded_inv_64_57_enc 100.00 100.00
prim_secded_inv_64_57_dec 100.00 100.00
prim_generic_flop 100.00 100.00 100.00
tlul_data_integ_enc
prim_reg_we_check
prim_buf
prim_generic_flop_2sync
prim_flop
prim_flop_2sync
tb
prim_sec_anchor_buf