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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.17 99.33 93.67 100.00 98.40 99.51 50.10


Total test records in report: 417
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T35 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.96488424 Jul 30 06:22:45 PM PDT 24 Jul 30 06:22:52 PM PDT 24 7792657226 ps
T194 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1476531663 Jul 30 06:22:36 PM PDT 24 Jul 30 06:22:37 PM PDT 24 332045466 ps
T282 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2119631169 Jul 30 06:22:42 PM PDT 24 Jul 30 06:22:44 PM PDT 24 476465487 ps
T283 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2136250292 Jul 30 06:22:57 PM PDT 24 Jul 30 06:22:58 PM PDT 24 322768092 ps
T284 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.919654983 Jul 30 06:23:02 PM PDT 24 Jul 30 06:23:03 PM PDT 24 385439064 ps
T36 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.432885390 Jul 30 06:22:40 PM PDT 24 Jul 30 06:22:42 PM PDT 24 4661831688 ps
T285 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3288670953 Jul 30 06:22:55 PM PDT 24 Jul 30 06:22:56 PM PDT 24 354948999 ps
T286 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1649266985 Jul 30 06:22:56 PM PDT 24 Jul 30 06:22:57 PM PDT 24 347269063 ps
T58 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1086025059 Jul 30 06:22:46 PM PDT 24 Jul 30 06:22:47 PM PDT 24 422085409 ps
T72 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2161740699 Jul 30 06:22:47 PM PDT 24 Jul 30 06:22:49 PM PDT 24 1529050821 ps
T287 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.4145261435 Jul 30 06:22:46 PM PDT 24 Jul 30 06:22:47 PM PDT 24 431083677 ps
T288 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.584736871 Jul 30 06:22:23 PM PDT 24 Jul 30 06:22:33 PM PDT 24 7112654978 ps
T289 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3238139908 Jul 30 06:22:34 PM PDT 24 Jul 30 06:22:35 PM PDT 24 279042407 ps
T73 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1582300415 Jul 30 06:22:34 PM PDT 24 Jul 30 06:22:36 PM PDT 24 1594612952 ps
T290 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2350138473 Jul 30 06:22:53 PM PDT 24 Jul 30 06:22:54 PM PDT 24 394449963 ps
T291 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1847853165 Jul 30 06:22:31 PM PDT 24 Jul 30 06:22:33 PM PDT 24 518493968 ps
T292 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3187396632 Jul 30 06:23:02 PM PDT 24 Jul 30 06:23:03 PM PDT 24 344862491 ps
T293 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3798911175 Jul 30 06:22:56 PM PDT 24 Jul 30 06:22:57 PM PDT 24 515099434 ps
T294 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3794099478 Jul 30 06:22:34 PM PDT 24 Jul 30 06:22:35 PM PDT 24 1615725533 ps
T295 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.49936983 Jul 30 06:22:47 PM PDT 24 Jul 30 06:22:48 PM PDT 24 371929286 ps
T59 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2609428606 Jul 30 06:22:36 PM PDT 24 Jul 30 06:22:37 PM PDT 24 545784878 ps
T196 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2346688784 Jul 30 06:22:36 PM PDT 24 Jul 30 06:22:37 PM PDT 24 333660067 ps
T195 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3530103648 Jul 30 06:22:48 PM PDT 24 Jul 30 06:22:49 PM PDT 24 388373598 ps
T296 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3781169747 Jul 30 06:22:23 PM PDT 24 Jul 30 06:22:24 PM PDT 24 279742714 ps
T37 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3232382506 Jul 30 06:22:35 PM PDT 24 Jul 30 06:22:39 PM PDT 24 8246642499 ps
T297 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2019021482 Jul 30 06:22:25 PM PDT 24 Jul 30 06:22:25 PM PDT 24 465061753 ps
T298 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.26357905 Jul 30 06:22:33 PM PDT 24 Jul 30 06:22:34 PM PDT 24 490133956 ps
T299 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.754264656 Jul 30 06:22:37 PM PDT 24 Jul 30 06:22:38 PM PDT 24 443027837 ps
T300 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.680156594 Jul 30 06:22:46 PM PDT 24 Jul 30 06:22:47 PM PDT 24 437096479 ps
T301 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2724080412 Jul 30 06:22:30 PM PDT 24 Jul 30 06:22:31 PM PDT 24 444756904 ps
T302 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3693763794 Jul 30 06:23:02 PM PDT 24 Jul 30 06:23:03 PM PDT 24 469897892 ps
T60 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1277400857 Jul 30 06:22:31 PM PDT 24 Jul 30 06:22:41 PM PDT 24 7611464366 ps
T303 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2999288789 Jul 30 06:22:32 PM PDT 24 Jul 30 06:22:33 PM PDT 24 352555774 ps
T304 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1769837146 Jul 30 06:22:35 PM PDT 24 Jul 30 06:22:42 PM PDT 24 4244168567 ps
T305 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3789829200 Jul 30 06:23:02 PM PDT 24 Jul 30 06:23:03 PM PDT 24 296474716 ps
T306 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.4294253401 Jul 30 06:22:46 PM PDT 24 Jul 30 06:22:47 PM PDT 24 314904259 ps
T307 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3779142897 Jul 30 06:22:38 PM PDT 24 Jul 30 06:22:39 PM PDT 24 520336348 ps
T308 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3223704781 Jul 30 06:22:31 PM PDT 24 Jul 30 06:22:32 PM PDT 24 362012116 ps
T309 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.430317632 Jul 30 06:23:03 PM PDT 24 Jul 30 06:23:04 PM PDT 24 365952305 ps
T61 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.4151682201 Jul 30 06:22:33 PM PDT 24 Jul 30 06:22:34 PM PDT 24 537133889 ps
T74 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3917368081 Jul 30 06:22:49 PM PDT 24 Jul 30 06:22:53 PM PDT 24 2461902085 ps
T310 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3083026906 Jul 30 06:22:47 PM PDT 24 Jul 30 06:22:48 PM PDT 24 454016457 ps
T311 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1647603983 Jul 30 06:22:43 PM PDT 24 Jul 30 06:22:45 PM PDT 24 584719499 ps
T312 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.54654484 Jul 30 06:22:50 PM PDT 24 Jul 30 06:22:52 PM PDT 24 440556908 ps
T313 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.893050711 Jul 30 06:22:42 PM PDT 24 Jul 30 06:22:43 PM PDT 24 627149156 ps
T190 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1425347916 Jul 30 06:22:41 PM PDT 24 Jul 30 06:22:55 PM PDT 24 8817281934 ps
T314 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.175760869 Jul 30 06:22:33 PM PDT 24 Jul 30 06:22:34 PM PDT 24 768177143 ps
T75 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1651516334 Jul 30 06:22:35 PM PDT 24 Jul 30 06:22:36 PM PDT 24 1179087034 ps
T315 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.426677561 Jul 30 06:22:57 PM PDT 24 Jul 30 06:22:58 PM PDT 24 418864691 ps
T316 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3796418432 Jul 30 06:23:01 PM PDT 24 Jul 30 06:23:02 PM PDT 24 540854302 ps
T68 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3472759300 Jul 30 06:22:50 PM PDT 24 Jul 30 06:22:52 PM PDT 24 475209088 ps
T317 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2766302982 Jul 30 06:22:53 PM PDT 24 Jul 30 06:22:55 PM PDT 24 492342376 ps
T318 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2709727948 Jul 30 06:22:31 PM PDT 24 Jul 30 06:22:33 PM PDT 24 503423057 ps
T319 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2609781717 Jul 30 06:22:53 PM PDT 24 Jul 30 06:22:54 PM PDT 24 380053973 ps
T320 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2322478978 Jul 30 06:23:03 PM PDT 24 Jul 30 06:23:04 PM PDT 24 462257813 ps
T321 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.525040422 Jul 30 06:22:30 PM PDT 24 Jul 30 06:22:31 PM PDT 24 422356116 ps
T62 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3325868198 Jul 30 06:22:35 PM PDT 24 Jul 30 06:22:36 PM PDT 24 595128099 ps
T322 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1946350925 Jul 30 06:22:40 PM PDT 24 Jul 30 06:22:41 PM PDT 24 554906557 ps
T76 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.4096159674 Jul 30 06:22:24 PM PDT 24 Jul 30 06:22:25 PM PDT 24 302280482 ps
T323 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1224245896 Jul 30 06:22:52 PM PDT 24 Jul 30 06:22:54 PM PDT 24 404712578 ps
T324 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.805168225 Jul 30 06:22:49 PM PDT 24 Jul 30 06:22:51 PM PDT 24 4194655681 ps
T77 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1449041431 Jul 30 06:22:37 PM PDT 24 Jul 30 06:22:39 PM PDT 24 1558807877 ps
T325 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2789986983 Jul 30 06:22:45 PM PDT 24 Jul 30 06:22:52 PM PDT 24 4208260971 ps
T326 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1476823765 Jul 30 06:22:38 PM PDT 24 Jul 30 06:22:41 PM PDT 24 4283092116 ps
T327 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1682528871 Jul 30 06:22:28 PM PDT 24 Jul 30 06:22:35 PM PDT 24 8404338064 ps
T328 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.4213129718 Jul 30 06:22:23 PM PDT 24 Jul 30 06:22:25 PM PDT 24 533314754 ps
T329 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1511495302 Jul 30 06:22:57 PM PDT 24 Jul 30 06:22:57 PM PDT 24 363246332 ps
T330 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2145710782 Jul 30 06:22:39 PM PDT 24 Jul 30 06:22:41 PM PDT 24 587508612 ps
T331 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2800672903 Jul 30 06:22:59 PM PDT 24 Jul 30 06:23:00 PM PDT 24 350687052 ps
T332 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.925350801 Jul 30 06:23:01 PM PDT 24 Jul 30 06:23:02 PM PDT 24 279880482 ps
T78 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3677085815 Jul 30 06:22:49 PM PDT 24 Jul 30 06:22:51 PM PDT 24 2313927286 ps
T63 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1584441940 Jul 30 06:22:42 PM PDT 24 Jul 30 06:22:44 PM PDT 24 300929455 ps
T333 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1739488379 Jul 30 06:22:28 PM PDT 24 Jul 30 06:22:28 PM PDT 24 308061520 ps
T334 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.660648510 Jul 30 06:23:07 PM PDT 24 Jul 30 06:23:08 PM PDT 24 377398083 ps
T191 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2201793813 Jul 30 06:22:51 PM PDT 24 Jul 30 06:22:54 PM PDT 24 3911343657 ps
T335 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3164982924 Jul 30 06:22:58 PM PDT 24 Jul 30 06:23:00 PM PDT 24 507026338 ps
T64 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.4165887428 Jul 30 06:22:34 PM PDT 24 Jul 30 06:22:36 PM PDT 24 1132615405 ps
T336 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.264747143 Jul 30 06:22:35 PM PDT 24 Jul 30 06:22:37 PM PDT 24 474321396 ps
T337 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2348911671 Jul 30 06:22:36 PM PDT 24 Jul 30 06:22:38 PM PDT 24 342015449 ps
T338 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.4275040220 Jul 30 06:22:40 PM PDT 24 Jul 30 06:22:41 PM PDT 24 306723295 ps
T339 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1630069799 Jul 30 06:22:45 PM PDT 24 Jul 30 06:22:46 PM PDT 24 487589506 ps
T340 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.784358862 Jul 30 06:22:41 PM PDT 24 Jul 30 06:22:43 PM PDT 24 568462457 ps
T341 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1132862127 Jul 30 06:22:37 PM PDT 24 Jul 30 06:22:39 PM PDT 24 386157283 ps
T65 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2495458232 Jul 30 06:22:46 PM PDT 24 Jul 30 06:22:47 PM PDT 24 371547299 ps
T342 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3494765840 Jul 30 06:22:46 PM PDT 24 Jul 30 06:22:58 PM PDT 24 7457434326 ps
T343 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3934861393 Jul 30 06:22:50 PM PDT 24 Jul 30 06:22:52 PM PDT 24 511183577 ps
T344 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.708753782 Jul 30 06:22:35 PM PDT 24 Jul 30 06:22:36 PM PDT 24 418791592 ps
T345 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1834350932 Jul 30 06:22:30 PM PDT 24 Jul 30 06:22:31 PM PDT 24 650390905 ps
T79 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2786261773 Jul 30 06:22:42 PM PDT 24 Jul 30 06:22:43 PM PDT 24 2294881962 ps
T346 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2791028193 Jul 30 06:22:37 PM PDT 24 Jul 30 06:22:42 PM PDT 24 1677748474 ps
T347 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3127346642 Jul 30 06:22:34 PM PDT 24 Jul 30 06:22:47 PM PDT 24 8375423948 ps
T348 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2551071010 Jul 30 06:22:27 PM PDT 24 Jul 30 06:22:29 PM PDT 24 2691580948 ps
T349 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.945875128 Jul 30 06:22:26 PM PDT 24 Jul 30 06:22:27 PM PDT 24 414187110 ps
T350 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.56368912 Jul 30 06:22:43 PM PDT 24 Jul 30 06:22:45 PM PDT 24 525780309 ps
T351 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.532219574 Jul 30 06:22:34 PM PDT 24 Jul 30 06:22:47 PM PDT 24 8586843634 ps
T352 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3299911063 Jul 30 06:22:27 PM PDT 24 Jul 30 06:22:28 PM PDT 24 512895282 ps
T353 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1527585337 Jul 30 06:22:58 PM PDT 24 Jul 30 06:22:59 PM PDT 24 307653183 ps
T354 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2180454065 Jul 30 06:22:31 PM PDT 24 Jul 30 06:22:32 PM PDT 24 487820116 ps
T355 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.926814479 Jul 30 06:22:45 PM PDT 24 Jul 30 06:22:46 PM PDT 24 479172347 ps
T66 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2122918493 Jul 30 06:22:31 PM PDT 24 Jul 30 06:22:32 PM PDT 24 525238856 ps
T69 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2827501840 Jul 30 06:22:26 PM PDT 24 Jul 30 06:22:28 PM PDT 24 910232401 ps
T356 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.4259560669 Jul 30 06:22:28 PM PDT 24 Jul 30 06:22:29 PM PDT 24 691373912 ps
T357 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2442330250 Jul 30 06:22:26 PM PDT 24 Jul 30 06:22:28 PM PDT 24 356225802 ps
T358 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1250933934 Jul 30 06:23:01 PM PDT 24 Jul 30 06:23:02 PM PDT 24 448545460 ps
T359 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1117189039 Jul 30 06:22:49 PM PDT 24 Jul 30 06:22:50 PM PDT 24 513191287 ps
T360 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.488422852 Jul 30 06:22:41 PM PDT 24 Jul 30 06:22:42 PM PDT 24 559121561 ps
T361 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1009384833 Jul 30 06:22:46 PM PDT 24 Jul 30 06:22:50 PM PDT 24 2462305610 ps
T362 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2924200160 Jul 30 06:22:31 PM PDT 24 Jul 30 06:22:33 PM PDT 24 509383170 ps
T363 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3763057427 Jul 30 06:22:46 PM PDT 24 Jul 30 06:22:47 PM PDT 24 390939530 ps
T364 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.4007248681 Jul 30 06:22:34 PM PDT 24 Jul 30 06:22:37 PM PDT 24 2268914303 ps
T365 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2194924276 Jul 30 06:22:31 PM PDT 24 Jul 30 06:22:33 PM PDT 24 466711357 ps
T366 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2824231628 Jul 30 06:22:51 PM PDT 24 Jul 30 06:22:52 PM PDT 24 1168750607 ps
T367 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.248803384 Jul 30 06:22:37 PM PDT 24 Jul 30 06:22:52 PM PDT 24 7274729943 ps
T368 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3069316183 Jul 30 06:22:44 PM PDT 24 Jul 30 06:22:46 PM PDT 24 399483052 ps
T369 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.947290199 Jul 30 06:22:33 PM PDT 24 Jul 30 06:22:36 PM PDT 24 1369021600 ps
T370 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.4056055617 Jul 30 06:22:46 PM PDT 24 Jul 30 06:22:48 PM PDT 24 1523931834 ps
T371 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.24394880 Jul 30 06:23:03 PM PDT 24 Jul 30 06:23:04 PM PDT 24 328618048 ps
T192 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2230294413 Jul 30 06:22:34 PM PDT 24 Jul 30 06:22:39 PM PDT 24 7977175420 ps
T372 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3744930060 Jul 30 06:22:52 PM PDT 24 Jul 30 06:22:54 PM PDT 24 1338361018 ps
T373 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3620069065 Jul 30 06:22:29 PM PDT 24 Jul 30 06:22:30 PM PDT 24 272275985 ps
T70 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2482038502 Jul 30 06:22:23 PM PDT 24 Jul 30 06:22:25 PM PDT 24 307491106 ps
T71 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1895031028 Jul 30 06:22:30 PM PDT 24 Jul 30 06:22:34 PM PDT 24 6678976503 ps
T374 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1594880744 Jul 30 06:22:58 PM PDT 24 Jul 30 06:22:59 PM PDT 24 356414915 ps
T375 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.4257663204 Jul 30 06:22:59 PM PDT 24 Jul 30 06:22:59 PM PDT 24 492586011 ps
T376 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.836566395 Jul 30 06:23:07 PM PDT 24 Jul 30 06:23:08 PM PDT 24 343250732 ps
T377 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.90655313 Jul 30 06:22:40 PM PDT 24 Jul 30 06:22:42 PM PDT 24 493919584 ps
T378 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2386553165 Jul 30 06:23:03 PM PDT 24 Jul 30 06:23:04 PM PDT 24 291826416 ps
T379 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2911756526 Jul 30 06:22:48 PM PDT 24 Jul 30 06:23:02 PM PDT 24 8591517222 ps
T380 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.85643652 Jul 30 06:22:47 PM PDT 24 Jul 30 06:22:48 PM PDT 24 496345048 ps
T381 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2459927183 Jul 30 06:22:46 PM PDT 24 Jul 30 06:22:51 PM PDT 24 8308116206 ps
T382 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1452847369 Jul 30 06:22:34 PM PDT 24 Jul 30 06:22:35 PM PDT 24 405972823 ps
T383 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2172693705 Jul 30 06:22:30 PM PDT 24 Jul 30 06:22:32 PM PDT 24 2857425135 ps
T384 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1732170495 Jul 30 06:22:34 PM PDT 24 Jul 30 06:22:35 PM PDT 24 517101138 ps
T385 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1649599122 Jul 30 06:23:07 PM PDT 24 Jul 30 06:23:08 PM PDT 24 424565126 ps
T386 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.824754915 Jul 30 06:23:01 PM PDT 24 Jul 30 06:23:02 PM PDT 24 448541632 ps
T387 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.278606630 Jul 30 06:22:59 PM PDT 24 Jul 30 06:23:00 PM PDT 24 474331840 ps
T388 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.994364330 Jul 30 06:22:48 PM PDT 24 Jul 30 06:22:52 PM PDT 24 2371267910 ps
T389 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1228399645 Jul 30 06:22:41 PM PDT 24 Jul 30 06:22:43 PM PDT 24 574951918 ps
T390 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1218417102 Jul 30 06:22:37 PM PDT 24 Jul 30 06:22:40 PM PDT 24 4085343245 ps
T391 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1331588817 Jul 30 06:22:41 PM PDT 24 Jul 30 06:22:41 PM PDT 24 527411412 ps
T392 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.18141683 Jul 30 06:22:39 PM PDT 24 Jul 30 06:22:40 PM PDT 24 641541455 ps
T393 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.30545200 Jul 30 06:22:49 PM PDT 24 Jul 30 06:22:51 PM PDT 24 740134133 ps
T394 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.329679298 Jul 30 06:22:29 PM PDT 24 Jul 30 06:22:31 PM PDT 24 749195282 ps
T395 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3866530955 Jul 30 06:22:35 PM PDT 24 Jul 30 06:22:37 PM PDT 24 525748298 ps
T396 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.654379508 Jul 30 06:22:38 PM PDT 24 Jul 30 06:22:46 PM PDT 24 4580020391 ps
T397 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2072948274 Jul 30 06:22:29 PM PDT 24 Jul 30 06:22:35 PM PDT 24 4676630072 ps
T398 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1371333102 Jul 30 06:22:49 PM PDT 24 Jul 30 06:22:51 PM PDT 24 743251259 ps
T399 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2156037808 Jul 30 06:22:34 PM PDT 24 Jul 30 06:22:36 PM PDT 24 368770419 ps
T400 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1705098235 Jul 30 06:22:48 PM PDT 24 Jul 30 06:22:49 PM PDT 24 295406170 ps
T401 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.415826708 Jul 30 06:22:23 PM PDT 24 Jul 30 06:22:24 PM PDT 24 371355603 ps
T402 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2405890509 Jul 30 06:22:41 PM PDT 24 Jul 30 06:22:43 PM PDT 24 1203878472 ps
T67 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.4165529996 Jul 30 06:22:27 PM PDT 24 Jul 30 06:22:29 PM PDT 24 1018052682 ps
T403 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1805042067 Jul 30 06:22:44 PM PDT 24 Jul 30 06:22:47 PM PDT 24 1472665762 ps
T404 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2387094817 Jul 30 06:22:48 PM PDT 24 Jul 30 06:22:50 PM PDT 24 1281523496 ps
T405 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.473513659 Jul 30 06:22:31 PM PDT 24 Jul 30 06:22:33 PM PDT 24 447415300 ps
T406 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2237801078 Jul 30 06:22:36 PM PDT 24 Jul 30 06:22:37 PM PDT 24 451884279 ps
T407 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1330337329 Jul 30 06:22:36 PM PDT 24 Jul 30 06:22:37 PM PDT 24 452214366 ps
T408 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2248010280 Jul 30 06:22:44 PM PDT 24 Jul 30 06:22:46 PM PDT 24 535047398 ps
T409 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2914034791 Jul 30 06:22:43 PM PDT 24 Jul 30 06:22:44 PM PDT 24 1677746578 ps
T410 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3412185617 Jul 30 06:22:46 PM PDT 24 Jul 30 06:22:48 PM PDT 24 464140282 ps
T411 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.4225942827 Jul 30 06:22:30 PM PDT 24 Jul 30 06:22:31 PM PDT 24 341458177 ps
T412 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2007130826 Jul 30 06:22:31 PM PDT 24 Jul 30 06:22:32 PM PDT 24 294132999 ps
T413 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.104138440 Jul 30 06:22:39 PM PDT 24 Jul 30 06:22:41 PM PDT 24 316845058 ps
T414 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1841432345 Jul 30 06:22:28 PM PDT 24 Jul 30 06:22:29 PM PDT 24 400872221 ps
T415 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.385655950 Jul 30 06:22:46 PM PDT 24 Jul 30 06:22:47 PM PDT 24 352743281 ps
T416 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2621243235 Jul 30 06:22:47 PM PDT 24 Jul 30 06:22:59 PM PDT 24 8205293012 ps
T417 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.52339156 Jul 30 06:22:42 PM PDT 24 Jul 30 06:22:43 PM PDT 24 510936687 ps

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1316380034
Short name T8
Test name
Test status
Simulation time 185645000005 ps
CPU time 404.09 seconds
Started Jul 30 06:44:14 PM PDT 24
Finished Jul 30 06:50:58 PM PDT 24
Peak memory 214152 kb
Host smart-b4ff19cf-2873-4c79-967b-8ce3821d6e12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316380034 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1316380034
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.2610777030
Short name T48
Test name
Test status
Simulation time 496304457816 ps
CPU time 789.5 seconds
Started Jul 30 06:44:14 PM PDT 24
Finished Jul 30 06:57:24 PM PDT 24
Peak memory 214864 kb
Host smart-045361a5-7fa6-4b93-a1b3-987259f4d694
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610777030 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.2610777030
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.96488424
Short name T35
Test name
Test status
Simulation time 7792657226 ps
CPU time 6.75 seconds
Started Jul 30 06:22:45 PM PDT 24
Finished Jul 30 06:22:52 PM PDT 24
Peak memory 198376 kb
Host smart-c83628ff-44dc-465d-b06f-c6ff63e2d1a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96488424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_
intg_err.96488424
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.2015474023
Short name T17
Test name
Test status
Simulation time 65374795236 ps
CPU time 101.81 seconds
Started Jul 30 06:43:35 PM PDT 24
Finished Jul 30 06:45:16 PM PDT 24
Peak memory 198256 kb
Host smart-0ae8a554-16fd-4ebf-add7-89f5946b4766
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015474023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.2015474023
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.2174314096
Short name T84
Test name
Test status
Simulation time 1008000624767 ps
CPU time 533.43 seconds
Started Jul 30 06:44:13 PM PDT 24
Finished Jul 30 06:53:07 PM PDT 24
Peak memory 204296 kb
Host smart-ca6cbdad-c465-4c68-8143-0c530bbaa917
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174314096 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.2174314096
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.1298429346
Short name T31
Test name
Test status
Simulation time 87066087894 ps
CPU time 369.62 seconds
Started Jul 30 06:44:12 PM PDT 24
Finished Jul 30 06:50:22 PM PDT 24
Peak memory 202260 kb
Host smart-2f1349d6-bb76-4c80-b24d-90f0cc532955
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298429346 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.1298429346
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1090649928
Short name T86
Test name
Test status
Simulation time 15347987883 ps
CPU time 100.85 seconds
Started Jul 30 06:44:14 PM PDT 24
Finished Jul 30 06:45:55 PM PDT 24
Peak memory 206692 kb
Host smart-d862f2af-5183-4f8c-8a7b-117f09047ab7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090649928 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.1090649928
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.3447880577
Short name T51
Test name
Test status
Simulation time 489754069919 ps
CPU time 221.63 seconds
Started Jul 30 06:43:32 PM PDT 24
Finished Jul 30 06:47:14 PM PDT 24
Peak memory 208700 kb
Host smart-63d44738-601c-4812-a9c4-97cc1d2402d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447880577 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.3447880577
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2564499025
Short name T101
Test name
Test status
Simulation time 399481431950 ps
CPU time 637.36 seconds
Started Jul 30 06:43:54 PM PDT 24
Finished Jul 30 06:54:31 PM PDT 24
Peak memory 206748 kb
Host smart-c04a04a5-0c89-458d-b0be-44c97d20828b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564499025 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2564499025
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.3307238720
Short name T4
Test name
Test status
Simulation time 794654245734 ps
CPU time 253.26 seconds
Started Jul 30 06:43:25 PM PDT 24
Finished Jul 30 06:47:39 PM PDT 24
Peak memory 193064 kb
Host smart-f433e1f9-ece5-4f6a-95c4-880f98771267
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307238720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.3307238720
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.599708354
Short name T102
Test name
Test status
Simulation time 98275695488 ps
CPU time 136.98 seconds
Started Jul 30 06:43:59 PM PDT 24
Finished Jul 30 06:46:16 PM PDT 24
Peak memory 192992 kb
Host smart-2f2a41f9-1f14-48fa-97b0-ff4d95e86a8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599708354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_a
ll.599708354
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.3067756126
Short name T14
Test name
Test status
Simulation time 4462373017 ps
CPU time 3.8 seconds
Started Jul 30 06:43:23 PM PDT 24
Finished Jul 30 06:43:27 PM PDT 24
Peak memory 215756 kb
Host smart-a05707b4-39c4-4726-b311-f2b216878e6e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067756126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.3067756126
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.1689569394
Short name T106
Test name
Test status
Simulation time 51212482414 ps
CPU time 4.66 seconds
Started Jul 30 06:43:50 PM PDT 24
Finished Jul 30 06:43:55 PM PDT 24
Peak memory 198260 kb
Host smart-6d36127a-4c3e-4f36-90aa-ce24746b4d70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689569394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.1689569394
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.3670326555
Short name T89
Test name
Test status
Simulation time 31538709057 ps
CPU time 237.73 seconds
Started Jul 30 06:44:12 PM PDT 24
Finished Jul 30 06:48:10 PM PDT 24
Peak memory 198508 kb
Host smart-39b7830c-943f-4966-9203-353d8bd7546b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670326555 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.3670326555
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.4014753714
Short name T109
Test name
Test status
Simulation time 127571712397 ps
CPU time 189.7 seconds
Started Jul 30 06:43:32 PM PDT 24
Finished Jul 30 06:46:42 PM PDT 24
Peak memory 198232 kb
Host smart-e8fdf45e-1cad-4f07-99b5-2f9c36b1e8ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014753714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.4014753714
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.2322154163
Short name T103
Test name
Test status
Simulation time 110126594188 ps
CPU time 40.48 seconds
Started Jul 30 06:43:40 PM PDT 24
Finished Jul 30 06:44:20 PM PDT 24
Peak memory 192948 kb
Host smart-9978b813-43ca-416d-b885-1871c9a9dc4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322154163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.2322154163
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.389593509
Short name T85
Test name
Test status
Simulation time 145607902734 ps
CPU time 999.77 seconds
Started Jul 30 06:43:58 PM PDT 24
Finished Jul 30 07:00:38 PM PDT 24
Peak memory 209312 kb
Host smart-eb813349-cf6b-4f60-8b70-449366772c0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389593509 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.389593509
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.125117650
Short name T91
Test name
Test status
Simulation time 105912433826 ps
CPU time 199.28 seconds
Started Jul 30 06:43:35 PM PDT 24
Finished Jul 30 06:46:54 PM PDT 24
Peak memory 214832 kb
Host smart-db5210ef-a5cc-4345-87a1-b6df302b6121
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125117650 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.125117650
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.3352675696
Short name T104
Test name
Test status
Simulation time 76484100711 ps
CPU time 24.07 seconds
Started Jul 30 06:44:17 PM PDT 24
Finished Jul 30 06:44:41 PM PDT 24
Peak memory 192932 kb
Host smart-169f53d7-fcf8-4c15-9372-14b2ba154b07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352675696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.3352675696
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.3154053768
Short name T107
Test name
Test status
Simulation time 35915520338 ps
CPU time 3.99 seconds
Started Jul 30 06:44:07 PM PDT 24
Finished Jul 30 06:44:11 PM PDT 24
Peak memory 192980 kb
Host smart-860efd03-a3c2-4cf2-a18a-5c66a55dd4e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154053768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.3154053768
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.1339946607
Short name T21
Test name
Test status
Simulation time 449470513323 ps
CPU time 1232.32 seconds
Started Jul 30 06:43:28 PM PDT 24
Finished Jul 30 07:04:01 PM PDT 24
Peak memory 213248 kb
Host smart-42f73b54-918a-49e8-98f5-290628431f8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339946607 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.1339946607
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.2277461931
Short name T143
Test name
Test status
Simulation time 288803684816 ps
CPU time 638 seconds
Started Jul 30 06:43:32 PM PDT 24
Finished Jul 30 06:54:10 PM PDT 24
Peak memory 213916 kb
Host smart-1a729122-6e56-439b-a422-f82cbce91420
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277461931 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.2277461931
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.757555846
Short name T13
Test name
Test status
Simulation time 50304329027 ps
CPU time 420.56 seconds
Started Jul 30 06:43:48 PM PDT 24
Finished Jul 30 06:50:48 PM PDT 24
Peak memory 200060 kb
Host smart-3bb5a369-c77c-405e-ab2d-849bf1b2f0a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757555846 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.757555846
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.2997756800
Short name T80
Test name
Test status
Simulation time 99528554784 ps
CPU time 514.41 seconds
Started Jul 30 06:43:58 PM PDT 24
Finished Jul 30 06:52:32 PM PDT 24
Peak memory 209288 kb
Host smart-17664f57-b398-4c9c-9c61-1b7977430cb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997756800 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.2997756800
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.297969145
Short name T105
Test name
Test status
Simulation time 50015568209 ps
CPU time 506.1 seconds
Started Jul 30 06:44:07 PM PDT 24
Finished Jul 30 06:52:33 PM PDT 24
Peak memory 201904 kb
Host smart-5e0c36a5-5aa8-446f-aecb-11fe5d5aba2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297969145 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.297969145
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.369540380
Short name T82
Test name
Test status
Simulation time 1253629306477 ps
CPU time 766.73 seconds
Started Jul 30 06:44:08 PM PDT 24
Finished Jul 30 06:56:55 PM PDT 24
Peak memory 208164 kb
Host smart-ae08d0c6-a6c1-4ac8-b37d-c5b82843c44e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369540380 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.369540380
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2787375729
Short name T151
Test name
Test status
Simulation time 68098555292 ps
CPU time 529.97 seconds
Started Jul 30 06:44:43 PM PDT 24
Finished Jul 30 06:53:33 PM PDT 24
Peak memory 202996 kb
Host smart-03106376-aa77-41d9-92fe-b4fa3b4c3b87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787375729 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2787375729
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.2225868612
Short name T26
Test name
Test status
Simulation time 122630620655 ps
CPU time 1025.14 seconds
Started Jul 30 06:43:48 PM PDT 24
Finished Jul 30 07:00:58 PM PDT 24
Peak memory 214880 kb
Host smart-5d966cf2-cf36-4cce-8e0d-abaaddc28216
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225868612 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.2225868612
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.3469087100
Short name T90
Test name
Test status
Simulation time 29432657117 ps
CPU time 211.19 seconds
Started Jul 30 06:44:15 PM PDT 24
Finished Jul 30 06:47:46 PM PDT 24
Peak memory 198596 kb
Host smart-231edf9f-2846-4a83-89cc-2aaa1ccea224
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469087100 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.3469087100
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1574543706
Short name T41
Test name
Test status
Simulation time 183122532693 ps
CPU time 335.42 seconds
Started Jul 30 06:43:30 PM PDT 24
Finished Jul 30 06:49:05 PM PDT 24
Peak memory 214080 kb
Host smart-b45110f3-5f44-4a6d-b45c-f08d81336a3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574543706 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1574543706
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1086025059
Short name T58
Test name
Test status
Simulation time 422085409 ps
CPU time 0.82 seconds
Started Jul 30 06:22:46 PM PDT 24
Finished Jul 30 06:22:47 PM PDT 24
Peak memory 192916 kb
Host smart-0742e3b8-c124-44fa-9356-0f56aa170bc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086025059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1086025059
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.1750198187
Short name T112
Test name
Test status
Simulation time 581363017275 ps
CPU time 827.57 seconds
Started Jul 30 06:43:35 PM PDT 24
Finished Jul 30 06:57:23 PM PDT 24
Peak memory 191884 kb
Host smart-97f3757f-c712-4959-b712-7b12d364c18b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750198187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.1750198187
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2286620257
Short name T130
Test name
Test status
Simulation time 54983717451 ps
CPU time 283.78 seconds
Started Jul 30 06:43:43 PM PDT 24
Finished Jul 30 06:48:27 PM PDT 24
Peak memory 207896 kb
Host smart-8ab47d6b-947a-404f-b023-b9535657743b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286620257 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2286620257
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.776722478
Short name T149
Test name
Test status
Simulation time 25328930155 ps
CPU time 39.52 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:59 PM PDT 24
Peak memory 192564 kb
Host smart-31c5dbef-0d58-4039-b952-1f048a44d158
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776722478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_a
ll.776722478
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3560522867
Short name T42
Test name
Test status
Simulation time 90501452477 ps
CPU time 376.55 seconds
Started Jul 30 06:43:27 PM PDT 24
Finished Jul 30 06:49:44 PM PDT 24
Peak memory 210688 kb
Host smart-d17148e7-cb69-43f1-8f57-5c3caa9a1615
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560522867 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3560522867
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.900911384
Short name T108
Test name
Test status
Simulation time 110597794419 ps
CPU time 39.42 seconds
Started Jul 30 06:44:35 PM PDT 24
Finished Jul 30 06:45:14 PM PDT 24
Peak memory 192736 kb
Host smart-e43bf01e-79d5-4ed8-b449-d106d82aba5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900911384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_al
l.900911384
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.3779823414
Short name T81
Test name
Test status
Simulation time 163484040276 ps
CPU time 427.28 seconds
Started Jul 30 06:43:43 PM PDT 24
Finished Jul 30 06:50:50 PM PDT 24
Peak memory 206720 kb
Host smart-c9572a9a-76de-4182-bea1-389ff1cb0cad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779823414 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.3779823414
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.2149630928
Short name T100
Test name
Test status
Simulation time 161074908791 ps
CPU time 261.26 seconds
Started Jul 30 06:43:57 PM PDT 24
Finished Jul 30 06:48:18 PM PDT 24
Peak memory 192948 kb
Host smart-ae14ff6e-5e29-4f35-b2f8-9facbfaed704
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149630928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.2149630928
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.1342279762
Short name T126
Test name
Test status
Simulation time 131120452796 ps
CPU time 46.42 seconds
Started Jul 30 06:44:05 PM PDT 24
Finished Jul 30 06:44:52 PM PDT 24
Peak memory 191884 kb
Host smart-f5b23ec8-1eaf-4852-8386-8bb383c9fddd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342279762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.1342279762
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.1025326878
Short name T123
Test name
Test status
Simulation time 35482078582 ps
CPU time 179.27 seconds
Started Jul 30 06:43:27 PM PDT 24
Finished Jul 30 06:46:27 PM PDT 24
Peak memory 198180 kb
Host smart-701309a0-1fed-4a3c-94a9-0ffe3ba9d77b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025326878 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.1025326878
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.626510605
Short name T87
Test name
Test status
Simulation time 53405769692 ps
CPU time 394.99 seconds
Started Jul 30 06:43:24 PM PDT 24
Finished Jul 30 06:50:00 PM PDT 24
Peak memory 200360 kb
Host smart-3e635046-c54b-4946-af7b-f29fee33cf6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626510605 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.626510605
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.3654561757
Short name T32
Test name
Test status
Simulation time 15627562794 ps
CPU time 127.61 seconds
Started Jul 30 06:43:30 PM PDT 24
Finished Jul 30 06:45:38 PM PDT 24
Peak memory 214468 kb
Host smart-2e1ea67a-b24b-4d49-834a-3e59d86dfa42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654561757 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.3654561757
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.3851942863
Short name T147
Test name
Test status
Simulation time 72401807685 ps
CPU time 110.1 seconds
Started Jul 30 06:43:43 PM PDT 24
Finished Jul 30 06:45:33 PM PDT 24
Peak memory 198232 kb
Host smart-ad94f6c5-b47f-4b6f-9154-31bd55312c8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851942863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.3851942863
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.51484690
Short name T113
Test name
Test status
Simulation time 39624767786 ps
CPU time 59.51 seconds
Started Jul 30 06:43:36 PM PDT 24
Finished Jul 30 06:44:36 PM PDT 24
Peak memory 192968 kb
Host smart-6b2b44b5-66b0-43f0-ab8d-4b40ed5cffef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51484690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_al
l.51484690
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.1494800079
Short name T111
Test name
Test status
Simulation time 65432316821 ps
CPU time 33.75 seconds
Started Jul 30 06:43:24 PM PDT 24
Finished Jul 30 06:43:58 PM PDT 24
Peak memory 191904 kb
Host smart-1f1f588d-d02d-4caf-9832-d2f6c555ae7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494800079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.1494800079
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.483013245
Short name T122
Test name
Test status
Simulation time 172361871023 ps
CPU time 44.57 seconds
Started Jul 30 06:44:39 PM PDT 24
Finished Jul 30 06:45:24 PM PDT 24
Peak memory 191608 kb
Host smart-829871a0-7f9b-4b6c-a20f-23e7bc087908
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483013245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_al
l.483013245
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.2574002973
Short name T1
Test name
Test status
Simulation time 358114492586 ps
CPU time 418.95 seconds
Started Jul 30 06:43:30 PM PDT 24
Finished Jul 30 06:50:29 PM PDT 24
Peak memory 213296 kb
Host smart-faf226da-d2ce-4bc9-92c5-7fb62aedd8dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574002973 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.2574002973
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.3506822528
Short name T156
Test name
Test status
Simulation time 21396057810 ps
CPU time 219.95 seconds
Started Jul 30 06:43:51 PM PDT 24
Finished Jul 30 06:47:36 PM PDT 24
Peak memory 198468 kb
Host smart-80dbd78a-2c1d-4c9b-bf76-98a66c4ed625
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506822528 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.3506822528
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2922086682
Short name T139
Test name
Test status
Simulation time 154835311933 ps
CPU time 202.97 seconds
Started Jul 30 06:44:05 PM PDT 24
Finished Jul 30 06:47:29 PM PDT 24
Peak memory 193020 kb
Host smart-67f6af2c-16df-4a7d-9e92-47c0203bcd7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922086682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2922086682
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.147338437
Short name T163
Test name
Test status
Simulation time 260573389664 ps
CPU time 41.21 seconds
Started Jul 30 06:43:34 PM PDT 24
Finished Jul 30 06:44:15 PM PDT 24
Peak memory 192680 kb
Host smart-87fd9d6b-851e-4128-89d6-de1d7d8c674a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147338437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_al
l.147338437
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.1628574165
Short name T176
Test name
Test status
Simulation time 103417202138 ps
CPU time 433.74 seconds
Started Jul 30 06:43:35 PM PDT 24
Finished Jul 30 06:50:49 PM PDT 24
Peak memory 211048 kb
Host smart-c78932bf-aa17-4d59-a7b5-56076cf78515
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628574165 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.1628574165
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.1355759605
Short name T114
Test name
Test status
Simulation time 122932119709 ps
CPU time 43.25 seconds
Started Jul 30 06:44:09 PM PDT 24
Finished Jul 30 06:44:53 PM PDT 24
Peak memory 191936 kb
Host smart-f50a3228-f627-4386-9482-060d14975395
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355759605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.1355759605
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.2170031735
Short name T22
Test name
Test status
Simulation time 99576717941 ps
CPU time 142.61 seconds
Started Jul 30 06:43:58 PM PDT 24
Finished Jul 30 06:46:21 PM PDT 24
Peak memory 192912 kb
Host smart-f1ffaad8-e692-4dc6-92d5-03dcdb5c9b8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170031735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.2170031735
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2388028615
Short name T155
Test name
Test status
Simulation time 109152014431 ps
CPU time 81.23 seconds
Started Jul 30 06:43:55 PM PDT 24
Finished Jul 30 06:45:17 PM PDT 24
Peak memory 192916 kb
Host smart-767e5f62-8b3c-438e-9251-f955223f26f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388028615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2388028615
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3251948591
Short name T153
Test name
Test status
Simulation time 565097546869 ps
CPU time 383.49 seconds
Started Jul 30 06:43:45 PM PDT 24
Finished Jul 30 06:50:08 PM PDT 24
Peak memory 192444 kb
Host smart-9ed4cf04-5ca4-48af-8459-42cf3ec373cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251948591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3251948591
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2601869697
Short name T47
Test name
Test status
Simulation time 669665500241 ps
CPU time 994.17 seconds
Started Jul 30 06:43:51 PM PDT 24
Finished Jul 30 07:00:26 PM PDT 24
Peak memory 198216 kb
Host smart-3d5e0de8-23fb-4697-87c7-4ccc0ab4224c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601869697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2601869697
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.3888481185
Short name T20
Test name
Test status
Simulation time 294245401760 ps
CPU time 112.59 seconds
Started Jul 30 06:43:38 PM PDT 24
Finished Jul 30 06:45:30 PM PDT 24
Peak memory 198244 kb
Host smart-ce0466a2-0cff-43e3-895d-1df63eae1135
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888481185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.3888481185
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.51717220
Short name T6
Test name
Test status
Simulation time 33704685533 ps
CPU time 89.14 seconds
Started Jul 30 06:43:46 PM PDT 24
Finished Jul 30 06:45:16 PM PDT 24
Peak memory 213200 kb
Host smart-495d0854-710a-4a03-b0b5-1701e43a13ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51717220 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.51717220
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.3468313054
Short name T138
Test name
Test status
Simulation time 501087668772 ps
CPU time 382.16 seconds
Started Jul 30 06:44:09 PM PDT 24
Finished Jul 30 06:50:32 PM PDT 24
Peak memory 191884 kb
Host smart-e0876342-89f3-473b-a521-33e30d8837ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468313054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.3468313054
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.1867027873
Short name T40
Test name
Test status
Simulation time 132201733073 ps
CPU time 341.61 seconds
Started Jul 30 06:44:06 PM PDT 24
Finished Jul 30 06:49:48 PM PDT 24
Peak memory 213804 kb
Host smart-280c9eb5-dfbe-44e9-8c3f-4e871d5c68c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867027873 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.1867027873
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.3279566319
Short name T124
Test name
Test status
Simulation time 97270811198 ps
CPU time 38.99 seconds
Started Jul 30 06:43:52 PM PDT 24
Finished Jul 30 06:44:31 PM PDT 24
Peak memory 191876 kb
Host smart-fbe25540-de0f-4976-912e-1bfc24dd2267
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279566319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.3279566319
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3148621941
Short name T135
Test name
Test status
Simulation time 98447163600 ps
CPU time 52.81 seconds
Started Jul 30 06:43:51 PM PDT 24
Finished Jul 30 06:44:43 PM PDT 24
Peak memory 192996 kb
Host smart-2dc48511-ee30-4682-92a4-167afcd0b293
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148621941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3148621941
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.2585413668
Short name T120
Test name
Test status
Simulation time 82464584502 ps
CPU time 124.23 seconds
Started Jul 30 06:43:57 PM PDT 24
Finished Jul 30 06:46:01 PM PDT 24
Peak memory 191884 kb
Host smart-1e83f1d0-9667-4f4d-a433-59c5ccf80e3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585413668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.2585413668
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.4292196343
Short name T118
Test name
Test status
Simulation time 109162844139 ps
CPU time 154.61 seconds
Started Jul 30 06:43:38 PM PDT 24
Finished Jul 30 06:46:13 PM PDT 24
Peak memory 198240 kb
Host smart-5d5b988a-efcf-468d-a97c-ea0855ff500c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292196343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.4292196343
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.1337497280
Short name T136
Test name
Test status
Simulation time 183833259945 ps
CPU time 255.41 seconds
Started Jul 30 06:43:26 PM PDT 24
Finished Jul 30 06:47:42 PM PDT 24
Peak memory 192804 kb
Host smart-2aa0debd-1f04-40ba-85b2-aed0cf17313c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337497280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.1337497280
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1125006050
Short name T5
Test name
Test status
Simulation time 108555119657 ps
CPU time 209.51 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:47:49 PM PDT 24
Peak memory 208588 kb
Host smart-a8e734a4-7e26-4027-abd5-2d45accc3915
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125006050 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1125006050
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.4099412102
Short name T158
Test name
Test status
Simulation time 595812203 ps
CPU time 0.8 seconds
Started Jul 30 06:43:37 PM PDT 24
Finished Jul 30 06:43:38 PM PDT 24
Peak memory 196676 kb
Host smart-ab1c8559-18a9-4361-97ee-440e1b95dec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099412102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.4099412102
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.844572324
Short name T53
Test name
Test status
Simulation time 627798832 ps
CPU time 0.81 seconds
Started Jul 30 06:44:39 PM PDT 24
Finished Jul 30 06:44:40 PM PDT 24
Peak memory 196372 kb
Host smart-390eac18-fc97-4bcd-aabd-b6efd0baafdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844572324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.844572324
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.3456294288
Short name T88
Test name
Test status
Simulation time 25586571184 ps
CPU time 44.67 seconds
Started Jul 30 06:43:58 PM PDT 24
Finished Jul 30 06:44:42 PM PDT 24
Peak memory 206688 kb
Host smart-5e9787fb-7fc5-47ca-82d9-659b47ef9bb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456294288 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.3456294288
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.4044004569
Short name T83
Test name
Test status
Simulation time 43887448020 ps
CPU time 294.89 seconds
Started Jul 30 06:43:57 PM PDT 24
Finished Jul 30 06:48:52 PM PDT 24
Peak memory 206688 kb
Host smart-f6575fea-1b27-4e4f-9d86-a75cef64d7e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044004569 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.4044004569
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.3641322849
Short name T99
Test name
Test status
Simulation time 557291625 ps
CPU time 0.99 seconds
Started Jul 30 06:43:25 PM PDT 24
Finished Jul 30 06:43:27 PM PDT 24
Peak memory 196664 kb
Host smart-5b58c8fa-6560-4c68-bb55-be64f04f22ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641322849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.3641322849
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.2847608755
Short name T54
Test name
Test status
Simulation time 14934334899 ps
CPU time 69.84 seconds
Started Jul 30 06:44:13 PM PDT 24
Finished Jul 30 06:45:23 PM PDT 24
Peak memory 206676 kb
Host smart-9b095eaf-0372-45ff-bb77-685a94fe0663
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847608755 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.2847608755
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1247628340
Short name T121
Test name
Test status
Simulation time 33138903431 ps
CPU time 52.16 seconds
Started Jul 30 06:44:13 PM PDT 24
Finished Jul 30 06:45:05 PM PDT 24
Peak memory 198232 kb
Host smart-554ba8a4-2ed2-42b0-b8ba-368ccae2cd55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247628340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1247628340
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.1517578408
Short name T160
Test name
Test status
Simulation time 60911795360 ps
CPU time 42.12 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:45:06 PM PDT 24
Peak memory 192944 kb
Host smart-9f5cddee-c341-48a5-b2cf-7e8b965f1e13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517578408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.1517578408
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_jump.3806121241
Short name T129
Test name
Test status
Simulation time 494814680 ps
CPU time 1.29 seconds
Started Jul 30 06:43:27 PM PDT 24
Finished Jul 30 06:43:28 PM PDT 24
Peak memory 196752 kb
Host smart-3d16a533-a3de-4bba-aebd-4a483076442c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806121241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.3806121241
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3002087691
Short name T154
Test name
Test status
Simulation time 170261306252 ps
CPU time 132.73 seconds
Started Jul 30 06:43:53 PM PDT 24
Finished Jul 30 06:46:06 PM PDT 24
Peak memory 191900 kb
Host smart-ebbf87b0-f7e0-429a-9641-a75185878a93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002087691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3002087691
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_jump.3969855230
Short name T98
Test name
Test status
Simulation time 407244558 ps
CPU time 0.72 seconds
Started Jul 30 06:44:09 PM PDT 24
Finished Jul 30 06:44:09 PM PDT 24
Peak memory 196600 kb
Host smart-20d6af8f-06bc-4e0f-9d78-35294c319c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969855230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.3969855230
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.189868793
Short name T140
Test name
Test status
Simulation time 156006177492 ps
CPU time 49.73 seconds
Started Jul 30 06:44:07 PM PDT 24
Finished Jul 30 06:44:57 PM PDT 24
Peak memory 192996 kb
Host smart-16d206ef-51bb-4c26-9dc8-f05f6578ccfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189868793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_a
ll.189868793
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1306348820
Short name T55
Test name
Test status
Simulation time 385409085 ps
CPU time 0.91 seconds
Started Jul 30 06:44:05 PM PDT 24
Finished Jul 30 06:44:06 PM PDT 24
Peak memory 196672 kb
Host smart-e9d599f3-8079-44de-b8c0-9dd7675b1c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306348820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1306348820
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_jump.726298307
Short name T159
Test name
Test status
Simulation time 471296727 ps
CPU time 1.3 seconds
Started Jul 30 06:44:12 PM PDT 24
Finished Jul 30 06:44:13 PM PDT 24
Peak memory 196740 kb
Host smart-f197df8b-a1e1-4e89-a000-9acceaa183ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726298307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.726298307
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.3251167501
Short name T157
Test name
Test status
Simulation time 492744054 ps
CPU time 1.31 seconds
Started Jul 30 06:44:22 PM PDT 24
Finished Jul 30 06:44:26 PM PDT 24
Peak memory 196664 kb
Host smart-5ecb5f29-2993-4689-a95e-92dfe76fabef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251167501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.3251167501
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.3037743708
Short name T56
Test name
Test status
Simulation time 475027108 ps
CPU time 1.29 seconds
Started Jul 30 06:44:16 PM PDT 24
Finished Jul 30 06:44:18 PM PDT 24
Peak memory 196588 kb
Host smart-df8308cd-3b98-4a58-8722-3ca715647755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037743708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3037743708
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1966336637
Short name T132
Test name
Test status
Simulation time 504431166 ps
CPU time 1 seconds
Started Jul 30 06:44:14 PM PDT 24
Finished Jul 30 06:44:15 PM PDT 24
Peak memory 196636 kb
Host smart-c1ca1c14-7dca-4a01-9f31-929812cfc96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966336637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1966336637
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.528378264
Short name T144
Test name
Test status
Simulation time 422675610 ps
CPU time 1.28 seconds
Started Jul 30 06:43:31 PM PDT 24
Finished Jul 30 06:43:32 PM PDT 24
Peak memory 196660 kb
Host smart-1fd8d6bf-45f7-4163-b3f5-172cda4c7111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528378264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.528378264
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.80510627
Short name T142
Test name
Test status
Simulation time 369205303 ps
CPU time 0.77 seconds
Started Jul 30 06:43:26 PM PDT 24
Finished Jul 30 06:43:27 PM PDT 24
Peak memory 196660 kb
Host smart-9a75823b-ccac-453f-a70e-0edc2e7259d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80510627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.80510627
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.1220107908
Short name T137
Test name
Test status
Simulation time 61123796159 ps
CPU time 87 seconds
Started Jul 30 06:43:42 PM PDT 24
Finished Jul 30 06:45:09 PM PDT 24
Peak memory 191864 kb
Host smart-70a89d4a-52a4-4951-bcb1-779674defde4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220107908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.1220107908
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1967654791
Short name T148
Test name
Test status
Simulation time 587933063 ps
CPU time 0.75 seconds
Started Jul 30 06:44:38 PM PDT 24
Finished Jul 30 06:44:39 PM PDT 24
Peak memory 196344 kb
Host smart-ed82206e-4a38-4acf-adb8-67e1e99de5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967654791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1967654791
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.2136680136
Short name T150
Test name
Test status
Simulation time 417459399 ps
CPU time 0.7 seconds
Started Jul 30 06:43:35 PM PDT 24
Finished Jul 30 06:43:36 PM PDT 24
Peak memory 196588 kb
Host smart-6d873785-7368-45a3-b496-ca1618383f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136680136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2136680136
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.752757803
Short name T44
Test name
Test status
Simulation time 222166542372 ps
CPU time 336.57 seconds
Started Jul 30 06:44:11 PM PDT 24
Finished Jul 30 06:49:48 PM PDT 24
Peak memory 198284 kb
Host smart-f7b0939a-ec3e-4930-9c08-58d3e0b7b3a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752757803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_a
ll.752757803
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3799826784
Short name T116
Test name
Test status
Simulation time 575707333 ps
CPU time 0.83 seconds
Started Jul 30 06:43:59 PM PDT 24
Finished Jul 30 06:44:00 PM PDT 24
Peak memory 196676 kb
Host smart-df8de86f-dee8-417e-a4f0-a9308a681d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799826784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3799826784
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.604304813
Short name T134
Test name
Test status
Simulation time 238585789873 ps
CPU time 66.69 seconds
Started Jul 30 06:44:11 PM PDT 24
Finished Jul 30 06:45:18 PM PDT 24
Peak memory 192884 kb
Host smart-ddf3b88a-67df-424f-9bbc-d5707f14681c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604304813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_a
ll.604304813
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1102754902
Short name T119
Test name
Test status
Simulation time 581210808 ps
CPU time 1.4 seconds
Started Jul 30 06:44:18 PM PDT 24
Finished Jul 30 06:44:19 PM PDT 24
Peak memory 196656 kb
Host smart-6cf0c6fb-64d8-4ad0-8b10-b93c1da94c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102754902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1102754902
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.259211196
Short name T152
Test name
Test status
Simulation time 146340350277 ps
CPU time 219.64 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:48:03 PM PDT 24
Peak memory 198224 kb
Host smart-c8126506-02d9-4234-93e8-c341481bad15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259211196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_a
ll.259211196
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_jump.290615237
Short name T128
Test name
Test status
Simulation time 383297385 ps
CPU time 1.09 seconds
Started Jul 30 06:43:41 PM PDT 24
Finished Jul 30 06:43:42 PM PDT 24
Peak memory 196660 kb
Host smart-a7754e79-d8c3-4044-82e2-2682b871516a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290615237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.290615237
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.2423887381
Short name T131
Test name
Test status
Simulation time 412345547 ps
CPU time 0.66 seconds
Started Jul 30 06:43:42 PM PDT 24
Finished Jul 30 06:43:42 PM PDT 24
Peak memory 196616 kb
Host smart-4816cf38-0103-4ce8-9043-75fef01a7920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423887381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.2423887381
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.633890892
Short name T146
Test name
Test status
Simulation time 437880163 ps
CPU time 1.41 seconds
Started Jul 30 06:43:52 PM PDT 24
Finished Jul 30 06:43:54 PM PDT 24
Peak memory 196736 kb
Host smart-016ef40a-3e7b-416c-907d-8d90e3e68c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633890892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.633890892
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.52419554
Short name T161
Test name
Test status
Simulation time 497119280 ps
CPU time 0.65 seconds
Started Jul 30 06:43:53 PM PDT 24
Finished Jul 30 06:43:54 PM PDT 24
Peak memory 196648 kb
Host smart-f85a24f3-3c1d-4c14-8391-b6b45283ae76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52419554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.52419554
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.296377069
Short name T164
Test name
Test status
Simulation time 172472116368 ps
CPU time 142.2 seconds
Started Jul 30 06:44:03 PM PDT 24
Finished Jul 30 06:46:26 PM PDT 24
Peak memory 198228 kb
Host smart-07e9f2e2-6002-4bb7-945e-aa8618ac699b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296377069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_a
ll.296377069
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.3775643183
Short name T166
Test name
Test status
Simulation time 113234733724 ps
CPU time 85.74 seconds
Started Jul 30 06:44:14 PM PDT 24
Finished Jul 30 06:45:40 PM PDT 24
Peak memory 198252 kb
Host smart-d256a7a4-62a6-40a0-8213-67470a14fec4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775643183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.3775643183
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3761476077
Short name T162
Test name
Test status
Simulation time 332090010416 ps
CPU time 476.33 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:52:17 PM PDT 24
Peak memory 192976 kb
Host smart-06bb9e3d-bc95-45a5-857f-677777fd08f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761476077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3761476077
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_jump.4062518345
Short name T115
Test name
Test status
Simulation time 402381707 ps
CPU time 1.08 seconds
Started Jul 30 06:43:25 PM PDT 24
Finished Jul 30 06:43:31 PM PDT 24
Peak memory 196628 kb
Host smart-71980a16-bba1-4baa-b859-ab29ca4e6cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062518345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.4062518345
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.1951283658
Short name T145
Test name
Test status
Simulation time 469818463 ps
CPU time 0.81 seconds
Started Jul 30 06:43:22 PM PDT 24
Finished Jul 30 06:43:23 PM PDT 24
Peak memory 196732 kb
Host smart-c7bcd15c-7f30-4d16-9cd9-4c0d1a34bc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951283658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.1951283658
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.378647938
Short name T172
Test name
Test status
Simulation time 120205038997 ps
CPU time 173.51 seconds
Started Jul 30 06:43:30 PM PDT 24
Finished Jul 30 06:46:24 PM PDT 24
Peak memory 198244 kb
Host smart-2b9a8970-b031-4cfe-9b07-59af83a42ca3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378647938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_a
ll.378647938
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.3552795290
Short name T171
Test name
Test status
Simulation time 57859400767 ps
CPU time 21.61 seconds
Started Jul 30 06:43:33 PM PDT 24
Finished Jul 30 06:43:55 PM PDT 24
Peak memory 192936 kb
Host smart-88a2d02b-cb1c-4c11-9407-5c4da4256fe5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552795290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.3552795290
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_jump.570994747
Short name T110
Test name
Test status
Simulation time 432862885 ps
CPU time 0.73 seconds
Started Jul 30 06:43:52 PM PDT 24
Finished Jul 30 06:43:53 PM PDT 24
Peak memory 196668 kb
Host smart-ce1bb80d-2163-4c62-9535-f95d8697edf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570994747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.570994747
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.3462018059
Short name T28
Test name
Test status
Simulation time 293606600807 ps
CPU time 176.3 seconds
Started Jul 30 06:43:55 PM PDT 24
Finished Jul 30 06:46:52 PM PDT 24
Peak memory 199812 kb
Host smart-63b01fff-4c94-4957-92c5-472f07fd5156
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462018059 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.3462018059
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1677309923
Short name T117
Test name
Test status
Simulation time 444038934 ps
CPU time 0.78 seconds
Started Jul 30 06:43:58 PM PDT 24
Finished Jul 30 06:43:59 PM PDT 24
Peak memory 196636 kb
Host smart-fb139be2-2b53-4fa1-891f-782022f7c9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677309923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1677309923
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_jump.1302202017
Short name T24
Test name
Test status
Simulation time 439207314 ps
CPU time 1.25 seconds
Started Jul 30 06:43:30 PM PDT 24
Finished Jul 30 06:43:32 PM PDT 24
Peak memory 196628 kb
Host smart-821acf5e-6d16-4bc2-bbd9-23e6b35eeb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302202017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1302202017
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.2253880829
Short name T95
Test name
Test status
Simulation time 555863293 ps
CPU time 0.98 seconds
Started Jul 30 06:43:32 PM PDT 24
Finished Jul 30 06:43:33 PM PDT 24
Peak memory 196632 kb
Host smart-1358b6b8-dcef-422a-809c-dced1bc14f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253880829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2253880829
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1865273168
Short name T30
Test name
Test status
Simulation time 552953664 ps
CPU time 0.83 seconds
Started Jul 30 06:43:34 PM PDT 24
Finished Jul 30 06:43:35 PM PDT 24
Peak memory 196772 kb
Host smart-75dc42ed-5703-4780-a4a5-23ed610f63fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865273168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1865273168
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.2188254939
Short name T141
Test name
Test status
Simulation time 523198768 ps
CPU time 1.41 seconds
Started Jul 30 06:44:11 PM PDT 24
Finished Jul 30 06:44:12 PM PDT 24
Peak memory 196684 kb
Host smart-9a7ce832-b417-4ff6-bfea-69d35fc943d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188254939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.2188254939
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.215774454
Short name T167
Test name
Test status
Simulation time 120080943331 ps
CPU time 41.1 seconds
Started Jul 30 06:43:48 PM PDT 24
Finished Jul 30 06:44:30 PM PDT 24
Peak memory 192352 kb
Host smart-4ea2771e-3388-4e83-84f7-9cbb6cfad58e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215774454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_a
ll.215774454
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_jump.75271853
Short name T127
Test name
Test status
Simulation time 404983522 ps
CPU time 1.17 seconds
Started Jul 30 06:43:59 PM PDT 24
Finished Jul 30 06:44:01 PM PDT 24
Peak memory 196720 kb
Host smart-bf81aa12-7419-4f90-ab08-910fe310bf95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75271853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.75271853
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.2320794520
Short name T133
Test name
Test status
Simulation time 360819118 ps
CPU time 1.06 seconds
Started Jul 30 06:44:05 PM PDT 24
Finished Jul 30 06:44:06 PM PDT 24
Peak memory 196676 kb
Host smart-706afb98-bbbb-4e85-ac9d-96df62c93c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320794520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2320794520
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.925317599
Short name T173
Test name
Test status
Simulation time 497931345 ps
CPU time 0.81 seconds
Started Jul 30 06:44:26 PM PDT 24
Finished Jul 30 06:44:28 PM PDT 24
Peak memory 196732 kb
Host smart-8ea02d5c-330f-44d4-b4b1-f2e38a73fc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925317599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.925317599
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.3814891599
Short name T11
Test name
Test status
Simulation time 76541842688 ps
CPU time 110.14 seconds
Started Jul 30 06:43:54 PM PDT 24
Finished Jul 30 06:45:45 PM PDT 24
Peak memory 192060 kb
Host smart-723b9773-aeae-40b7-b656-8d848da124ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814891599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.3814891599
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.96428239
Short name T177
Test name
Test status
Simulation time 108229205614 ps
CPU time 112.79 seconds
Started Jul 30 06:43:26 PM PDT 24
Finished Jul 30 06:45:19 PM PDT 24
Peak memory 207260 kb
Host smart-0c0a0a2d-d383-4650-8ffe-98943af6d001
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96428239 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.96428239
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.2365212773
Short name T175
Test name
Test status
Simulation time 61073690885 ps
CPU time 181.12 seconds
Started Jul 30 06:43:33 PM PDT 24
Finished Jul 30 06:46:34 PM PDT 24
Peak memory 206684 kb
Host smart-4878d31e-251f-4828-9bc2-06aef0b8880a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365212773 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2365212773
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1425347916
Short name T190
Test name
Test status
Simulation time 8817281934 ps
CPU time 14.48 seconds
Started Jul 30 06:22:41 PM PDT 24
Finished Jul 30 06:22:55 PM PDT 24
Peak memory 198220 kb
Host smart-bb008724-a4d3-48a8-844a-133a57b74203
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425347916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1425347916
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.1037159551
Short name T180
Test name
Test status
Simulation time 30094982187 ps
CPU time 43.14 seconds
Started Jul 30 06:43:25 PM PDT 24
Finished Jul 30 06:44:09 PM PDT 24
Peak memory 191852 kb
Host smart-027a97d1-96b5-4681-9e42-dd67a2c113c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037159551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.1037159551
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_jump.3250688717
Short name T186
Test name
Test status
Simulation time 421489023 ps
CPU time 1.16 seconds
Started Jul 30 06:43:25 PM PDT 24
Finished Jul 30 06:43:27 PM PDT 24
Peak memory 196632 kb
Host smart-b85d070e-1adc-465b-b164-0c04aead7ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250688717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3250688717
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.592544662
Short name T125
Test name
Test status
Simulation time 483968032 ps
CPU time 1.39 seconds
Started Jul 30 06:43:47 PM PDT 24
Finished Jul 30 06:43:49 PM PDT 24
Peak memory 196680 kb
Host smart-615ee449-bf95-4c8e-aa1e-d44916a6cf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592544662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.592544662
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2325738507
Short name T181
Test name
Test status
Simulation time 464117158 ps
CPU time 0.93 seconds
Started Jul 30 06:44:10 PM PDT 24
Finished Jul 30 06:44:11 PM PDT 24
Peak memory 196708 kb
Host smart-99667fa8-0a46-480d-bc57-47692ec58435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325738507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2325738507
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2911756526
Short name T379
Test name
Test status
Simulation time 8591517222 ps
CPU time 14.45 seconds
Started Jul 30 06:22:48 PM PDT 24
Finished Jul 30 06:23:02 PM PDT 24
Peak memory 198192 kb
Host smart-f8a2c185-5d3b-421b-88a5-fec4c146925b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911756526 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2911756526
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2456209925
Short name T168
Test name
Test status
Simulation time 589021851 ps
CPU time 0.82 seconds
Started Jul 30 06:43:38 PM PDT 24
Finished Jul 30 06:43:39 PM PDT 24
Peak memory 196604 kb
Host smart-b1dd1692-c458-4e8c-8ada-39895e528a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456209925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2456209925
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.935389737
Short name T96
Test name
Test status
Simulation time 438344721 ps
CPU time 0.73 seconds
Started Jul 30 06:43:45 PM PDT 24
Finished Jul 30 06:43:45 PM PDT 24
Peak memory 196672 kb
Host smart-2099c3a2-3f0d-4c94-bb41-f4bceedbb872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935389737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.935389737
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.3035277885
Short name T45
Test name
Test status
Simulation time 440830112 ps
CPU time 1.36 seconds
Started Jul 30 06:43:32 PM PDT 24
Finished Jul 30 06:43:33 PM PDT 24
Peak memory 196700 kb
Host smart-dd2e7a83-8cea-4948-8fad-264f579d4c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035277885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3035277885
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_jump.2038370592
Short name T23
Test name
Test status
Simulation time 469769603 ps
CPU time 1.22 seconds
Started Jul 30 06:43:56 PM PDT 24
Finished Jul 30 06:43:57 PM PDT 24
Peak memory 196636 kb
Host smart-4cd842fe-a85d-4d6e-b30c-2e6d43f36a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038370592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.2038370592
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.2081626442
Short name T185
Test name
Test status
Simulation time 522719511 ps
CPU time 1.25 seconds
Started Jul 30 06:43:57 PM PDT 24
Finished Jul 30 06:43:58 PM PDT 24
Peak memory 196732 kb
Host smart-07c23afb-87a4-40ba-bcf0-9abd3d8d0735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081626442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2081626442
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.3687340132
Short name T179
Test name
Test status
Simulation time 117760259934 ps
CPU time 142.75 seconds
Started Jul 30 06:43:49 PM PDT 24
Finished Jul 30 06:46:11 PM PDT 24
Peak memory 191860 kb
Host smart-af1cf283-8878-43f9-8f95-fa3b0719fa83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687340132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.3687340132
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_jump.2712880440
Short name T169
Test name
Test status
Simulation time 540894702 ps
CPU time 0.67 seconds
Started Jul 30 06:44:21 PM PDT 24
Finished Jul 30 06:44:24 PM PDT 24
Peak memory 196640 kb
Host smart-74877aa8-71fd-4e02-aed9-f9e911eea914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712880440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2712880440
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.1395223150
Short name T183
Test name
Test status
Simulation time 566118293 ps
CPU time 0.68 seconds
Started Jul 30 06:44:20 PM PDT 24
Finished Jul 30 06:44:22 PM PDT 24
Peak memory 196620 kb
Host smart-bfe584cf-5ce9-4205-9695-908bb027fba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395223150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1395223150
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2482038502
Short name T70
Test name
Test status
Simulation time 307491106 ps
CPU time 1.09 seconds
Started Jul 30 06:22:23 PM PDT 24
Finished Jul 30 06:22:25 PM PDT 24
Peak memory 183956 kb
Host smart-79205159-0a49-4537-b9a6-89393949ff6e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482038502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.2482038502
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.584736871
Short name T288
Test name
Test status
Simulation time 7112654978 ps
CPU time 9.67 seconds
Started Jul 30 06:22:23 PM PDT 24
Finished Jul 30 06:22:33 PM PDT 24
Peak memory 192280 kb
Host smart-fa7c5fa0-a5da-4eed-879f-a68c22ba0efd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584736871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bi
t_bash.584736871
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.4259560669
Short name T356
Test name
Test status
Simulation time 691373912 ps
CPU time 1.04 seconds
Started Jul 30 06:22:28 PM PDT 24
Finished Jul 30 06:22:29 PM PDT 24
Peak memory 192168 kb
Host smart-082fdf37-8438-4d33-a288-f4ca1bec1b98
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259560669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.4259560669
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2724080412
Short name T301
Test name
Test status
Simulation time 444756904 ps
CPU time 0.94 seconds
Started Jul 30 06:22:30 PM PDT 24
Finished Jul 30 06:22:31 PM PDT 24
Peak memory 195656 kb
Host smart-23493226-7978-47a0-a240-dc5974e10bc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724080412 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2724080412
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.4096159674
Short name T76
Test name
Test status
Simulation time 302280482 ps
CPU time 0.68 seconds
Started Jul 30 06:22:24 PM PDT 24
Finished Jul 30 06:22:25 PM PDT 24
Peak memory 192904 kb
Host smart-13c5f1a3-0d84-4057-a80c-7e76f8c6defd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096159674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.4096159674
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.415826708
Short name T401
Test name
Test status
Simulation time 371355603 ps
CPU time 0.83 seconds
Started Jul 30 06:22:23 PM PDT 24
Finished Jul 30 06:22:24 PM PDT 24
Peak memory 183836 kb
Host smart-c4c764a6-cbc6-49ef-8f83-b208941796b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415826708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.415826708
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3781169747
Short name T296
Test name
Test status
Simulation time 279742714 ps
CPU time 0.8 seconds
Started Jul 30 06:22:23 PM PDT 24
Finished Jul 30 06:22:24 PM PDT 24
Peak memory 183684 kb
Host smart-7eb720c4-45fd-48a8-93d5-db0927ecd922
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781169747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.3781169747
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3620069065
Short name T373
Test name
Test status
Simulation time 272275985 ps
CPU time 0.93 seconds
Started Jul 30 06:22:29 PM PDT 24
Finished Jul 30 06:22:30 PM PDT 24
Peak memory 183688 kb
Host smart-0399926d-0f72-4e70-acf1-cd12e241f56a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620069065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.3620069065
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2551071010
Short name T348
Test name
Test status
Simulation time 2691580948 ps
CPU time 2.22 seconds
Started Jul 30 06:22:27 PM PDT 24
Finished Jul 30 06:22:29 PM PDT 24
Peak memory 194188 kb
Host smart-e580a5a6-5de7-4d21-9857-8161666558fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551071010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.2551071010
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.4213129718
Short name T328
Test name
Test status
Simulation time 533314754 ps
CPU time 1.32 seconds
Started Jul 30 06:22:23 PM PDT 24
Finished Jul 30 06:22:25 PM PDT 24
Peak memory 198612 kb
Host smart-ae84a707-768f-4ed8-b8c9-9073433ef446
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213129718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.4213129718
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2072948274
Short name T397
Test name
Test status
Simulation time 4676630072 ps
CPU time 5.55 seconds
Started Jul 30 06:22:29 PM PDT 24
Finished Jul 30 06:22:35 PM PDT 24
Peak memory 198128 kb
Host smart-7651fa6d-e9f4-4ee4-aa59-de9ad28d5dca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072948274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2072948274
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.329679298
Short name T394
Test name
Test status
Simulation time 749195282 ps
CPU time 1.81 seconds
Started Jul 30 06:22:29 PM PDT 24
Finished Jul 30 06:22:31 PM PDT 24
Peak memory 194288 kb
Host smart-b3252850-07f5-4fde-a7e8-07300c8979ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329679298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al
iasing.329679298
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.4165529996
Short name T67
Test name
Test status
Simulation time 1018052682 ps
CPU time 1.63 seconds
Started Jul 30 06:22:27 PM PDT 24
Finished Jul 30 06:22:29 PM PDT 24
Peak memory 192224 kb
Host smart-fd32709c-b5d5-4edf-bbed-f54570eb6fc9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165529996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.4165529996
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2827501840
Short name T69
Test name
Test status
Simulation time 910232401 ps
CPU time 1.8 seconds
Started Jul 30 06:22:26 PM PDT 24
Finished Jul 30 06:22:28 PM PDT 24
Peak memory 193316 kb
Host smart-b20b4284-ec21-480c-94e0-deaf18c11e93
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827501840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2827501840
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.945875128
Short name T349
Test name
Test status
Simulation time 414187110 ps
CPU time 0.9 seconds
Started Jul 30 06:22:26 PM PDT 24
Finished Jul 30 06:22:27 PM PDT 24
Peak memory 197252 kb
Host smart-3de09426-6ae7-4a33-8ea9-f75055544807
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945875128 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.945875128
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1903322629
Short name T33
Test name
Test status
Simulation time 446851423 ps
CPU time 0.67 seconds
Started Jul 30 06:22:33 PM PDT 24
Finished Jul 30 06:22:34 PM PDT 24
Peak memory 193240 kb
Host smart-27f51eb5-f872-43c3-a692-08c79b6285f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903322629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1903322629
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3299911063
Short name T352
Test name
Test status
Simulation time 512895282 ps
CPU time 0.71 seconds
Started Jul 30 06:22:27 PM PDT 24
Finished Jul 30 06:22:28 PM PDT 24
Peak memory 183772 kb
Host smart-c54c5d52-0e86-469f-918a-6487851d0a47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299911063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.3299911063
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2019021482
Short name T297
Test name
Test status
Simulation time 465061753 ps
CPU time 0.59 seconds
Started Jul 30 06:22:25 PM PDT 24
Finished Jul 30 06:22:25 PM PDT 24
Peak memory 183764 kb
Host smart-310fc810-a2fa-432d-8899-56d2de076c2c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019021482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.2019021482
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1739488379
Short name T333
Test name
Test status
Simulation time 308061520 ps
CPU time 0.74 seconds
Started Jul 30 06:22:28 PM PDT 24
Finished Jul 30 06:22:28 PM PDT 24
Peak memory 183736 kb
Host smart-7137bcb4-e62a-45b0-b20a-b89592c5a36e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739488379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.1739488379
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.947290199
Short name T369
Test name
Test status
Simulation time 1369021600 ps
CPU time 2.51 seconds
Started Jul 30 06:22:33 PM PDT 24
Finished Jul 30 06:22:36 PM PDT 24
Peak memory 193012 kb
Host smart-35fb29e8-6c9f-46eb-95c8-5169335926dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947290199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_
timer_same_csr_outstanding.947290199
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1745790514
Short name T276
Test name
Test status
Simulation time 772432726 ps
CPU time 1.52 seconds
Started Jul 30 06:22:26 PM PDT 24
Finished Jul 30 06:22:27 PM PDT 24
Peak memory 198792 kb
Host smart-9ccafacb-82da-4ac6-973c-e63ee7b5ef77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745790514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1745790514
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1682528871
Short name T327
Test name
Test status
Simulation time 8404338064 ps
CPU time 6.47 seconds
Started Jul 30 06:22:28 PM PDT 24
Finished Jul 30 06:22:35 PM PDT 24
Peak memory 198324 kb
Host smart-ebf93578-7055-4051-bf49-6b3a3226d8c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682528871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.1682528871
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3779142897
Short name T307
Test name
Test status
Simulation time 520336348 ps
CPU time 0.8 seconds
Started Jul 30 06:22:38 PM PDT 24
Finished Jul 30 06:22:39 PM PDT 24
Peak memory 196528 kb
Host smart-3c709893-c0cf-446a-a93b-9e606d856428
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779142897 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3779142897
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1331588817
Short name T391
Test name
Test status
Simulation time 527411412 ps
CPU time 0.79 seconds
Started Jul 30 06:22:41 PM PDT 24
Finished Jul 30 06:22:41 PM PDT 24
Peak memory 193464 kb
Host smart-ba57c5ee-2b31-41d6-b996-9a9bac528777
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331588817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1331588817
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.4275040220
Short name T338
Test name
Test status
Simulation time 306723295 ps
CPU time 0.65 seconds
Started Jul 30 06:22:40 PM PDT 24
Finished Jul 30 06:22:41 PM PDT 24
Peak memory 183844 kb
Host smart-5a84802d-e1e7-4623-8378-fc2f2d1227e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275040220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.4275040220
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2405890509
Short name T402
Test name
Test status
Simulation time 1203878472 ps
CPU time 1.98 seconds
Started Jul 30 06:22:41 PM PDT 24
Finished Jul 30 06:22:43 PM PDT 24
Peak memory 193296 kb
Host smart-39be6ce7-5e1d-444a-8241-82b3410383c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405890509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.2405890509
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.104138440
Short name T413
Test name
Test status
Simulation time 316845058 ps
CPU time 1.67 seconds
Started Jul 30 06:22:39 PM PDT 24
Finished Jul 30 06:22:41 PM PDT 24
Peak memory 198608 kb
Host smart-bd27c7a0-dc12-49ed-bd97-32fcbb312de4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104138440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.104138440
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3494765840
Short name T342
Test name
Test status
Simulation time 7457434326 ps
CPU time 12.04 seconds
Started Jul 30 06:22:46 PM PDT 24
Finished Jul 30 06:22:58 PM PDT 24
Peak memory 198360 kb
Host smart-923d75ac-372e-4694-bab4-a53faedbe2e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494765840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3494765840
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.488422852
Short name T360
Test name
Test status
Simulation time 559121561 ps
CPU time 0.96 seconds
Started Jul 30 06:22:41 PM PDT 24
Finished Jul 30 06:22:42 PM PDT 24
Peak memory 196116 kb
Host smart-d7789a12-6bee-4a99-9348-ecff979642fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488422852 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.488422852
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.52339156
Short name T417
Test name
Test status
Simulation time 510936687 ps
CPU time 1.25 seconds
Started Jul 30 06:22:42 PM PDT 24
Finished Jul 30 06:22:43 PM PDT 24
Peak memory 192976 kb
Host smart-ac539d49-d9ba-4549-8344-89d6580b0543
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52339156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.52339156
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3069316183
Short name T368
Test name
Test status
Simulation time 399483052 ps
CPU time 1.08 seconds
Started Jul 30 06:22:44 PM PDT 24
Finished Jul 30 06:22:46 PM PDT 24
Peak memory 183760 kb
Host smart-e3443934-7d64-48d5-9ecb-d36097902608
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069316183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.3069316183
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2786261773
Short name T79
Test name
Test status
Simulation time 2294881962 ps
CPU time 1.69 seconds
Started Jul 30 06:22:42 PM PDT 24
Finished Jul 30 06:22:43 PM PDT 24
Peak memory 192172 kb
Host smart-f181cfd2-4b80-4196-b744-b4c40939ece7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786261773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.2786261773
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2145710782
Short name T330
Test name
Test status
Simulation time 587508612 ps
CPU time 1.43 seconds
Started Jul 30 06:22:39 PM PDT 24
Finished Jul 30 06:22:41 PM PDT 24
Peak memory 198592 kb
Host smart-2305a8d2-9423-4e8b-8067-937feef071f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145710782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2145710782
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.432885390
Short name T36
Test name
Test status
Simulation time 4661831688 ps
CPU time 2.56 seconds
Started Jul 30 06:22:40 PM PDT 24
Finished Jul 30 06:22:42 PM PDT 24
Peak memory 197856 kb
Host smart-eca5fc30-277d-4e47-ab4b-334133a5597d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432885390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl
_intg_err.432885390
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.56368912
Short name T350
Test name
Test status
Simulation time 525780309 ps
CPU time 1.36 seconds
Started Jul 30 06:22:43 PM PDT 24
Finished Jul 30 06:22:45 PM PDT 24
Peak memory 198612 kb
Host smart-c7ba0bed-ac0d-4d05-9ea0-c34f04ee4b50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56368912 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.56368912
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1584441940
Short name T63
Test name
Test status
Simulation time 300929455 ps
CPU time 1.03 seconds
Started Jul 30 06:22:42 PM PDT 24
Finished Jul 30 06:22:44 PM PDT 24
Peak memory 193076 kb
Host smart-5d84eb0c-98e4-457e-8e5b-e918cba9822e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584441940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1584441940
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.267845338
Short name T278
Test name
Test status
Simulation time 354969090 ps
CPU time 0.65 seconds
Started Jul 30 06:22:39 PM PDT 24
Finished Jul 30 06:22:40 PM PDT 24
Peak memory 183700 kb
Host smart-2de61ada-e47f-4782-8526-5e7b0397caeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267845338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.267845338
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1805042067
Short name T403
Test name
Test status
Simulation time 1472665762 ps
CPU time 2.7 seconds
Started Jul 30 06:22:44 PM PDT 24
Finished Jul 30 06:22:47 PM PDT 24
Peak memory 193288 kb
Host smart-7af1bea9-4e7f-4c39-8f21-3b9dd70e492d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805042067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1805042067
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1647603983
Short name T311
Test name
Test status
Simulation time 584719499 ps
CPU time 1.83 seconds
Started Jul 30 06:22:43 PM PDT 24
Finished Jul 30 06:22:45 PM PDT 24
Peak memory 198596 kb
Host smart-ff575f6c-9118-4ae6-a600-e1b131122633
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647603983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.1647603983
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1630069799
Short name T339
Test name
Test status
Simulation time 487589506 ps
CPU time 0.9 seconds
Started Jul 30 06:22:45 PM PDT 24
Finished Jul 30 06:22:46 PM PDT 24
Peak memory 198352 kb
Host smart-8161c0fa-372d-4144-ae18-d6adae7e793f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630069799 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1630069799
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2248010280
Short name T408
Test name
Test status
Simulation time 535047398 ps
CPU time 1.44 seconds
Started Jul 30 06:22:44 PM PDT 24
Finished Jul 30 06:22:46 PM PDT 24
Peak memory 193988 kb
Host smart-f6523d72-b9b0-4948-9f10-f69db327396a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248010280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2248010280
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.893050711
Short name T313
Test name
Test status
Simulation time 627149156 ps
CPU time 0.61 seconds
Started Jul 30 06:22:42 PM PDT 24
Finished Jul 30 06:22:43 PM PDT 24
Peak memory 193060 kb
Host smart-d521db63-33ec-44f4-b6f9-4324d1279ee3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893050711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.893050711
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2914034791
Short name T409
Test name
Test status
Simulation time 1677746578 ps
CPU time 1.57 seconds
Started Jul 30 06:22:43 PM PDT 24
Finished Jul 30 06:22:44 PM PDT 24
Peak memory 193988 kb
Host smart-e536a12f-b46d-4429-bd2a-b207dfcbab1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914034791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.2914034791
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.784358862
Short name T340
Test name
Test status
Simulation time 568462457 ps
CPU time 1.42 seconds
Started Jul 30 06:22:41 PM PDT 24
Finished Jul 30 06:22:43 PM PDT 24
Peak memory 198564 kb
Host smart-80d0db82-8cb1-409e-bc1b-c3589bd37550
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784358862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.784358862
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2789986983
Short name T325
Test name
Test status
Simulation time 4208260971 ps
CPU time 6.95 seconds
Started Jul 30 06:22:45 PM PDT 24
Finished Jul 30 06:22:52 PM PDT 24
Peak memory 198212 kb
Host smart-38483863-3b70-439a-b273-1a8acdb11fcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789986983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.2789986983
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.680156594
Short name T300
Test name
Test status
Simulation time 437096479 ps
CPU time 1.24 seconds
Started Jul 30 06:22:46 PM PDT 24
Finished Jul 30 06:22:47 PM PDT 24
Peak memory 196480 kb
Host smart-efc56c10-2562-46c9-ac78-bb082d0358f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680156594 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.680156594
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2495458232
Short name T65
Test name
Test status
Simulation time 371547299 ps
CPU time 0.68 seconds
Started Jul 30 06:22:46 PM PDT 24
Finished Jul 30 06:22:47 PM PDT 24
Peak memory 193404 kb
Host smart-4fb82a99-5828-4f80-a305-7348f902c590
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495458232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2495458232
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.49936983
Short name T295
Test name
Test status
Simulation time 371929286 ps
CPU time 0.8 seconds
Started Jul 30 06:22:47 PM PDT 24
Finished Jul 30 06:22:48 PM PDT 24
Peak memory 183784 kb
Host smart-26d988f4-f06d-49ad-b79b-9a47e0b676c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49936983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.49936983
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2161740699
Short name T72
Test name
Test status
Simulation time 1529050821 ps
CPU time 1.72 seconds
Started Jul 30 06:22:47 PM PDT 24
Finished Jul 30 06:22:49 PM PDT 24
Peak memory 193020 kb
Host smart-f17f641a-41cb-464d-bee7-f3abfdafd193
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161740699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2161740699
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2119631169
Short name T282
Test name
Test status
Simulation time 476465487 ps
CPU time 1.63 seconds
Started Jul 30 06:22:42 PM PDT 24
Finished Jul 30 06:22:44 PM PDT 24
Peak memory 198048 kb
Host smart-d9645235-2052-4c8f-87c8-e7f47007150a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119631169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2119631169
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.926814479
Short name T355
Test name
Test status
Simulation time 479172347 ps
CPU time 0.97 seconds
Started Jul 30 06:22:45 PM PDT 24
Finished Jul 30 06:22:46 PM PDT 24
Peak memory 196612 kb
Host smart-84ad4ddc-1abf-4424-88d5-d2575f9ab9e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926814479 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.926814479
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.85643652
Short name T380
Test name
Test status
Simulation time 496345048 ps
CPU time 0.72 seconds
Started Jul 30 06:22:47 PM PDT 24
Finished Jul 30 06:22:48 PM PDT 24
Peak memory 193076 kb
Host smart-187f7e51-cdd6-40be-b71a-33ce43db06d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85643652 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.85643652
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3763057427
Short name T363
Test name
Test status
Simulation time 390939530 ps
CPU time 0.77 seconds
Started Jul 30 06:22:46 PM PDT 24
Finished Jul 30 06:22:47 PM PDT 24
Peak memory 183804 kb
Host smart-f017b1a3-4578-4815-afbd-a4890dcbd52b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763057427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3763057427
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3917368081
Short name T74
Test name
Test status
Simulation time 2461902085 ps
CPU time 3.82 seconds
Started Jul 30 06:22:49 PM PDT 24
Finished Jul 30 06:22:53 PM PDT 24
Peak memory 184084 kb
Host smart-1883d7a5-fdc5-46ed-a947-0198b4b2a2e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917368081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.3917368081
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2387094817
Short name T404
Test name
Test status
Simulation time 1281523496 ps
CPU time 1.65 seconds
Started Jul 30 06:22:48 PM PDT 24
Finished Jul 30 06:22:50 PM PDT 24
Peak memory 198688 kb
Host smart-935a826c-1f60-4393-915b-37f24cb55de2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387094817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2387094817
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3083026906
Short name T310
Test name
Test status
Simulation time 454016457 ps
CPU time 1.41 seconds
Started Jul 30 06:22:47 PM PDT 24
Finished Jul 30 06:22:48 PM PDT 24
Peak memory 196212 kb
Host smart-4bab3d83-d2b3-414d-b58b-74ce7b2ed78e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083026906 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.3083026906
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1117189039
Short name T359
Test name
Test status
Simulation time 513191287 ps
CPU time 0.74 seconds
Started Jul 30 06:22:49 PM PDT 24
Finished Jul 30 06:22:50 PM PDT 24
Peak memory 193012 kb
Host smart-ea258930-0337-46ad-a11b-fca31c454064
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117189039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1117189039
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.4145261435
Short name T287
Test name
Test status
Simulation time 431083677 ps
CPU time 0.87 seconds
Started Jul 30 06:22:46 PM PDT 24
Finished Jul 30 06:22:47 PM PDT 24
Peak memory 183780 kb
Host smart-54ea2b14-46e8-4d1f-9ca8-c26ecfc781a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145261435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.4145261435
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.994364330
Short name T388
Test name
Test status
Simulation time 2371267910 ps
CPU time 4.1 seconds
Started Jul 30 06:22:48 PM PDT 24
Finished Jul 30 06:22:52 PM PDT 24
Peak memory 193980 kb
Host smart-c49ebd3a-41ff-4187-a757-513154de57d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994364330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon
_timer_same_csr_outstanding.994364330
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3412185617
Short name T410
Test name
Test status
Simulation time 464140282 ps
CPU time 2.02 seconds
Started Jul 30 06:22:46 PM PDT 24
Finished Jul 30 06:22:48 PM PDT 24
Peak memory 198644 kb
Host smart-8d7cbe8c-8c7f-4e9c-8169-18bfe9881467
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412185617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.3412185617
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2621243235
Short name T416
Test name
Test status
Simulation time 8205293012 ps
CPU time 11.17 seconds
Started Jul 30 06:22:47 PM PDT 24
Finished Jul 30 06:22:59 PM PDT 24
Peak memory 198468 kb
Host smart-000165b7-d90b-4229-aa58-0304c26e000d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621243235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.2621243235
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.54654484
Short name T312
Test name
Test status
Simulation time 440556908 ps
CPU time 1.35 seconds
Started Jul 30 06:22:50 PM PDT 24
Finished Jul 30 06:22:52 PM PDT 24
Peak memory 196272 kb
Host smart-626a3465-499c-4ae3-bf2e-7e17c8219671
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54654484 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.54654484
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3530103648
Short name T195
Test name
Test status
Simulation time 388373598 ps
CPU time 0.75 seconds
Started Jul 30 06:22:48 PM PDT 24
Finished Jul 30 06:22:49 PM PDT 24
Peak memory 192956 kb
Host smart-893760af-9624-4e0a-93bc-afc76f1042dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530103648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3530103648
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1705098235
Short name T400
Test name
Test status
Simulation time 295406170 ps
CPU time 0.64 seconds
Started Jul 30 06:22:48 PM PDT 24
Finished Jul 30 06:22:49 PM PDT 24
Peak memory 183768 kb
Host smart-4a6a24d2-7d70-4682-87fa-103f03d33941
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705098235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.1705098235
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2824231628
Short name T366
Test name
Test status
Simulation time 1168750607 ps
CPU time 0.8 seconds
Started Jul 30 06:22:51 PM PDT 24
Finished Jul 30 06:22:52 PM PDT 24
Peak memory 194008 kb
Host smart-c6406c00-fb3c-4977-b18f-ccec6aa49e67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824231628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.2824231628
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.30545200
Short name T393
Test name
Test status
Simulation time 740134133 ps
CPU time 2.18 seconds
Started Jul 30 06:22:49 PM PDT 24
Finished Jul 30 06:22:51 PM PDT 24
Peak memory 198664 kb
Host smart-d6d87ab1-8bbf-46a5-b71e-431ea4d8e7d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30545200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.30545200
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2459927183
Short name T381
Test name
Test status
Simulation time 8308116206 ps
CPU time 5.07 seconds
Started Jul 30 06:22:46 PM PDT 24
Finished Jul 30 06:22:51 PM PDT 24
Peak memory 198376 kb
Host smart-03bca6cd-3c42-40af-ba62-4c661c4c1f08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459927183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.2459927183
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1358018349
Short name T34
Test name
Test status
Simulation time 519407653 ps
CPU time 1.52 seconds
Started Jul 30 06:22:50 PM PDT 24
Finished Jul 30 06:22:51 PM PDT 24
Peak memory 196172 kb
Host smart-292ba6b0-f480-4ce4-a28f-e6ada0c9119b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358018349 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1358018349
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3472759300
Short name T68
Test name
Test status
Simulation time 475209088 ps
CPU time 1.3 seconds
Started Jul 30 06:22:50 PM PDT 24
Finished Jul 30 06:22:52 PM PDT 24
Peak memory 192072 kb
Host smart-28bb258a-fb47-4f26-843b-ec80207ef271
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472759300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3472759300
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1224245896
Short name T323
Test name
Test status
Simulation time 404712578 ps
CPU time 1.16 seconds
Started Jul 30 06:22:52 PM PDT 24
Finished Jul 30 06:22:54 PM PDT 24
Peak memory 192980 kb
Host smart-fca05028-408d-4717-b641-ba5a99e32c13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224245896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.1224245896
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3677085815
Short name T78
Test name
Test status
Simulation time 2313927286 ps
CPU time 1.5 seconds
Started Jul 30 06:22:49 PM PDT 24
Finished Jul 30 06:22:51 PM PDT 24
Peak memory 192104 kb
Host smart-036d129d-cc2c-4e9b-babc-1a58acf74da4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677085815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.3677085815
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3934861393
Short name T343
Test name
Test status
Simulation time 511183577 ps
CPU time 1.67 seconds
Started Jul 30 06:22:50 PM PDT 24
Finished Jul 30 06:22:52 PM PDT 24
Peak memory 198672 kb
Host smart-4ef8f28c-bf10-41c1-a0de-cdcf8a661faa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934861393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3934861393
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.805168225
Short name T324
Test name
Test status
Simulation time 4194655681 ps
CPU time 2.21 seconds
Started Jul 30 06:22:49 PM PDT 24
Finished Jul 30 06:22:51 PM PDT 24
Peak memory 197904 kb
Host smart-1f6ce651-c74f-4038-b03b-2715f9aa8e2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805168225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.805168225
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3288670953
Short name T285
Test name
Test status
Simulation time 354948999 ps
CPU time 1.11 seconds
Started Jul 30 06:22:55 PM PDT 24
Finished Jul 30 06:22:56 PM PDT 24
Peak memory 197188 kb
Host smart-00c0cf75-56b0-4ab4-94e0-37beec22932b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288670953 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3288670953
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.278606630
Short name T387
Test name
Test status
Simulation time 474331840 ps
CPU time 0.74 seconds
Started Jul 30 06:22:59 PM PDT 24
Finished Jul 30 06:23:00 PM PDT 24
Peak memory 192988 kb
Host smart-52c139b6-1e73-4127-88c8-1535037823b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278606630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.278606630
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1250933934
Short name T358
Test name
Test status
Simulation time 448545460 ps
CPU time 0.7 seconds
Started Jul 30 06:23:01 PM PDT 24
Finished Jul 30 06:23:02 PM PDT 24
Peak memory 183756 kb
Host smart-78e09a9e-486b-4d43-922a-8c250c4957e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250933934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.1250933934
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3744930060
Short name T372
Test name
Test status
Simulation time 1338361018 ps
CPU time 1.21 seconds
Started Jul 30 06:22:52 PM PDT 24
Finished Jul 30 06:22:54 PM PDT 24
Peak memory 184056 kb
Host smart-6f11cfae-cec2-418f-8254-4f39bfe18e3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744930060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.3744930060
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1371333102
Short name T398
Test name
Test status
Simulation time 743251259 ps
CPU time 1.95 seconds
Started Jul 30 06:22:49 PM PDT 24
Finished Jul 30 06:22:51 PM PDT 24
Peak memory 198604 kb
Host smart-71ec6028-667a-42b1-94c9-621d2e36b09a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371333102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.1371333102
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2201793813
Short name T191
Test name
Test status
Simulation time 3911343657 ps
CPU time 3.34 seconds
Started Jul 30 06:22:51 PM PDT 24
Finished Jul 30 06:22:54 PM PDT 24
Peak memory 198396 kb
Host smart-b56e3e63-d988-449b-be2f-92a63e9a9396
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201793813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.2201793813
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.4151682201
Short name T61
Test name
Test status
Simulation time 537133889 ps
CPU time 0.86 seconds
Started Jul 30 06:22:33 PM PDT 24
Finished Jul 30 06:22:34 PM PDT 24
Peak memory 193276 kb
Host smart-0a7e6096-b6d7-40db-997d-4c40d9b8ee8f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151682201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.4151682201
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1895031028
Short name T71
Test name
Test status
Simulation time 6678976503 ps
CPU time 4.47 seconds
Started Jul 30 06:22:30 PM PDT 24
Finished Jul 30 06:22:34 PM PDT 24
Peak memory 192308 kb
Host smart-ab16755a-c1e7-4be9-9e62-f14abf635174
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895031028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1895031028
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1834350932
Short name T345
Test name
Test status
Simulation time 650390905 ps
CPU time 0.8 seconds
Started Jul 30 06:22:30 PM PDT 24
Finished Jul 30 06:22:31 PM PDT 24
Peak memory 193060 kb
Host smart-6650da61-afff-4fa5-af3d-f9e2713f91a8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834350932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.1834350932
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.473513659
Short name T405
Test name
Test status
Simulation time 447415300 ps
CPU time 1.29 seconds
Started Jul 30 06:22:31 PM PDT 24
Finished Jul 30 06:22:33 PM PDT 24
Peak memory 195748 kb
Host smart-e7b0bf45-61e4-4040-bb21-0017772c08d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473513659 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.473513659
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2122918493
Short name T66
Test name
Test status
Simulation time 525238856 ps
CPU time 0.76 seconds
Started Jul 30 06:22:31 PM PDT 24
Finished Jul 30 06:22:32 PM PDT 24
Peak memory 193308 kb
Host smart-2e6c60f5-e753-478d-b889-1ed8429c5670
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122918493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2122918493
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1841432345
Short name T414
Test name
Test status
Simulation time 400872221 ps
CPU time 0.66 seconds
Started Jul 30 06:22:28 PM PDT 24
Finished Jul 30 06:22:29 PM PDT 24
Peak memory 183756 kb
Host smart-de2ff86a-517d-4dc4-9d3b-d911e43ffc93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841432345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1841432345
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2180454065
Short name T354
Test name
Test status
Simulation time 487820116 ps
CPU time 1.23 seconds
Started Jul 30 06:22:31 PM PDT 24
Finished Jul 30 06:22:32 PM PDT 24
Peak memory 183724 kb
Host smart-7e81f711-919e-41fb-a46f-5b52135b644c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180454065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.2180454065
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.4225942827
Short name T411
Test name
Test status
Simulation time 341458177 ps
CPU time 0.55 seconds
Started Jul 30 06:22:30 PM PDT 24
Finished Jul 30 06:22:31 PM PDT 24
Peak memory 183668 kb
Host smart-f9ada592-eb86-483a-bc30-cdaf8f5eb6d8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225942827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.4225942827
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2172693705
Short name T383
Test name
Test status
Simulation time 2857425135 ps
CPU time 1.04 seconds
Started Jul 30 06:22:30 PM PDT 24
Finished Jul 30 06:22:32 PM PDT 24
Peak memory 194192 kb
Host smart-2bdf5ba2-746f-4d98-901c-6d835e797125
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172693705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2172693705
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2442330250
Short name T357
Test name
Test status
Simulation time 356225802 ps
CPU time 2.14 seconds
Started Jul 30 06:22:26 PM PDT 24
Finished Jul 30 06:22:28 PM PDT 24
Peak memory 198644 kb
Host smart-2075fbae-7e66-4976-a9f3-fdfa7b185a45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442330250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2442330250
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3127346642
Short name T347
Test name
Test status
Simulation time 8375423948 ps
CPU time 12.66 seconds
Started Jul 30 06:22:34 PM PDT 24
Finished Jul 30 06:22:47 PM PDT 24
Peak memory 198404 kb
Host smart-d133d9a4-6b2a-478d-988f-9afe37e783cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127346642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3127346642
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2350138473
Short name T290
Test name
Test status
Simulation time 394449963 ps
CPU time 1.06 seconds
Started Jul 30 06:22:53 PM PDT 24
Finished Jul 30 06:22:54 PM PDT 24
Peak memory 192972 kb
Host smart-95cd7908-5ef1-42a7-be4d-e3fe2e658d22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350138473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2350138473
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2609781717
Short name T319
Test name
Test status
Simulation time 380053973 ps
CPU time 1.07 seconds
Started Jul 30 06:22:53 PM PDT 24
Finished Jul 30 06:22:54 PM PDT 24
Peak memory 192928 kb
Host smart-2453337c-570f-49af-af66-a24b2ccc5506
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609781717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2609781717
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1649266985
Short name T286
Test name
Test status
Simulation time 347269063 ps
CPU time 0.72 seconds
Started Jul 30 06:22:56 PM PDT 24
Finished Jul 30 06:22:57 PM PDT 24
Peak memory 193008 kb
Host smart-8614f206-380b-40f2-8474-9d4494bebf73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649266985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1649266985
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2766302982
Short name T317
Test name
Test status
Simulation time 492342376 ps
CPU time 1.29 seconds
Started Jul 30 06:22:53 PM PDT 24
Finished Jul 30 06:22:55 PM PDT 24
Peak memory 183792 kb
Host smart-e97bbac0-5b26-4283-83cd-a1164658b0f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766302982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2766302982
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.4257663204
Short name T375
Test name
Test status
Simulation time 492586011 ps
CPU time 0.71 seconds
Started Jul 30 06:22:59 PM PDT 24
Finished Jul 30 06:22:59 PM PDT 24
Peak memory 192996 kb
Host smart-3ae24eb8-7e4f-4bc9-9213-711849ed53da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257663204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.4257663204
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1511495302
Short name T329
Test name
Test status
Simulation time 363246332 ps
CPU time 0.65 seconds
Started Jul 30 06:22:57 PM PDT 24
Finished Jul 30 06:22:57 PM PDT 24
Peak memory 183780 kb
Host smart-4696c04a-ff44-4bbc-9b34-34b41ef55334
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511495302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1511495302
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2800672903
Short name T331
Test name
Test status
Simulation time 350687052 ps
CPU time 1.08 seconds
Started Jul 30 06:22:59 PM PDT 24
Finished Jul 30 06:23:00 PM PDT 24
Peak memory 183760 kb
Host smart-e2163fb3-2dce-4170-81f4-d0045f1fff63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800672903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2800672903
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3798911175
Short name T293
Test name
Test status
Simulation time 515099434 ps
CPU time 0.66 seconds
Started Jul 30 06:22:56 PM PDT 24
Finished Jul 30 06:22:57 PM PDT 24
Peak memory 183752 kb
Host smart-26223eb8-033c-4687-9c95-4111398348ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798911175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3798911175
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3164982924
Short name T335
Test name
Test status
Simulation time 507026338 ps
CPU time 1.2 seconds
Started Jul 30 06:22:58 PM PDT 24
Finished Jul 30 06:23:00 PM PDT 24
Peak memory 183784 kb
Host smart-ef4f64dd-ac06-46ef-9bfc-6e014a465804
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164982924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3164982924
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.426677561
Short name T315
Test name
Test status
Simulation time 418864691 ps
CPU time 0.6 seconds
Started Jul 30 06:22:57 PM PDT 24
Finished Jul 30 06:22:58 PM PDT 24
Peak memory 183852 kb
Host smart-08197f78-ddc6-441f-b5d0-07ff304146d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426677561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.426677561
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1732170495
Short name T384
Test name
Test status
Simulation time 517101138 ps
CPU time 1.69 seconds
Started Jul 30 06:22:34 PM PDT 24
Finished Jul 30 06:22:35 PM PDT 24
Peak memory 194684 kb
Host smart-e9beaf3d-6f50-4386-a79a-771275be929b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732170495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1732170495
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1277400857
Short name T60
Test name
Test status
Simulation time 7611464366 ps
CPU time 10.1 seconds
Started Jul 30 06:22:31 PM PDT 24
Finished Jul 30 06:22:41 PM PDT 24
Peak memory 196380 kb
Host smart-5b182db0-14af-40d4-a041-992abb32c313
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277400857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1277400857
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.4165887428
Short name T64
Test name
Test status
Simulation time 1132615405 ps
CPU time 2.06 seconds
Started Jul 30 06:22:34 PM PDT 24
Finished Jul 30 06:22:36 PM PDT 24
Peak memory 193216 kb
Host smart-ff27286a-f95f-4464-beb8-85728eaeba83
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165887428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.4165887428
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2999288789
Short name T303
Test name
Test status
Simulation time 352555774 ps
CPU time 1.14 seconds
Started Jul 30 06:22:32 PM PDT 24
Finished Jul 30 06:22:33 PM PDT 24
Peak memory 196220 kb
Host smart-e4cd65a4-f5fb-43f2-aa23-55056db996d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999288789 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2999288789
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2924200160
Short name T362
Test name
Test status
Simulation time 509383170 ps
CPU time 1.32 seconds
Started Jul 30 06:22:31 PM PDT 24
Finished Jul 30 06:22:33 PM PDT 24
Peak memory 193432 kb
Host smart-296d4adb-4837-4a08-8db9-797cd2260cf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924200160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.2924200160
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3223704781
Short name T308
Test name
Test status
Simulation time 362012116 ps
CPU time 0.81 seconds
Started Jul 30 06:22:31 PM PDT 24
Finished Jul 30 06:22:32 PM PDT 24
Peak memory 193004 kb
Host smart-82075374-9ded-4f24-bf7d-b578ca51ab65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223704781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3223704781
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2194924276
Short name T365
Test name
Test status
Simulation time 466711357 ps
CPU time 1.21 seconds
Started Jul 30 06:22:31 PM PDT 24
Finished Jul 30 06:22:33 PM PDT 24
Peak memory 183644 kb
Host smart-d73b759c-1cd4-420d-82eb-f7513a7f2c66
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194924276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2194924276
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2007130826
Short name T412
Test name
Test status
Simulation time 294132999 ps
CPU time 0.86 seconds
Started Jul 30 06:22:31 PM PDT 24
Finished Jul 30 06:22:32 PM PDT 24
Peak memory 183716 kb
Host smart-57907200-f66e-4e07-8a92-64fcd4bea739
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007130826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2007130826
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.4007248681
Short name T364
Test name
Test status
Simulation time 2268914303 ps
CPU time 3.13 seconds
Started Jul 30 06:22:34 PM PDT 24
Finished Jul 30 06:22:37 PM PDT 24
Peak memory 195024 kb
Host smart-7e723dde-cb79-4c0e-997a-19bf6c4273de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007248681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.4007248681
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1847853165
Short name T291
Test name
Test status
Simulation time 518493968 ps
CPU time 1.73 seconds
Started Jul 30 06:22:31 PM PDT 24
Finished Jul 30 06:22:33 PM PDT 24
Peak memory 198612 kb
Host smart-03f68578-ac2f-47e9-859e-59cdc612a698
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847853165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1847853165
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1769837146
Short name T304
Test name
Test status
Simulation time 4244168567 ps
CPU time 7.26 seconds
Started Jul 30 06:22:35 PM PDT 24
Finished Jul 30 06:22:42 PM PDT 24
Peak memory 198060 kb
Host smart-aeb29c9e-3c4a-41c6-84cc-8e3bd3093087
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769837146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.1769837146
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1527585337
Short name T353
Test name
Test status
Simulation time 307653183 ps
CPU time 0.71 seconds
Started Jul 30 06:22:58 PM PDT 24
Finished Jul 30 06:22:59 PM PDT 24
Peak memory 193000 kb
Host smart-eba35107-682b-4f59-9a42-e2b53e240052
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527585337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1527585337
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1594880744
Short name T374
Test name
Test status
Simulation time 356414915 ps
CPU time 0.69 seconds
Started Jul 30 06:22:58 PM PDT 24
Finished Jul 30 06:22:59 PM PDT 24
Peak memory 183808 kb
Host smart-86482c58-1dc5-4472-9943-191b65122ee9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594880744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1594880744
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2136250292
Short name T283
Test name
Test status
Simulation time 322768092 ps
CPU time 0.77 seconds
Started Jul 30 06:22:57 PM PDT 24
Finished Jul 30 06:22:58 PM PDT 24
Peak memory 192984 kb
Host smart-999f79ed-1cce-45d6-be94-ad9389b31ede
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136250292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.2136250292
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2386553165
Short name T378
Test name
Test status
Simulation time 291826416 ps
CPU time 1 seconds
Started Jul 30 06:23:03 PM PDT 24
Finished Jul 30 06:23:04 PM PDT 24
Peak memory 183836 kb
Host smart-924bc188-f3f2-4b18-96c3-02291628e443
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386553165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2386553165
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.24394880
Short name T371
Test name
Test status
Simulation time 328618048 ps
CPU time 0.69 seconds
Started Jul 30 06:23:03 PM PDT 24
Finished Jul 30 06:23:04 PM PDT 24
Peak memory 193000 kb
Host smart-b2a5332e-85be-40fb-a5cf-95f130b804cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24394880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.24394880
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3187396632
Short name T292
Test name
Test status
Simulation time 344862491 ps
CPU time 1.02 seconds
Started Jul 30 06:23:02 PM PDT 24
Finished Jul 30 06:23:03 PM PDT 24
Peak memory 183828 kb
Host smart-1288a56c-4a2c-4cef-b70e-3d54b89222f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187396632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.3187396632
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.430317632
Short name T309
Test name
Test status
Simulation time 365952305 ps
CPU time 1.02 seconds
Started Jul 30 06:23:03 PM PDT 24
Finished Jul 30 06:23:04 PM PDT 24
Peak memory 192984 kb
Host smart-49f88ab3-31dd-42a6-a757-953d888c36b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430317632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.430317632
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3789829200
Short name T305
Test name
Test status
Simulation time 296474716 ps
CPU time 0.96 seconds
Started Jul 30 06:23:02 PM PDT 24
Finished Jul 30 06:23:03 PM PDT 24
Peak memory 193060 kb
Host smart-e59d0659-522a-4264-b222-217913d21c89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789829200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3789829200
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.925350801
Short name T332
Test name
Test status
Simulation time 279880482 ps
CPU time 0.91 seconds
Started Jul 30 06:23:01 PM PDT 24
Finished Jul 30 06:23:02 PM PDT 24
Peak memory 183828 kb
Host smart-b33dbd44-f318-426a-bfd3-78701cf08aa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925350801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.925350801
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.836566395
Short name T376
Test name
Test status
Simulation time 343250732 ps
CPU time 0.98 seconds
Started Jul 30 06:23:07 PM PDT 24
Finished Jul 30 06:23:08 PM PDT 24
Peak memory 193032 kb
Host smart-b4fd4cec-0769-4f9a-b0d7-ec3b527d9fba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836566395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.836566395
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3325868198
Short name T62
Test name
Test status
Simulation time 595128099 ps
CPU time 1.54 seconds
Started Jul 30 06:22:35 PM PDT 24
Finished Jul 30 06:22:36 PM PDT 24
Peak memory 194728 kb
Host smart-999331c7-d590-429b-94e8-c53bbd95d08f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325868198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.3325868198
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.248803384
Short name T367
Test name
Test status
Simulation time 7274729943 ps
CPU time 14.74 seconds
Started Jul 30 06:22:37 PM PDT 24
Finished Jul 30 06:22:52 PM PDT 24
Peak memory 192272 kb
Host smart-b3a0c42f-57b4-4c65-a55d-928ca2d0514d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248803384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bi
t_bash.248803384
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.175760869
Short name T314
Test name
Test status
Simulation time 768177143 ps
CPU time 0.8 seconds
Started Jul 30 06:22:33 PM PDT 24
Finished Jul 30 06:22:34 PM PDT 24
Peak memory 183760 kb
Host smart-9bc3b346-aecf-43fd-b1b4-db07f4029157
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175760869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.175760869
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2346688784
Short name T196
Test name
Test status
Simulation time 333660067 ps
CPU time 1.12 seconds
Started Jul 30 06:22:36 PM PDT 24
Finished Jul 30 06:22:37 PM PDT 24
Peak memory 195976 kb
Host smart-e5b5eda7-71e4-4fdd-88ab-4c1e3915a6a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346688784 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.2346688784
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2709727948
Short name T318
Test name
Test status
Simulation time 503423057 ps
CPU time 1.2 seconds
Started Jul 30 06:22:31 PM PDT 24
Finished Jul 30 06:22:33 PM PDT 24
Peak memory 193288 kb
Host smart-875cbaa1-79e0-495f-a777-b174936151ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709727948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2709727948
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.525040422
Short name T321
Test name
Test status
Simulation time 422356116 ps
CPU time 0.68 seconds
Started Jul 30 06:22:30 PM PDT 24
Finished Jul 30 06:22:31 PM PDT 24
Peak memory 192988 kb
Host smart-6fb85632-e343-4b29-836b-444ca920b397
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525040422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.525040422
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3238139908
Short name T289
Test name
Test status
Simulation time 279042407 ps
CPU time 0.89 seconds
Started Jul 30 06:22:34 PM PDT 24
Finished Jul 30 06:22:35 PM PDT 24
Peak memory 183620 kb
Host smart-65cd9680-8a96-4727-a986-6360b3d81f75
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238139908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3238139908
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.26357905
Short name T298
Test name
Test status
Simulation time 490133956 ps
CPU time 0.83 seconds
Started Jul 30 06:22:33 PM PDT 24
Finished Jul 30 06:22:34 PM PDT 24
Peak memory 183760 kb
Host smart-5125b990-fadc-40f3-8b95-d985ae3a1c90
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26357905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_wal
k.26357905
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1582300415
Short name T73
Test name
Test status
Simulation time 1594612952 ps
CPU time 2.05 seconds
Started Jul 30 06:22:34 PM PDT 24
Finished Jul 30 06:22:36 PM PDT 24
Peak memory 193332 kb
Host smart-18f8e1ca-8d66-40d3-b15c-b74e060aaa72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582300415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.1582300415
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3794099478
Short name T294
Test name
Test status
Simulation time 1615725533 ps
CPU time 1.47 seconds
Started Jul 30 06:22:34 PM PDT 24
Finished Jul 30 06:22:35 PM PDT 24
Peak memory 198664 kb
Host smart-e5b484aa-fcbf-4381-9242-e3e46c02a423
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794099478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3794099478
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2230294413
Short name T192
Test name
Test status
Simulation time 7977175420 ps
CPU time 4.48 seconds
Started Jul 30 06:22:34 PM PDT 24
Finished Jul 30 06:22:39 PM PDT 24
Peak memory 198148 kb
Host smart-96a06583-5712-4160-95c7-18d6ef9dbc1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230294413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.2230294413
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1649599122
Short name T385
Test name
Test status
Simulation time 424565126 ps
CPU time 0.69 seconds
Started Jul 30 06:23:07 PM PDT 24
Finished Jul 30 06:23:08 PM PDT 24
Peak memory 193032 kb
Host smart-e1009524-1f18-4235-a53f-2dced307a0a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649599122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.1649599122
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.660648510
Short name T334
Test name
Test status
Simulation time 377398083 ps
CPU time 0.99 seconds
Started Jul 30 06:23:07 PM PDT 24
Finished Jul 30 06:23:08 PM PDT 24
Peak memory 183812 kb
Host smart-25508ecc-15ec-4621-b917-633162cdb69c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660648510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.660648510
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3796418432
Short name T316
Test name
Test status
Simulation time 540854302 ps
CPU time 0.58 seconds
Started Jul 30 06:23:01 PM PDT 24
Finished Jul 30 06:23:02 PM PDT 24
Peak memory 183780 kb
Host smart-a8c68718-513a-4544-86a8-f09a4cd92944
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796418432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.3796418432
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3693763794
Short name T302
Test name
Test status
Simulation time 469897892 ps
CPU time 0.84 seconds
Started Jul 30 06:23:02 PM PDT 24
Finished Jul 30 06:23:03 PM PDT 24
Peak memory 183768 kb
Host smart-b2aa8468-d6c1-4176-9f2a-34da5bf2d507
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693763794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.3693763794
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.919654983
Short name T284
Test name
Test status
Simulation time 385439064 ps
CPU time 0.85 seconds
Started Jul 30 06:23:02 PM PDT 24
Finished Jul 30 06:23:03 PM PDT 24
Peak memory 183776 kb
Host smart-d95f37d3-6fc9-4330-84d8-83559fd3b570
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919654983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.919654983
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2322478978
Short name T320
Test name
Test status
Simulation time 462257813 ps
CPU time 1.24 seconds
Started Jul 30 06:23:03 PM PDT 24
Finished Jul 30 06:23:04 PM PDT 24
Peak memory 183848 kb
Host smart-533f67d5-bb94-4cce-b443-dbdc2d3f3ddb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322478978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2322478978
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2230066209
Short name T279
Test name
Test status
Simulation time 389044613 ps
CPU time 0.68 seconds
Started Jul 30 06:23:07 PM PDT 24
Finished Jul 30 06:23:07 PM PDT 24
Peak memory 193032 kb
Host smart-91de5d8e-9193-4a80-9fb8-464df397696e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230066209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2230066209
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3806457693
Short name T280
Test name
Test status
Simulation time 296474603 ps
CPU time 0.76 seconds
Started Jul 30 06:23:02 PM PDT 24
Finished Jul 30 06:23:03 PM PDT 24
Peak memory 183848 kb
Host smart-140edce1-d569-42c5-acb3-be22131b2e65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806457693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3806457693
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.824754915
Short name T386
Test name
Test status
Simulation time 448541632 ps
CPU time 1.32 seconds
Started Jul 30 06:23:01 PM PDT 24
Finished Jul 30 06:23:02 PM PDT 24
Peak memory 192996 kb
Host smart-e58e03ca-f774-4111-be32-c1f936be53ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824754915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.824754915
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.4282639567
Short name T281
Test name
Test status
Simulation time 505228478 ps
CPU time 1.26 seconds
Started Jul 30 06:23:03 PM PDT 24
Finished Jul 30 06:23:04 PM PDT 24
Peak memory 193068 kb
Host smart-b590b67d-8db1-4fd9-8373-739a43043f88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282639567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.4282639567
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1330337329
Short name T407
Test name
Test status
Simulation time 452214366 ps
CPU time 0.85 seconds
Started Jul 30 06:22:36 PM PDT 24
Finished Jul 30 06:22:37 PM PDT 24
Peak memory 195936 kb
Host smart-beecf3ea-d35a-4f65-8554-25469b3c8c1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330337329 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1330337329
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1452847369
Short name T382
Test name
Test status
Simulation time 405972823 ps
CPU time 0.73 seconds
Started Jul 30 06:22:34 PM PDT 24
Finished Jul 30 06:22:35 PM PDT 24
Peak memory 193300 kb
Host smart-69306667-739e-4179-8283-ffc3c7bfe239
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452847369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1452847369
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.754264656
Short name T299
Test name
Test status
Simulation time 443027837 ps
CPU time 1.13 seconds
Started Jul 30 06:22:37 PM PDT 24
Finished Jul 30 06:22:38 PM PDT 24
Peak memory 183820 kb
Host smart-619c2517-91ac-489c-94a6-6568bc31720f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754264656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.754264656
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1009384833
Short name T361
Test name
Test status
Simulation time 2462305610 ps
CPU time 3.77 seconds
Started Jul 30 06:22:46 PM PDT 24
Finished Jul 30 06:22:50 PM PDT 24
Peak memory 194340 kb
Host smart-a6dd6e1b-7fd5-4a69-81a6-828a2620458a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009384833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.1009384833
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1472527369
Short name T277
Test name
Test status
Simulation time 567704978 ps
CPU time 2.79 seconds
Started Jul 30 06:22:46 PM PDT 24
Finished Jul 30 06:22:49 PM PDT 24
Peak memory 198640 kb
Host smart-0a052f40-007b-4a8f-ac88-91eb1b1f4be5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472527369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1472527369
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3232382506
Short name T37
Test name
Test status
Simulation time 8246642499 ps
CPU time 4.03 seconds
Started Jul 30 06:22:35 PM PDT 24
Finished Jul 30 06:22:39 PM PDT 24
Peak memory 198272 kb
Host smart-acd07917-37b1-46b0-92e5-8654833a5e8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232382506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.3232382506
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1476531663
Short name T194
Test name
Test status
Simulation time 332045466 ps
CPU time 0.91 seconds
Started Jul 30 06:22:36 PM PDT 24
Finished Jul 30 06:22:37 PM PDT 24
Peak memory 196260 kb
Host smart-f7fa1263-0e3f-445d-9c81-6a2d842f4b8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476531663 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1476531663
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2609428606
Short name T59
Test name
Test status
Simulation time 545784878 ps
CPU time 0.79 seconds
Started Jul 30 06:22:36 PM PDT 24
Finished Jul 30 06:22:37 PM PDT 24
Peak memory 193060 kb
Host smart-7bec03ff-10e7-4a7d-a1be-e42ad9294cd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609428606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.2609428606
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.708753782
Short name T344
Test name
Test status
Simulation time 418791592 ps
CPU time 0.67 seconds
Started Jul 30 06:22:35 PM PDT 24
Finished Jul 30 06:22:36 PM PDT 24
Peak memory 183736 kb
Host smart-134728d4-4638-4556-a3fc-0a4f3b57bcc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708753782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.708753782
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1651516334
Short name T75
Test name
Test status
Simulation time 1179087034 ps
CPU time 1.24 seconds
Started Jul 30 06:22:35 PM PDT 24
Finished Jul 30 06:22:36 PM PDT 24
Peak memory 193988 kb
Host smart-3e994108-1cd0-4cd1-b9c2-dad04b5e94e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651516334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.1651516334
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3866530955
Short name T395
Test name
Test status
Simulation time 525748298 ps
CPU time 1.48 seconds
Started Jul 30 06:22:35 PM PDT 24
Finished Jul 30 06:22:37 PM PDT 24
Peak memory 198588 kb
Host smart-f98096fa-9480-4f44-87fa-e6ba5ae2a7d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866530955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3866530955
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.654379508
Short name T396
Test name
Test status
Simulation time 4580020391 ps
CPU time 7.56 seconds
Started Jul 30 06:22:38 PM PDT 24
Finished Jul 30 06:22:46 PM PDT 24
Peak memory 196844 kb
Host smart-0e31ad91-996b-45c4-b420-a2b1ad5449a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654379508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_
intg_err.654379508
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.264747143
Short name T336
Test name
Test status
Simulation time 474321396 ps
CPU time 1.33 seconds
Started Jul 30 06:22:35 PM PDT 24
Finished Jul 30 06:22:37 PM PDT 24
Peak memory 196068 kb
Host smart-e23b569e-3bfc-4111-a82a-5dd5d256c90c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264747143 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.264747143
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.4294253401
Short name T306
Test name
Test status
Simulation time 314904259 ps
CPU time 0.78 seconds
Started Jul 30 06:22:46 PM PDT 24
Finished Jul 30 06:22:47 PM PDT 24
Peak memory 183768 kb
Host smart-efdafce3-04cc-4208-9030-7f525f0f33bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294253401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.4294253401
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1449041431
Short name T77
Test name
Test status
Simulation time 1558807877 ps
CPU time 1.43 seconds
Started Jul 30 06:22:37 PM PDT 24
Finished Jul 30 06:22:39 PM PDT 24
Peak memory 193024 kb
Host smart-653b47ed-5a23-449c-b44d-63d37aff6694
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449041431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.1449041431
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2156037808
Short name T399
Test name
Test status
Simulation time 368770419 ps
CPU time 2.11 seconds
Started Jul 30 06:22:34 PM PDT 24
Finished Jul 30 06:22:36 PM PDT 24
Peak memory 198568 kb
Host smart-7e5c8e0b-2b0f-4778-89d4-49677f14b6ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156037808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.2156037808
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.532219574
Short name T351
Test name
Test status
Simulation time 8586843634 ps
CPU time 12.92 seconds
Started Jul 30 06:22:34 PM PDT 24
Finished Jul 30 06:22:47 PM PDT 24
Peak memory 198244 kb
Host smart-d3c88de8-1fc3-4ce3-8d1d-583aaa5bf215
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532219574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_
intg_err.532219574
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.18141683
Short name T392
Test name
Test status
Simulation time 641541455 ps
CPU time 0.93 seconds
Started Jul 30 06:22:39 PM PDT 24
Finished Jul 30 06:22:40 PM PDT 24
Peak memory 198464 kb
Host smart-ca9977b9-9023-43eb-8152-817d95d076fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18141683 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.18141683
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2237801078
Short name T406
Test name
Test status
Simulation time 451884279 ps
CPU time 0.64 seconds
Started Jul 30 06:22:36 PM PDT 24
Finished Jul 30 06:22:37 PM PDT 24
Peak memory 193296 kb
Host smart-f246d850-db97-4785-9cb9-c38f94c34b65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237801078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2237801078
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1132862127
Short name T341
Test name
Test status
Simulation time 386157283 ps
CPU time 0.97 seconds
Started Jul 30 06:22:37 PM PDT 24
Finished Jul 30 06:22:39 PM PDT 24
Peak memory 193000 kb
Host smart-88821090-5a8e-49bf-965d-204b25644701
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132862127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.1132862127
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.4056055617
Short name T370
Test name
Test status
Simulation time 1523931834 ps
CPU time 1.6 seconds
Started Jul 30 06:22:46 PM PDT 24
Finished Jul 30 06:22:48 PM PDT 24
Peak memory 193264 kb
Host smart-55789af5-646e-4aec-a04b-6866af8a8f7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056055617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.4056055617
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2348911671
Short name T337
Test name
Test status
Simulation time 342015449 ps
CPU time 1.96 seconds
Started Jul 30 06:22:36 PM PDT 24
Finished Jul 30 06:22:38 PM PDT 24
Peak memory 198764 kb
Host smart-6e784b45-a674-4277-9d27-5caca9be95f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348911671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2348911671
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1218417102
Short name T390
Test name
Test status
Simulation time 4085343245 ps
CPU time 3.37 seconds
Started Jul 30 06:22:37 PM PDT 24
Finished Jul 30 06:22:40 PM PDT 24
Peak memory 197864 kb
Host smart-e3c64541-c4ba-44bb-9287-56bb4825405f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218417102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.1218417102
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1228399645
Short name T389
Test name
Test status
Simulation time 574951918 ps
CPU time 1.14 seconds
Started Jul 30 06:22:41 PM PDT 24
Finished Jul 30 06:22:43 PM PDT 24
Peak memory 196280 kb
Host smart-bdf6bfd3-e72f-4821-932c-4ee79794983c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228399645 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.1228399645
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1946350925
Short name T322
Test name
Test status
Simulation time 554906557 ps
CPU time 0.78 seconds
Started Jul 30 06:22:40 PM PDT 24
Finished Jul 30 06:22:41 PM PDT 24
Peak memory 193988 kb
Host smart-ca42ff8a-05d4-4bbb-ab86-f1e9baad4057
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946350925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.1946350925
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.385655950
Short name T415
Test name
Test status
Simulation time 352743281 ps
CPU time 0.65 seconds
Started Jul 30 06:22:46 PM PDT 24
Finished Jul 30 06:22:47 PM PDT 24
Peak memory 192996 kb
Host smart-12a055b0-e23b-4bf6-a925-3998e2ab7d88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385655950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.385655950
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2791028193
Short name T346
Test name
Test status
Simulation time 1677748474 ps
CPU time 4.71 seconds
Started Jul 30 06:22:37 PM PDT 24
Finished Jul 30 06:22:42 PM PDT 24
Peak memory 194960 kb
Host smart-1d53776a-3f8d-4147-99e6-66d5a3c846c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791028193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2791028193
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.90655313
Short name T377
Test name
Test status
Simulation time 493919584 ps
CPU time 1.94 seconds
Started Jul 30 06:22:40 PM PDT 24
Finished Jul 30 06:22:42 PM PDT 24
Peak memory 198592 kb
Host smart-f9d31bc9-89da-493e-a175-f60ad8d972c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90655313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.90655313
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1476823765
Short name T326
Test name
Test status
Simulation time 4283092116 ps
CPU time 2.21 seconds
Started Jul 30 06:22:38 PM PDT 24
Finished Jul 30 06:22:41 PM PDT 24
Peak memory 197868 kb
Host smart-cbb2d8ca-a9e2-43ee-9801-90677dec2a2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476823765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.1476823765
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.1615038071
Short name T248
Test name
Test status
Simulation time 32722277572 ps
CPU time 11.86 seconds
Started Jul 30 06:43:17 PM PDT 24
Finished Jul 30 06:43:29 PM PDT 24
Peak memory 196876 kb
Host smart-cee52f31-0e1b-4ff1-bd53-e5cff3a98328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615038071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1615038071
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.2209923713
Short name T251
Test name
Test status
Simulation time 499405798 ps
CPU time 0.72 seconds
Started Jul 30 06:43:24 PM PDT 24
Finished Jul 30 06:43:25 PM PDT 24
Peak memory 191860 kb
Host smart-a432ac9d-e342-4706-8ac8-f81f789a7f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209923713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.2209923713
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3190050853
Short name T165
Test name
Test status
Simulation time 528788396 ps
CPU time 0.73 seconds
Started Jul 30 06:44:38 PM PDT 24
Finished Jul 30 06:44:39 PM PDT 24
Peak memory 196308 kb
Host smart-2742a3a5-8ae5-4b78-a473-077cc8729f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190050853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3190050853
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.3844969496
Short name T240
Test name
Test status
Simulation time 21050073632 ps
CPU time 32.96 seconds
Started Jul 30 06:43:25 PM PDT 24
Finished Jul 30 06:43:58 PM PDT 24
Peak memory 196564 kb
Host smart-56ab5f74-4244-427d-b51c-920094fe7373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844969496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3844969496
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3363216454
Short name T18
Test name
Test status
Simulation time 4249288731 ps
CPU time 3.86 seconds
Started Jul 30 06:43:20 PM PDT 24
Finished Jul 30 06:43:24 PM PDT 24
Peak memory 215344 kb
Host smart-3923b9eb-9bfa-4407-b5d1-a33dcb5055b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363216454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3363216454
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.353929940
Short name T7
Test name
Test status
Simulation time 488248398 ps
CPU time 0.97 seconds
Started Jul 30 06:43:26 PM PDT 24
Finished Jul 30 06:43:27 PM PDT 24
Peak memory 196712 kb
Host smart-554e51ce-b485-42b7-95b3-d90011813325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353929940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.353929940
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.3147475592
Short name T39
Test name
Test status
Simulation time 20494415140 ps
CPU time 7.05 seconds
Started Jul 30 06:43:35 PM PDT 24
Finished Jul 30 06:43:42 PM PDT 24
Peak memory 191840 kb
Host smart-d310714b-155a-4447-a7af-b1458c171953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147475592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3147475592
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.744126169
Short name T93
Test name
Test status
Simulation time 391007565 ps
CPU time 0.72 seconds
Started Jul 30 06:43:26 PM PDT 24
Finished Jul 30 06:43:27 PM PDT 24
Peak memory 191816 kb
Host smart-ba727f67-028d-4408-af99-533b89ab3d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744126169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.744126169
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.2929755174
Short name T217
Test name
Test status
Simulation time 14357769723 ps
CPU time 22.26 seconds
Started Jul 30 06:43:28 PM PDT 24
Finished Jul 30 06:43:50 PM PDT 24
Peak memory 196924 kb
Host smart-0a7e832e-a45a-4c5e-a6ed-39aa73790966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929755174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.2929755174
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.1938358679
Short name T27
Test name
Test status
Simulation time 467590889 ps
CPU time 1.28 seconds
Started Jul 30 06:43:29 PM PDT 24
Finished Jul 30 06:43:30 PM PDT 24
Peak memory 191752 kb
Host smart-61c93d0e-d9e2-4f31-8e67-fb9d9363be41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938358679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.1938358679
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.1129542957
Short name T203
Test name
Test status
Simulation time 19548598468 ps
CPU time 16.43 seconds
Started Jul 30 06:43:46 PM PDT 24
Finished Jul 30 06:44:03 PM PDT 24
Peak memory 191892 kb
Host smart-3f07457e-d88e-47aa-95ee-89363bd644f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129542957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1129542957
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.307572106
Short name T97
Test name
Test status
Simulation time 503765772 ps
CPU time 0.85 seconds
Started Jul 30 06:43:39 PM PDT 24
Finished Jul 30 06:43:39 PM PDT 24
Peak memory 191800 kb
Host smart-ba4bc6ec-0e0c-436d-b3c5-1789a1f5097b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307572106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.307572106
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3971007019
Short name T229
Test name
Test status
Simulation time 44133439043 ps
CPU time 32.3 seconds
Started Jul 30 06:43:44 PM PDT 24
Finished Jul 30 06:44:17 PM PDT 24
Peak memory 196876 kb
Host smart-71dfcc9c-be40-4385-9be6-834524f99e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971007019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3971007019
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.696686918
Short name T261
Test name
Test status
Simulation time 595120544 ps
CPU time 0.83 seconds
Started Jul 30 06:43:31 PM PDT 24
Finished Jul 30 06:43:32 PM PDT 24
Peak memory 191800 kb
Host smart-4e996902-a3ec-4cb0-b30a-595567a8f339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696686918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.696686918
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.739265664
Short name T3
Test name
Test status
Simulation time 29202884204 ps
CPU time 10.46 seconds
Started Jul 30 06:43:42 PM PDT 24
Finished Jul 30 06:43:53 PM PDT 24
Peak memory 191872 kb
Host smart-73d0771b-ad12-45a1-b5ba-ffe869181d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739265664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.739265664
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.207257937
Short name T197
Test name
Test status
Simulation time 511603762 ps
CPU time 1.29 seconds
Started Jul 30 06:43:38 PM PDT 24
Finished Jul 30 06:43:39 PM PDT 24
Peak memory 191848 kb
Host smart-db9b5d7f-3f58-4a05-b11e-890e56b98c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207257937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.207257937
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_jump.3500910729
Short name T43
Test name
Test status
Simulation time 429657505 ps
CPU time 0.78 seconds
Started Jul 30 06:43:24 PM PDT 24
Finished Jul 30 06:43:25 PM PDT 24
Peak memory 196684 kb
Host smart-2aba812d-ebaa-436e-87df-8c7b51325ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500910729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3500910729
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.2298484339
Short name T193
Test name
Test status
Simulation time 37346951870 ps
CPU time 15.8 seconds
Started Jul 30 06:43:23 PM PDT 24
Finished Jul 30 06:43:39 PM PDT 24
Peak memory 191896 kb
Host smart-e0d4d656-271b-4903-8ff6-47994950f9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298484339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2298484339
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.945406284
Short name T270
Test name
Test status
Simulation time 602956211 ps
CPU time 0.77 seconds
Started Jul 30 06:43:22 PM PDT 24
Finished Jul 30 06:43:23 PM PDT 24
Peak memory 191828 kb
Host smart-3a910ccd-853a-4581-8f78-a13b9c306020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945406284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.945406284
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1852937024
Short name T201
Test name
Test status
Simulation time 42626871643 ps
CPU time 63.25 seconds
Started Jul 30 06:43:50 PM PDT 24
Finished Jul 30 06:44:58 PM PDT 24
Peak memory 196852 kb
Host smart-822a5cb9-114b-48fc-8c46-31a0336f1608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852937024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1852937024
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.1471434624
Short name T255
Test name
Test status
Simulation time 413358796 ps
CPU time 1.13 seconds
Started Jul 30 06:43:28 PM PDT 24
Finished Jul 30 06:43:30 PM PDT 24
Peak memory 191828 kb
Host smart-62cb0f1c-9958-4feb-a460-d5045de55701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471434624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.1471434624
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.955856277
Short name T228
Test name
Test status
Simulation time 41966788723 ps
CPU time 17.42 seconds
Started Jul 30 06:43:38 PM PDT 24
Finished Jul 30 06:43:56 PM PDT 24
Peak memory 191868 kb
Host smart-1ba5e128-5954-4027-bab8-adc82a6047f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955856277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.955856277
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.3439689239
Short name T2
Test name
Test status
Simulation time 490191730 ps
CPU time 0.71 seconds
Started Jul 30 06:43:41 PM PDT 24
Finished Jul 30 06:43:42 PM PDT 24
Peak memory 191792 kb
Host smart-3fe927de-8ebf-4c0e-80a3-532353b9250a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439689239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3439689239
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.31206576
Short name T202
Test name
Test status
Simulation time 2656213508 ps
CPU time 1.71 seconds
Started Jul 30 06:43:28 PM PDT 24
Finished Jul 30 06:43:30 PM PDT 24
Peak memory 191916 kb
Host smart-19b76f42-7d63-48d4-82ae-15f0578c4e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31206576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.31206576
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.1883090109
Short name T235
Test name
Test status
Simulation time 420884462 ps
CPU time 1.1 seconds
Started Jul 30 06:43:30 PM PDT 24
Finished Jul 30 06:43:31 PM PDT 24
Peak memory 196648 kb
Host smart-51c9cc67-0749-4a0e-841c-fa4c56603124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883090109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1883090109
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.3038298986
Short name T222
Test name
Test status
Simulation time 60984889911 ps
CPU time 23.9 seconds
Started Jul 30 06:43:29 PM PDT 24
Finished Jul 30 06:43:53 PM PDT 24
Peak memory 191844 kb
Host smart-83e39a8a-7965-40ed-9450-a4ce0c94a90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038298986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.3038298986
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1950338548
Short name T259
Test name
Test status
Simulation time 435341978 ps
CPU time 0.78 seconds
Started Jul 30 06:43:45 PM PDT 24
Finished Jul 30 06:43:46 PM PDT 24
Peak memory 191796 kb
Host smart-fb76c8f1-3a26-4448-a685-c2b6450fa4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950338548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1950338548
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3314013063
Short name T188
Test name
Test status
Simulation time 20860729055 ps
CPU time 167.02 seconds
Started Jul 30 06:43:32 PM PDT 24
Finished Jul 30 06:46:19 PM PDT 24
Peak memory 198480 kb
Host smart-f8dc316b-9454-48f7-8517-7f8fd8e366cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314013063 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3314013063
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1823245291
Short name T214
Test name
Test status
Simulation time 32938726746 ps
CPU time 45.57 seconds
Started Jul 30 06:44:39 PM PDT 24
Finished Jul 30 06:45:25 PM PDT 24
Peak memory 191616 kb
Host smart-3466c99c-3d68-4dd8-9abc-4a0e2f7e4a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823245291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1823245291
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.4274253230
Short name T15
Test name
Test status
Simulation time 4582739600 ps
CPU time 1.15 seconds
Started Jul 30 06:43:25 PM PDT 24
Finished Jul 30 06:43:26 PM PDT 24
Peak memory 215756 kb
Host smart-281ff03d-7011-4ea1-8fe0-e4d05cc3d0cd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274253230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.4274253230
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.2979050509
Short name T267
Test name
Test status
Simulation time 494924886 ps
CPU time 0.73 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:22 PM PDT 24
Peak memory 190708 kb
Host smart-65185407-96e1-4f8f-9e74-6bb57cc065a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979050509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2979050509
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1920103302
Short name T242
Test name
Test status
Simulation time 31142183577 ps
CPU time 13.26 seconds
Started Jul 30 06:43:47 PM PDT 24
Finished Jul 30 06:44:01 PM PDT 24
Peak memory 191896 kb
Host smart-fb4585f5-3a7b-4444-b148-0fba5af5f3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920103302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1920103302
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2731450113
Short name T252
Test name
Test status
Simulation time 403972416 ps
CPU time 1.2 seconds
Started Jul 30 06:43:34 PM PDT 24
Finished Jul 30 06:43:35 PM PDT 24
Peak memory 196712 kb
Host smart-838b662a-664d-4cec-8e9f-3c995a245175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731450113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2731450113
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.2588150229
Short name T232
Test name
Test status
Simulation time 58352716110 ps
CPU time 47.53 seconds
Started Jul 30 06:44:09 PM PDT 24
Finished Jul 30 06:44:57 PM PDT 24
Peak memory 191848 kb
Host smart-3cd757d3-2a08-4d8d-a850-43bc70c94307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588150229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.2588150229
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1952214037
Short name T49
Test name
Test status
Simulation time 589645177 ps
CPU time 0.79 seconds
Started Jul 30 06:43:57 PM PDT 24
Finished Jul 30 06:43:58 PM PDT 24
Peak memory 191808 kb
Host smart-96ba9cda-4836-4b16-844c-311b7e9e869f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952214037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1952214037
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.3859858944
Short name T241
Test name
Test status
Simulation time 20508383885 ps
CPU time 13.94 seconds
Started Jul 30 06:43:36 PM PDT 24
Finished Jul 30 06:43:50 PM PDT 24
Peak memory 191912 kb
Host smart-be6db417-7886-4bc3-afaf-aba345181e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859858944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.3859858944
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1997285915
Short name T274
Test name
Test status
Simulation time 400974878 ps
CPU time 0.71 seconds
Started Jul 30 06:43:40 PM PDT 24
Finished Jul 30 06:43:41 PM PDT 24
Peak memory 191828 kb
Host smart-123a4678-cb72-4e15-a767-eac3b5b28b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997285915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1997285915
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.3183256593
Short name T273
Test name
Test status
Simulation time 18826577479 ps
CPU time 26.88 seconds
Started Jul 30 06:43:45 PM PDT 24
Finished Jul 30 06:44:12 PM PDT 24
Peak memory 191880 kb
Host smart-4be96ecc-b18b-4a19-a3d7-9f2b274bbc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183256593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.3183256593
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.125584579
Short name T275
Test name
Test status
Simulation time 367197888 ps
CPU time 0.82 seconds
Started Jul 30 06:43:45 PM PDT 24
Finished Jul 30 06:43:46 PM PDT 24
Peak memory 191824 kb
Host smart-40c9c266-7edf-4770-8bd6-3e24853ef892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125584579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.125584579
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2896867773
Short name T260
Test name
Test status
Simulation time 24061151115 ps
CPU time 18.26 seconds
Started Jul 30 06:43:45 PM PDT 24
Finished Jul 30 06:44:03 PM PDT 24
Peak memory 191872 kb
Host smart-a9b590b9-6fee-4bcb-9024-7d11ddd2ebe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896867773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2896867773
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.134831710
Short name T226
Test name
Test status
Simulation time 615300663 ps
CPU time 0.85 seconds
Started Jul 30 06:43:33 PM PDT 24
Finished Jul 30 06:43:34 PM PDT 24
Peak memory 196732 kb
Host smart-cb1c8ebc-56b1-4c17-9c81-17cb31a37f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134831710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.134831710
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1082449558
Short name T182
Test name
Test status
Simulation time 389005953 ps
CPU time 0.72 seconds
Started Jul 30 06:43:40 PM PDT 24
Finished Jul 30 06:43:41 PM PDT 24
Peak memory 196644 kb
Host smart-c6ed7f24-9470-43eb-a8e1-dda21522125f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082449558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1082449558
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1247836314
Short name T207
Test name
Test status
Simulation time 1372948905 ps
CPU time 0.9 seconds
Started Jul 30 06:43:34 PM PDT 24
Finished Jul 30 06:43:35 PM PDT 24
Peak memory 191860 kb
Host smart-1b427220-60cb-4213-9831-a9717a04df36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247836314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1247836314
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.228372422
Short name T209
Test name
Test status
Simulation time 625896416 ps
CPU time 0.81 seconds
Started Jul 30 06:43:34 PM PDT 24
Finished Jul 30 06:43:35 PM PDT 24
Peak memory 191824 kb
Host smart-3125bcea-abe5-4627-b34b-247382aa8593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228372422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.228372422
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.153687027
Short name T57
Test name
Test status
Simulation time 12347978716 ps
CPU time 5.3 seconds
Started Jul 30 06:43:53 PM PDT 24
Finished Jul 30 06:43:58 PM PDT 24
Peak memory 191884 kb
Host smart-b960eea8-b478-4d29-aba8-3b8d8f106ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153687027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.153687027
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.891653383
Short name T264
Test name
Test status
Simulation time 520897553 ps
CPU time 0.88 seconds
Started Jul 30 06:43:57 PM PDT 24
Finished Jul 30 06:43:58 PM PDT 24
Peak memory 191760 kb
Host smart-4166744e-6c1b-4e7b-8526-755387193817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891653383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.891653383
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_jump.1104335918
Short name T187
Test name
Test status
Simulation time 535678674 ps
CPU time 0.81 seconds
Started Jul 30 06:43:48 PM PDT 24
Finished Jul 30 06:43:49 PM PDT 24
Peak memory 196680 kb
Host smart-365514e9-2c85-42b3-a878-5ea3838ab486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104335918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.1104335918
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.1325750896
Short name T225
Test name
Test status
Simulation time 44774890352 ps
CPU time 71.73 seconds
Started Jul 30 06:43:56 PM PDT 24
Finished Jul 30 06:45:08 PM PDT 24
Peak memory 191896 kb
Host smart-fb5b5c9a-a5c0-48ee-89c2-4d9d77de6a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325750896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1325750896
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.814821697
Short name T199
Test name
Test status
Simulation time 359981917 ps
CPU time 0.73 seconds
Started Jul 30 06:44:01 PM PDT 24
Finished Jul 30 06:44:02 PM PDT 24
Peak memory 191812 kb
Host smart-befc5356-36a8-4618-a12c-700cb97d5e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814821697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.814821697
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_jump.3512130974
Short name T178
Test name
Test status
Simulation time 496219849 ps
CPU time 1.31 seconds
Started Jul 30 06:43:46 PM PDT 24
Finished Jul 30 06:43:48 PM PDT 24
Peak memory 196608 kb
Host smart-603a0302-46a4-46de-936e-3fefe32e5760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512130974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3512130974
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.2958700067
Short name T236
Test name
Test status
Simulation time 40212634985 ps
CPU time 55.21 seconds
Started Jul 30 06:43:58 PM PDT 24
Finished Jul 30 06:44:53 PM PDT 24
Peak memory 192028 kb
Host smart-6c55f743-3ee7-4b30-9f8f-48be2d4f68fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958700067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.2958700067
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.115819535
Short name T223
Test name
Test status
Simulation time 361452446 ps
CPU time 0.71 seconds
Started Jul 30 06:43:49 PM PDT 24
Finished Jul 30 06:43:50 PM PDT 24
Peak memory 191812 kb
Host smart-86dba394-8d67-48c9-9966-5beee99fcd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115819535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.115819535
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.824182941
Short name T224
Test name
Test status
Simulation time 38819246276 ps
CPU time 7.19 seconds
Started Jul 30 06:43:51 PM PDT 24
Finished Jul 30 06:43:58 PM PDT 24
Peak memory 191900 kb
Host smart-66c830ba-7999-4446-be0f-53582881cf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824182941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.824182941
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.3100808887
Short name T256
Test name
Test status
Simulation time 369347609 ps
CPU time 1.08 seconds
Started Jul 30 06:43:41 PM PDT 24
Finished Jul 30 06:43:42 PM PDT 24
Peak memory 191788 kb
Host smart-9d5c9ecf-48a7-4d75-ae68-fa50fde53d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100808887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.3100808887
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.907629450
Short name T249
Test name
Test status
Simulation time 20303046289 ps
CPU time 19.14 seconds
Started Jul 30 06:43:24 PM PDT 24
Finished Jul 30 06:43:44 PM PDT 24
Peak memory 196768 kb
Host smart-8d1d2cce-c1cd-48a4-8e92-74f780ec9d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907629450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.907629450
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2375390813
Short name T16
Test name
Test status
Simulation time 8767267979 ps
CPU time 3.74 seconds
Started Jul 30 06:43:26 PM PDT 24
Finished Jul 30 06:43:30 PM PDT 24
Peak memory 215728 kb
Host smart-fc056b10-586f-470c-9056-909315dc323a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375390813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2375390813
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.3002952739
Short name T206
Test name
Test status
Simulation time 475063133 ps
CPU time 0.73 seconds
Started Jul 30 06:43:28 PM PDT 24
Finished Jul 30 06:43:29 PM PDT 24
Peak memory 191860 kb
Host smart-814b9d88-92b9-44bc-8d9d-ce0db2796eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002952739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.3002952739
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_jump.3270577525
Short name T174
Test name
Test status
Simulation time 503615180 ps
CPU time 0.71 seconds
Started Jul 30 06:43:55 PM PDT 24
Finished Jul 30 06:43:56 PM PDT 24
Peak memory 196636 kb
Host smart-77ee2a4f-b10c-4704-a6b4-e1c776a795f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270577525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3270577525
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.3909670548
Short name T94
Test name
Test status
Simulation time 26015947867 ps
CPU time 21.16 seconds
Started Jul 30 06:43:50 PM PDT 24
Finished Jul 30 06:44:11 PM PDT 24
Peak memory 191924 kb
Host smart-c0081320-fa66-42f3-a93f-8c0a7ce923b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909670548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.3909670548
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.14606945
Short name T213
Test name
Test status
Simulation time 595957446 ps
CPU time 1.03 seconds
Started Jul 30 06:43:54 PM PDT 24
Finished Jul 30 06:43:55 PM PDT 24
Peak memory 191812 kb
Host smart-06df7ecb-8443-438a-b34a-87edfd96b922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14606945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.14606945
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.1573189189
Short name T200
Test name
Test status
Simulation time 33820239505 ps
CPU time 28.39 seconds
Started Jul 30 06:43:50 PM PDT 24
Finished Jul 30 06:44:19 PM PDT 24
Peak memory 196916 kb
Host smart-e66dbb5c-db73-4e04-8de7-dc8a7f01edc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573189189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1573189189
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.4008988025
Short name T218
Test name
Test status
Simulation time 421991586 ps
CPU time 1.15 seconds
Started Jul 30 06:43:58 PM PDT 24
Finished Jul 30 06:43:59 PM PDT 24
Peak memory 191792 kb
Host smart-4cf16958-6abb-45de-83c1-92ed9e83dc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008988025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.4008988025
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.4007475022
Short name T198
Test name
Test status
Simulation time 21570740117 ps
CPU time 7.69 seconds
Started Jul 30 06:44:10 PM PDT 24
Finished Jul 30 06:44:17 PM PDT 24
Peak memory 191872 kb
Host smart-85aaa819-a35a-4d46-b76f-3b9edf1e6e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007475022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.4007475022
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.901514374
Short name T9
Test name
Test status
Simulation time 467572863 ps
CPU time 1.11 seconds
Started Jul 30 06:44:01 PM PDT 24
Finished Jul 30 06:44:02 PM PDT 24
Peak memory 191868 kb
Host smart-573e3c90-9e44-4abb-8cee-bf457f1872b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901514374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.901514374
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.2016095165
Short name T263
Test name
Test status
Simulation time 17561738211 ps
CPU time 25.1 seconds
Started Jul 30 06:44:07 PM PDT 24
Finished Jul 30 06:44:32 PM PDT 24
Peak memory 196712 kb
Host smart-527a759f-e6f7-4920-bd8b-1a0fa5875948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016095165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.2016095165
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2306651570
Short name T227
Test name
Test status
Simulation time 506193814 ps
CPU time 0.75 seconds
Started Jul 30 06:44:00 PM PDT 24
Finished Jul 30 06:44:01 PM PDT 24
Peak memory 196620 kb
Host smart-906ee53f-d9a3-4a61-8b35-f75eec199012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306651570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2306651570
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3652056464
Short name T272
Test name
Test status
Simulation time 60090897532 ps
CPU time 40.86 seconds
Started Jul 30 06:44:05 PM PDT 24
Finished Jul 30 06:44:46 PM PDT 24
Peak memory 191888 kb
Host smart-3ccdbc54-32ca-4c81-9196-eb1318586ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652056464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3652056464
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.2194313762
Short name T215
Test name
Test status
Simulation time 334986467 ps
CPU time 1 seconds
Started Jul 30 06:44:06 PM PDT 24
Finished Jul 30 06:44:07 PM PDT 24
Peak memory 196704 kb
Host smart-ead9a51d-e0d4-4348-a1f4-690ea6f18c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194313762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.2194313762
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.505739357
Short name T234
Test name
Test status
Simulation time 12752204492 ps
CPU time 18.12 seconds
Started Jul 30 06:44:08 PM PDT 24
Finished Jul 30 06:44:26 PM PDT 24
Peak memory 191936 kb
Host smart-ba43006e-1983-4c5e-ab87-e4bf6b69375e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505739357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.505739357
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.3016490027
Short name T211
Test name
Test status
Simulation time 595086031 ps
CPU time 1.46 seconds
Started Jul 30 06:44:08 PM PDT 24
Finished Jul 30 06:44:10 PM PDT 24
Peak memory 191812 kb
Host smart-acebe316-2736-4e40-a311-e714f8fb4581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016490027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3016490027
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.3110637805
Short name T244
Test name
Test status
Simulation time 5710838463 ps
CPU time 1.6 seconds
Started Jul 30 06:44:09 PM PDT 24
Finished Jul 30 06:44:11 PM PDT 24
Peak memory 191868 kb
Host smart-b063cf36-3715-4803-b4bc-e8b101d8a88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110637805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.3110637805
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.900487310
Short name T265
Test name
Test status
Simulation time 406228031 ps
CPU time 0.87 seconds
Started Jul 30 06:44:09 PM PDT 24
Finished Jul 30 06:44:10 PM PDT 24
Peak memory 191836 kb
Host smart-f0e7d0e0-c266-4bb5-92e6-b835af318d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900487310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.900487310
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2185780411
Short name T250
Test name
Test status
Simulation time 15476799633 ps
CPU time 12.92 seconds
Started Jul 30 06:44:11 PM PDT 24
Finished Jul 30 06:44:24 PM PDT 24
Peak memory 196892 kb
Host smart-2cd72700-f387-49e0-9f1a-ee47ebc92225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185780411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2185780411
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.3437411895
Short name T233
Test name
Test status
Simulation time 515400059 ps
CPU time 1.26 seconds
Started Jul 30 06:44:02 PM PDT 24
Finished Jul 30 06:44:04 PM PDT 24
Peak memory 196804 kb
Host smart-93d3d167-a239-45db-aca2-487e93aacbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437411895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.3437411895
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.935873743
Short name T238
Test name
Test status
Simulation time 3290571013 ps
CPU time 1.53 seconds
Started Jul 30 06:43:51 PM PDT 24
Finished Jul 30 06:43:53 PM PDT 24
Peak memory 191868 kb
Host smart-0a4fa3a7-0a2b-4773-b7e1-059d35990850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935873743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.935873743
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.514199748
Short name T220
Test name
Test status
Simulation time 445817889 ps
CPU time 0.86 seconds
Started Jul 30 06:44:01 PM PDT 24
Finished Jul 30 06:44:02 PM PDT 24
Peak memory 191732 kb
Host smart-990aa045-91fd-4420-a1e2-7390e84f659f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514199748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.514199748
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_jump.3766832291
Short name T189
Test name
Test status
Simulation time 555461682 ps
CPU time 0.96 seconds
Started Jul 30 06:44:11 PM PDT 24
Finished Jul 30 06:44:12 PM PDT 24
Peak memory 196608 kb
Host smart-577f29b9-da50-43f2-a363-4b6f72fa8a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766832291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.3766832291
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.3064518600
Short name T92
Test name
Test status
Simulation time 35619261244 ps
CPU time 6.48 seconds
Started Jul 30 06:44:01 PM PDT 24
Finished Jul 30 06:44:08 PM PDT 24
Peak memory 191716 kb
Host smart-b728844b-9340-41d1-a991-6bd6c5f5c43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064518600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3064518600
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2331758710
Short name T266
Test name
Test status
Simulation time 541273118 ps
CPU time 0.9 seconds
Started Jul 30 06:43:51 PM PDT 24
Finished Jul 30 06:43:52 PM PDT 24
Peak memory 196676 kb
Host smart-fe5a30cc-449c-4d30-afd8-a1fc92252a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331758710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2331758710
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.2923085380
Short name T231
Test name
Test status
Simulation time 7987335298 ps
CPU time 3.51 seconds
Started Jul 30 06:43:25 PM PDT 24
Finished Jul 30 06:43:29 PM PDT 24
Peak memory 191892 kb
Host smart-f3f8a79e-e514-4341-b4e1-efb768300114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923085380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.2923085380
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.67480145
Short name T19
Test name
Test status
Simulation time 7104731891 ps
CPU time 3.18 seconds
Started Jul 30 06:43:24 PM PDT 24
Finished Jul 30 06:43:27 PM PDT 24
Peak memory 215808 kb
Host smart-c05320b5-12e8-4bfb-b4fc-9af0a52221ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67480145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.67480145
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2932083483
Short name T208
Test name
Test status
Simulation time 524785054 ps
CPU time 0.75 seconds
Started Jul 30 06:43:36 PM PDT 24
Finished Jul 30 06:43:37 PM PDT 24
Peak memory 191816 kb
Host smart-85be7d6a-2ed3-4093-bc59-198a3bf19550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932083483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2932083483
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3747324776
Short name T253
Test name
Test status
Simulation time 25820775125 ps
CPU time 10.44 seconds
Started Jul 30 06:44:06 PM PDT 24
Finished Jul 30 06:44:16 PM PDT 24
Peak memory 191912 kb
Host smart-015a242b-2d39-4878-9479-96c3adb5f99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747324776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3747324776
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.2964751044
Short name T246
Test name
Test status
Simulation time 379217675 ps
CPU time 1.1 seconds
Started Jul 30 06:44:06 PM PDT 24
Finished Jul 30 06:44:07 PM PDT 24
Peak memory 191792 kb
Host smart-fd7d07ee-fa7d-4eba-af3b-54ab5e854f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964751044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2964751044
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.3607578369
Short name T237
Test name
Test status
Simulation time 27904385405 ps
CPU time 10.22 seconds
Started Jul 30 06:44:09 PM PDT 24
Finished Jul 30 06:44:19 PM PDT 24
Peak memory 191924 kb
Host smart-70bd0578-1d76-4705-bbd4-3ec9062ec831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607578369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3607578369
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.1367524251
Short name T258
Test name
Test status
Simulation time 447904056 ps
CPU time 0.84 seconds
Started Jul 30 06:44:03 PM PDT 24
Finished Jul 30 06:44:04 PM PDT 24
Peak memory 191784 kb
Host smart-3d05a40d-646d-488e-85c8-f9518500529f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367524251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.1367524251
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.2961242396
Short name T205
Test name
Test status
Simulation time 34040641768 ps
CPU time 45.01 seconds
Started Jul 30 06:44:08 PM PDT 24
Finished Jul 30 06:44:53 PM PDT 24
Peak memory 196892 kb
Host smart-da913429-0439-46a1-9539-50bf2aa41e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961242396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.2961242396
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.3479940969
Short name T230
Test name
Test status
Simulation time 406582283 ps
CPU time 0.73 seconds
Started Jul 30 06:44:18 PM PDT 24
Finished Jul 30 06:44:19 PM PDT 24
Peak memory 191808 kb
Host smart-b129f5dd-f867-4b25-9afa-f043e430283e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479940969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3479940969
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.3351318037
Short name T204
Test name
Test status
Simulation time 3350885278 ps
CPU time 3.14 seconds
Started Jul 30 06:44:14 PM PDT 24
Finished Jul 30 06:44:17 PM PDT 24
Peak memory 191908 kb
Host smart-a24ce93d-8ae3-43f2-b507-a6b76c1d8505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351318037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3351318037
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.561065870
Short name T216
Test name
Test status
Simulation time 508161659 ps
CPU time 1.13 seconds
Started Jul 30 06:44:09 PM PDT 24
Finished Jul 30 06:44:10 PM PDT 24
Peak memory 191828 kb
Host smart-6876842c-2fb9-4aa7-be82-66816cba1b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561065870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.561065870
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.773695437
Short name T239
Test name
Test status
Simulation time 39155445546 ps
CPU time 10.54 seconds
Started Jul 30 06:44:06 PM PDT 24
Finished Jul 30 06:44:17 PM PDT 24
Peak memory 191868 kb
Host smart-e83728db-043f-42a8-95be-a07d9ae9408c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773695437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.773695437
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2470263875
Short name T262
Test name
Test status
Simulation time 564101726 ps
CPU time 0.78 seconds
Started Jul 30 06:44:12 PM PDT 24
Finished Jul 30 06:44:13 PM PDT 24
Peak memory 191852 kb
Host smart-a7e5bb5d-7d75-4796-a037-f6902c43efd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470263875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2470263875
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_jump.1522582665
Short name T184
Test name
Test status
Simulation time 518273121 ps
CPU time 0.77 seconds
Started Jul 30 06:44:10 PM PDT 24
Finished Jul 30 06:44:11 PM PDT 24
Peak memory 196644 kb
Host smart-1804d6dc-af2f-4dfb-9639-bcd399bcd4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522582665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1522582665
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2761135502
Short name T221
Test name
Test status
Simulation time 34800700440 ps
CPU time 52.22 seconds
Started Jul 30 06:44:16 PM PDT 24
Finished Jul 30 06:45:08 PM PDT 24
Peak memory 196916 kb
Host smart-0e11a7cf-c871-4a6d-a688-5f15e201c7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761135502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2761135502
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.3719891010
Short name T52
Test name
Test status
Simulation time 408283501 ps
CPU time 0.7 seconds
Started Jul 30 06:44:24 PM PDT 24
Finished Jul 30 06:44:27 PM PDT 24
Peak memory 191836 kb
Host smart-04026064-90c4-4159-b301-d078d309e817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719891010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3719891010
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.1570770573
Short name T243
Test name
Test status
Simulation time 3229331699 ps
CPU time 0.95 seconds
Started Jul 30 06:44:15 PM PDT 24
Finished Jul 30 06:44:17 PM PDT 24
Peak memory 191872 kb
Host smart-792fbc62-66ce-4d3d-872e-8015a12da939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570770573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1570770573
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.3204674856
Short name T271
Test name
Test status
Simulation time 444759117 ps
CPU time 1.25 seconds
Started Jul 30 06:44:16 PM PDT 24
Finished Jul 30 06:44:17 PM PDT 24
Peak memory 191792 kb
Host smart-8e4f379c-7949-475e-ac4a-1d7b1acc914c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204674856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.3204674856
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.1606441613
Short name T254
Test name
Test status
Simulation time 40623580755 ps
CPU time 16.77 seconds
Started Jul 30 06:44:14 PM PDT 24
Finished Jul 30 06:44:31 PM PDT 24
Peak memory 196896 kb
Host smart-7d02d847-ea8c-4c9d-b801-dab2bed2830d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606441613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1606441613
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.2596316030
Short name T12
Test name
Test status
Simulation time 455692522 ps
CPU time 0.74 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:21 PM PDT 24
Peak memory 191880 kb
Host smart-0230ba73-d5ba-4243-855a-d8f46dc9ecd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596316030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.2596316030
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.2499138690
Short name T210
Test name
Test status
Simulation time 59706665388 ps
CPU time 39.14 seconds
Started Jul 30 06:44:13 PM PDT 24
Finished Jul 30 06:44:52 PM PDT 24
Peak memory 191920 kb
Host smart-1455b87b-5ef1-49d4-8fa3-5245d3d2502e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499138690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2499138690
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.1389880203
Short name T219
Test name
Test status
Simulation time 574184033 ps
CPU time 0.7 seconds
Started Jul 30 06:44:20 PM PDT 24
Finished Jul 30 06:44:22 PM PDT 24
Peak memory 191880 kb
Host smart-e033f660-39b6-43bc-bf3e-208a776ae4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389880203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1389880203
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1169483470
Short name T50
Test name
Test status
Simulation time 23640768457 ps
CPU time 37.5 seconds
Started Jul 30 06:44:23 PM PDT 24
Finished Jul 30 06:45:03 PM PDT 24
Peak memory 191928 kb
Host smart-32a13e1c-bc95-4719-b485-a5a52923dc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169483470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1169483470
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.2588865533
Short name T257
Test name
Test status
Simulation time 578935613 ps
CPU time 0.76 seconds
Started Jul 30 06:44:13 PM PDT 24
Finished Jul 30 06:44:14 PM PDT 24
Peak memory 191816 kb
Host smart-18aa95cf-a853-419f-8833-a998b24e9403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588865533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.2588865533
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.4139351116
Short name T46
Test name
Test status
Simulation time 2056686851 ps
CPU time 3.27 seconds
Started Jul 30 06:43:25 PM PDT 24
Finished Jul 30 06:43:29 PM PDT 24
Peak memory 191808 kb
Host smart-580f34d8-98b0-43c9-8c29-3ab9211f1e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139351116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.4139351116
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.1982630192
Short name T247
Test name
Test status
Simulation time 464046061 ps
CPU time 1.3 seconds
Started Jul 30 06:43:28 PM PDT 24
Finished Jul 30 06:43:29 PM PDT 24
Peak memory 191824 kb
Host smart-f3fdaa69-203c-439a-a348-95b3d7dadb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982630192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.1982630192
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_jump.1093045243
Short name T170
Test name
Test status
Simulation time 508692786 ps
CPU time 1.23 seconds
Started Jul 30 06:43:41 PM PDT 24
Finished Jul 30 06:43:43 PM PDT 24
Peak memory 196608 kb
Host smart-a3188e87-e2b1-40bb-ac47-e2fc210304f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093045243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.1093045243
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3120783982
Short name T245
Test name
Test status
Simulation time 39574617877 ps
CPU time 13.22 seconds
Started Jul 30 06:43:25 PM PDT 24
Finished Jul 30 06:43:38 PM PDT 24
Peak memory 196888 kb
Host smart-6a51045b-b99b-4b35-99b3-a77195f4ff19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120783982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3120783982
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.4006196003
Short name T268
Test name
Test status
Simulation time 470736359 ps
CPU time 1.26 seconds
Started Jul 30 06:43:35 PM PDT 24
Finished Jul 30 06:43:37 PM PDT 24
Peak memory 196680 kb
Host smart-bba77748-d9a3-4e40-bd4a-1d126194cb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006196003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.4006196003
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3462727110
Short name T38
Test name
Test status
Simulation time 26434149109 ps
CPU time 4.97 seconds
Started Jul 30 06:43:31 PM PDT 24
Finished Jul 30 06:43:36 PM PDT 24
Peak memory 196740 kb
Host smart-c6548237-c568-4972-b0ec-f91ebc12c4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462727110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3462727110
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3024134640
Short name T10
Test name
Test status
Simulation time 581288741 ps
CPU time 1.41 seconds
Started Jul 30 06:43:36 PM PDT 24
Finished Jul 30 06:43:38 PM PDT 24
Peak memory 191824 kb
Host smart-3d85b041-b382-43e0-9334-3cd37a4c9ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024134640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3024134640
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2077303729
Short name T269
Test name
Test status
Simulation time 54811625944 ps
CPU time 77.24 seconds
Started Jul 30 06:43:37 PM PDT 24
Finished Jul 30 06:44:54 PM PDT 24
Peak memory 191892 kb
Host smart-a7f1feb9-b516-43c8-8171-5841d618b59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077303729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2077303729
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.2276377884
Short name T29
Test name
Test status
Simulation time 420709745 ps
CPU time 0.87 seconds
Started Jul 30 06:43:32 PM PDT 24
Finished Jul 30 06:43:38 PM PDT 24
Peak memory 191808 kb
Host smart-829b2f75-710d-4732-87ff-bb4a66fcead9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276377884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.2276377884
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.2065581264
Short name T212
Test name
Test status
Simulation time 1433612171 ps
CPU time 2.46 seconds
Started Jul 30 06:43:26 PM PDT 24
Finished Jul 30 06:43:29 PM PDT 24
Peak memory 196536 kb
Host smart-273191b1-4182-459c-be68-8d2119cb6510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065581264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2065581264
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.41984165
Short name T25
Test name
Test status
Simulation time 559827786 ps
CPU time 1.29 seconds
Started Jul 30 06:44:35 PM PDT 24
Finished Jul 30 06:44:36 PM PDT 24
Peak memory 191548 kb
Host smart-88091fb3-61ad-4984-92e7-6deed8840305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41984165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.41984165
Directory /workspace/9.aon_timer_smoke/latest
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