Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	306436	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	3765040	1		T1	11		T2	11		T3	15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1000558	1		T1	1		T2	1		T3	1
values[0x0]	1439949	1		T1	10		T2	8		T3	7
values[0x1]	1630969	1		T1	7		T2	10		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	137725	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	3933751	1		T1	12		T2	12		T3	15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15158	1		T4	8		T9	417		T10	1
valid_sources[0x01]	17057	1		T9	303		T12	597		T13	201
valid_sources[0x02]	15358	1		T8	1		T9	384		T10	2
valid_sources[0x03]	16001	1		T8	1		T9	426		T11	3
valid_sources[0x04]	15539	1		T9	456		T12	297		T13	156
valid_sources[0x05]	16828	1		T4	5		T9	365		T12	623
valid_sources[0x06]	14944	1		T9	367		T12	312		T13	197
valid_sources[0x07]	17489	1		T9	379		T10	1		T12	316
valid_sources[0x08]	15879	1		T9	340		T10	1		T12	275
valid_sources[0x09]	15960	1		T9	395		T12	841		T13	178
valid_sources[0x0a]	13895	1		T8	4		T9	379		T10	5
valid_sources[0x0b]	15473	1		T9	436		T12	32		T13	213
valid_sources[0x0c]	14376	1		T9	352		T10	4		T12	144
valid_sources[0x0d]	13825	1		T9	368		T10	4		T12	266
valid_sources[0x0e]	15050	1		T9	371		T10	1		T12	192
valid_sources[0x0f]	15096	1		T9	358		T10	2		T12	277
valid_sources[0x10]	15587	1		T2	15		T9	413		T12	234
valid_sources[0x11]	16294	1		T9	411		T10	4		T12	487
valid_sources[0x12]	14389	1		T7	1		T8	2		T9	387
valid_sources[0x13]	15170	1		T9	393		T12	163		T13	186
valid_sources[0x14]	14419	1		T9	357		T12	241		T13	185
valid_sources[0x15]	16034	1		T9	330		T12	9		T13	166
valid_sources[0x16]	15926	1		T9	415		T10	2		T12	16
valid_sources[0x17]	14929	1		T4	2		T5	320		T9	360
valid_sources[0x18]	15520	1		T4	2		T9	365		T12	176
valid_sources[0x19]	15298	1		T1	3		T8	18		T9	329
valid_sources[0x1a]	14821	1		T8	1		T9	367		T11	1
valid_sources[0x1b]	17007	1		T8	4		T9	424		T12	80
valid_sources[0x1c]	17113	1		T4	5		T9	431		T12	361
valid_sources[0x1d]	15206	1		T9	435		T11	2		T12	303
valid_sources[0x1e]	13874	1		T9	404		T12	78		T13	186
valid_sources[0x1f]	18135	1		T9	379		T12	94		T13	181
valid_sources[0x20]	16525	1		T4	4		T9	404		T10	4
valid_sources[0x21]	14607	1		T4	8		T8	4		T9	391
valid_sources[0x22]	16290	1		T4	3		T8	1		T9	400
valid_sources[0x23]	15347	1		T9	368		T12	359		T13	178
valid_sources[0x24]	15793	1		T9	413		T10	3		T12	13
valid_sources[0x25]	15930	1		T4	1		T8	2		T9	385
valid_sources[0x26]	17407	1		T9	428		T12	225		T13	187
valid_sources[0x27]	14909	1		T4	8		T9	347		T10	3
valid_sources[0x28]	17126	1		T9	401		T10	2		T12	94
valid_sources[0x29]	18570	1		T9	395		T10	1		T12	187
valid_sources[0x2a]	14183	1		T4	1		T8	2		T9	443
valid_sources[0x2b]	14880	1		T4	1		T9	424		T10	4
valid_sources[0x2c]	15722	1		T8	15		T9	392		T10	2
valid_sources[0x2d]	16074	1		T4	1		T9	394		T10	5
valid_sources[0x2e]	16275	1		T9	391		T12	30		T13	180
valid_sources[0x2f]	14632	1		T8	1		T9	479		T12	324
valid_sources[0x30]	15674	1		T9	410		T12	333		T13	186
valid_sources[0x31]	16069	1		T4	2		T9	387		T10	1
valid_sources[0x32]	18533	1		T4	2		T9	363		T10	4
valid_sources[0x33]	16588	1		T9	425		T11	1		T12	10
valid_sources[0x34]	16852	1		T8	5		T9	356		T12	322
valid_sources[0x35]	15301	1		T9	411		T10	2		T12	127
valid_sources[0x36]	15992	1		T9	362		T12	24		T13	173
valid_sources[0x37]	16653	1		T4	1		T9	365		T12	408
valid_sources[0x38]	15282	1		T8	4		T9	398		T12	258
valid_sources[0x39]	15909	1		T6	9		T9	370		T12	105
valid_sources[0x3a]	15703	1		T9	400		T10	8		T12	11
valid_sources[0x3b]	15687	1		T9	365		T12	337		T13	181
valid_sources[0x3c]	15794	1		T9	348		T12	282		T13	213
valid_sources[0x3d]	15923	1		T4	6		T9	422		T12	56
valid_sources[0x3e]	16378	1		T4	6		T9	370		T12	467
valid_sources[0x3f]	15215	1		T4	9		T8	6		T9	372
valid_sources[0x40]	16622	1		T9	468		T12	78		T13	172
valid_sources[0x41]	14112	1		T3	10		T9	372		T10	2
valid_sources[0x42]	15741	1		T9	394		T10	3		T12	219
valid_sources[0x43]	16621	1		T8	3		T9	342		T10	3
valid_sources[0x44]	15456	1		T9	360		T12	420		T13	208
valid_sources[0x45]	14999	1		T9	356		T12	159		T13	187
valid_sources[0x46]	15595	1		T9	399		T10	2		T12	33
valid_sources[0x47]	16478	1		T7	13		T8	9		T9	328
valid_sources[0x48]	15832	1		T9	401		T10	1		T12	260
valid_sources[0x49]	17596	1		T8	3		T9	375		T12	313
valid_sources[0x4a]	16960	1		T1	1		T9	410		T10	1
valid_sources[0x4b]	14914	1		T9	359		T10	2		T12	193
valid_sources[0x4c]	16778	1		T9	417		T10	4		T12	484
valid_sources[0x4d]	16755	1		T8	15		T9	363		T12	9
valid_sources[0x4e]	15836	1		T8	13		T9	389		T10	1
valid_sources[0x4f]	15263	1		T9	300		T12	579		T13	214
valid_sources[0x50]	13351	1		T4	8		T9	492		T10	3
valid_sources[0x51]	14357	1		T8	1		T9	412		T12	11
valid_sources[0x52]	18812	1		T9	404		T12	266		T13	184
valid_sources[0x53]	18044	1		T4	2		T9	428		T12	191
valid_sources[0x54]	16090	1		T9	444		T12	223		T13	160
valid_sources[0x55]	14617	1		T1	2		T9	372		T10	1
valid_sources[0x56]	16459	1		T9	404		T10	1		T12	209
valid_sources[0x57]	15840	1		T9	435		T10	1		T12	92
valid_sources[0x58]	16540	1		T9	369		T12	270		T13	194
valid_sources[0x59]	15686	1		T4	4		T9	352		T10	1
valid_sources[0x5a]	16840	1		T4	2		T9	376		T12	81
valid_sources[0x5b]	16012	1		T9	396		T12	345		T13	189
valid_sources[0x5c]	15321	1		T9	368		T12	77		T13	194
valid_sources[0x5d]	15511	1		T9	368		T10	3		T12	15
valid_sources[0x5e]	17171	1		T9	357		T10	1		T12	354
valid_sources[0x5f]	16378	1		T8	6		T9	410		T10	1
valid_sources[0x60]	15111	1		T8	14		T9	471		T10	3
valid_sources[0x61]	16375	1		T4	2		T9	379		T10	1
valid_sources[0x62]	14768	1		T9	364		T10	3		T12	115
valid_sources[0x63]	16007	1		T4	1		T9	373		T12	127
valid_sources[0x64]	16959	1		T1	1		T2	2		T8	6
valid_sources[0x65]	16089	1		T6	6		T9	431		T10	1
valid_sources[0x66]	15349	1		T4	7		T6	3		T8	2
valid_sources[0x67]	14943	1		T8	1		T9	373		T12	174
valid_sources[0x68]	16467	1		T8	6		T9	402		T10	4
valid_sources[0x69]	15050	1		T1	4		T8	3		T9	385
valid_sources[0x6a]	15688	1		T8	5		T9	461		T12	28
valid_sources[0x6b]	14671	1		T4	2		T9	413		T12	326
valid_sources[0x6c]	16599	1		T9	351		T12	693		T13	169
valid_sources[0x6d]	16282	1		T9	430		T12	15		T13	181
valid_sources[0x6e]	15261	1		T9	359		T12	20		T13	148
valid_sources[0x6f]	16565	1		T9	368		T12	84		T13	182
valid_sources[0x70]	16557	1		T4	12		T8	5		T9	407
valid_sources[0x71]	17335	1		T4	2		T9	388		T12	85
valid_sources[0x72]	15636	1		T9	351		T11	1		T12	691
valid_sources[0x73]	15742	1		T9	461		T10	4		T12	5
valid_sources[0x74]	14819	1		T9	395		T12	158		T13	187
valid_sources[0x75]	15317	1		T9	391		T10	4		T12	301
valid_sources[0x76]	16403	1		T9	466		T12	328		T13	188
valid_sources[0x77]	15570	1		T9	355		T10	2		T11	1
valid_sources[0x78]	16523	1		T9	342		T10	2		T12	87
valid_sources[0x79]	17026	1		T9	371		T10	1		T12	76
valid_sources[0x7a]	16186	1		T9	452		T10	1		T12	3
valid_sources[0x7b]	15152	1		T9	384		T10	2		T12	27
valid_sources[0x7c]	16803	1		T9	393		T12	18		T13	204
valid_sources[0x7d]	15735	1		T9	395		T10	3		T12	85
valid_sources[0x7e]	18841	1		T9	385		T11	3		T12	1234
valid_sources[0x7f]	14988	1		T9	350		T10	2		T12	353
valid_sources[0x80]	15858	1		T4	7		T9	373		T10	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

937585

1

T3

1

T4

31

T5

15

values[0x0]

all_enables

biggest_size

1413805

1

T1

7

T2

5

T3

5

values[0x1]

all_enables

biggest_size

1413650

1

T1

4

T2

6

T3

9