Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	794569891	4430275	0	0
wdog_bark_thold_rd_A	794569891	147313	0	0
wdog_bite_thold_rd_A	794569891	129571	0	0
wdog_ctrl_rd_A	794569891	129224	0	0
wdog_regwen_rd_A	794569891	149221	0	0
wkup_ctrl_rd_A	794569891	128232	0	0
wkup_thold_hi_rd_A	794569891	148328	0	0
wkup_thold_lo_rd_A	794569891	130681	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794569891	4430275	0	0
T9	464582	104408	0	0
T10	135479	0	0	0
T11	11047	0	0	0
T12	185654	62698	0	0
T13	185277	49102	0	0
T19	0	102502	0	0
T27	0	179284	0	0
T28	40584	0	0	0
T29	0	33906	0	0
T37	0	182922	0	0
T38	0	240983	0	0
T39	0	223407	0	0
T40	0	41052	0	0
T41	117437	0	0	0
T42	685807	0	0	0
T43	535850	0	0	0
T44	223368	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794569891	147313	0	0
T9	464582	10324	0	0
T10	135479	0	0	0
T11	11047	0	0	0
T12	185654	0	0	0
T13	185277	0	0	0
T28	40584	0	0	0
T29	0	3458	0	0
T40	0	2111	0	0
T41	117437	0	0	0
T42	685807	0	0	0
T43	535850	0	0	0
T44	223368	0	0	0
T49	0	19943	0	0
T53	0	7476	0	0
T88	0	11263	0	0
T89	0	3644	0	0
T90	0	14094	0	0
T91	0	9731	0	0
T92	0	1755	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794569891	129571	0	0
T9	464582	9252	0	0
T10	135479	0	0	0
T11	11047	0	0	0
T12	185654	0	0	0
T13	185277	0	0	0
T28	40584	0	0	0
T29	0	3089	0	0
T40	0	1827	0	0
T41	117437	0	0	0
T42	685807	0	0	0
T43	535850	0	0	0
T44	223368	0	0	0
T49	0	17294	0	0
T53	0	6797	0	0
T88	0	10204	0	0
T89	0	3061	0	0
T90	0	11886	0	0
T91	0	8692	0	0
T92	0	1582	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794569891	129224	0	0
T9	464582	8944	0	0
T10	135479	0	0	0
T11	11047	0	0	0
T12	185654	0	0	0
T13	185277	0	0	0
T28	40584	0	0	0
T29	0	3080	0	0
T40	0	1909	0	0
T41	117437	0	0	0
T42	685807	0	0	0
T43	535850	0	0	0
T44	223368	0	0	0
T49	0	17516	0	0
T53	0	6565	0	0
T88	0	10246	0	0
T89	0	2916	0	0
T90	0	12206	0	0
T91	0	8545	0	0
T92	0	1713	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794569891	149221	0	0
T9	464582	10471	0	0
T10	135479	0	0	0
T11	11047	0	0	0
T12	185654	0	0	0
T13	185277	0	0	0
T28	40584	0	0	0
T29	0	3496	0	0
T40	0	2297	0	0
T41	117437	0	0	0
T42	685807	0	0	0
T43	535850	0	0	0
T44	223368	0	0	0
T49	0	19936	0	0
T53	0	7631	0	0
T88	0	12244	0	0
T89	0	3554	0	0
T90	0	14072	0	0
T91	0	9696	0	0
T92	0	1787	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794569891	128232	0	0
T9	464582	8983	0	0
T10	135479	0	0	0
T11	11047	0	0	0
T12	185654	0	0	0
T13	185277	0	0	0
T28	40584	0	0	0
T29	0	3040	0	0
T40	0	1903	0	0
T41	117437	0	0	0
T42	685807	0	0	0
T43	535850	0	0	0
T44	223368	0	0	0
T49	0	16921	0	0
T53	0	6490	0	0
T88	0	10620	0	0
T89	0	2781	0	0
T90	0	11799	0	0
T91	0	7912	0	0
T92	0	1669	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794569891	148328	0	0
T9	464582	10730	0	0
T10	135479	0	0	0
T11	11047	0	0	0
T12	185654	0	0	0
T13	185277	0	0	0
T28	40584	0	0	0
T29	0	3680	0	0
T40	0	2353	0	0
T41	117437	0	0	0
T42	685807	0	0	0
T43	535850	0	0	0
T44	223368	0	0	0
T49	0	20031	0	0
T53	0	7355	0	0
T88	0	11762	0	0
T89	0	3628	0	0
T90	0	14104	0	0
T91	0	9568	0	0
T92	0	1842	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794569891	130681	0	0
T9	464582	9292	0	0
T10	135479	0	0	0
T11	11047	0	0	0
T12	185654	0	0	0
T13	185277	0	0	0
T28	40584	0	0	0
T29	0	2961	0	0
T40	0	1743	0	0
T41	117437	0	0	0
T42	685807	0	0	0
T43	535850	0	0	0
T44	223368	0	0	0
T49	0	17733	0	0
T53	0	6747	0	0
T88	0	10472	0	0
T89	0	3085	0	0
T90	0	12090	0	0
T91	0	8655	0	0
T92	0	1780	0	0