Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	349239	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4226331	1		T1	15		T2	13		T3	14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1124740	1		T1	1		T2	1		T3	1
values[0x0]	1613886	1		T1	6		T2	9		T3	10
values[0x1]	1836944	1		T1	13		T2	8		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	155716	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4419854	1		T1	15		T2	14		T3	14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19775	1		T4	2		T13	619		T14	625
valid_sources[0x01]	19363	1		T4	2		T5	4		T12	2
valid_sources[0x02]	17297	1		T13	544		T14	626		T16	441
valid_sources[0x03]	18251	1		T5	7		T13	561		T21	3
valid_sources[0x04]	18445	1		T5	1		T13	567		T14	590
valid_sources[0x05]	18454	1		T4	1		T5	4		T12	1
valid_sources[0x06]	17712	1		T3	1		T4	3		T13	567
valid_sources[0x07]	16678	1		T4	1		T13	538		T14	637
valid_sources[0x08]	18756	1		T4	3		T13	575		T14	571
valid_sources[0x09]	19249	1		T10	7		T13	555		T14	615
valid_sources[0x0a]	18558	1		T6	1		T13	560		T22	1
valid_sources[0x0b]	17997	1		T4	1		T13	588		T14	574
valid_sources[0x0c]	18109	1		T13	550		T14	591		T16	269
valid_sources[0x0d]	17285	1		T4	1		T13	557		T14	588
valid_sources[0x0e]	19629	1		T5	4		T7	1		T13	547
valid_sources[0x0f]	18836	1		T5	3		T13	514		T14	596
valid_sources[0x10]	17431	1		T4	2		T5	5		T13	574
valid_sources[0x11]	17235	1		T5	4		T13	569		T21	19
valid_sources[0x12]	16914	1		T4	1		T5	1		T13	580
valid_sources[0x13]	18636	1		T7	1		T13	559		T14	641
valid_sources[0x14]	18931	1		T4	2		T9	2		T12	2
valid_sources[0x15]	16777	1		T9	1		T12	1		T13	508
valid_sources[0x16]	17917	1		T4	1		T13	547		T14	587
valid_sources[0x17]	17355	1		T4	1		T5	6		T7	1
valid_sources[0x18]	18273	1		T4	1		T13	538		T14	659
valid_sources[0x19]	20320	1		T5	4		T7	1		T13	529
valid_sources[0x1a]	17963	1		T4	1		T13	574		T14	565
valid_sources[0x1b]	18453	1		T4	2		T13	511		T14	567
valid_sources[0x1c]	17787	1		T4	1		T13	582		T14	572
valid_sources[0x1d]	18889	1		T4	2		T5	1		T13	563
valid_sources[0x1e]	19378	1		T5	1		T13	545		T14	650
valid_sources[0x1f]	17960	1		T5	1		T13	543		T14	601
valid_sources[0x20]	18564	1		T5	2		T13	569		T14	615
valid_sources[0x21]	17610	1		T4	3		T13	541		T14	594
valid_sources[0x22]	18501	1		T13	533		T14	599		T16	284
valid_sources[0x23]	18055	1		T13	562		T14	672		T16	396
valid_sources[0x24]	17803	1		T4	1		T5	3		T12	1
valid_sources[0x25]	17696	1		T4	1		T6	1		T13	533
valid_sources[0x26]	18876	1		T4	2		T5	1		T13	530
valid_sources[0x27]	18605	1		T4	1		T13	599		T14	623
valid_sources[0x28]	17314	1		T5	8		T13	516		T14	609
valid_sources[0x29]	18082	1		T4	1		T9	1		T13	574
valid_sources[0x2a]	17776	1		T4	2		T9	3		T12	1
valid_sources[0x2b]	17942	1		T4	1		T5	7		T13	570
valid_sources[0x2c]	17516	1		T4	1		T5	1		T13	505
valid_sources[0x2d]	17482	1		T4	1		T6	1		T13	548
valid_sources[0x2e]	16683	1		T6	1		T13	545		T14	609
valid_sources[0x2f]	17582	1		T4	1		T5	1		T13	550
valid_sources[0x30]	17116	1		T4	1		T5	1		T12	1
valid_sources[0x31]	17158	1		T5	1		T13	511		T14	612
valid_sources[0x32]	17383	1		T4	3		T13	519		T14	585
valid_sources[0x33]	17122	1		T13	541		T14	608		T16	193
valid_sources[0x34]	17644	1		T4	4		T5	1		T13	541
valid_sources[0x35]	19258	1		T4	1		T13	542		T14	625
valid_sources[0x36]	17990	1		T5	3		T13	500		T14	637
valid_sources[0x37]	17288	1		T4	5		T5	15		T13	573
valid_sources[0x38]	17499	1		T5	3		T13	535		T14	604
valid_sources[0x39]	17095	1		T3	1		T5	2		T13	529
valid_sources[0x3a]	17937	1		T5	7		T13	551		T14	634
valid_sources[0x3b]	19318	1		T5	2		T7	1		T12	1
valid_sources[0x3c]	17170	1		T4	4		T5	2		T13	493
valid_sources[0x3d]	17968	1		T5	1		T13	567		T14	647
valid_sources[0x3e]	16568	1		T13	548		T14	595		T16	285
valid_sources[0x3f]	18970	1		T4	2		T13	556		T14	591
valid_sources[0x40]	18055	1		T2	18		T4	3		T5	1
valid_sources[0x41]	16523	1		T13	556		T14	583		T16	217
valid_sources[0x42]	17656	1		T4	1		T13	585		T22	1
valid_sources[0x43]	16797	1		T12	1		T13	533		T14	562
valid_sources[0x44]	17925	1		T13	608		T14	652		T16	200
valid_sources[0x45]	17247	1		T4	1		T13	573		T14	560
valid_sources[0x46]	17584	1		T13	512		T14	631		T16	224
valid_sources[0x47]	18715	1		T5	2		T13	538		T14	593
valid_sources[0x48]	16574	1		T13	555		T15	13		T14	645
valid_sources[0x49]	17717	1		T4	2		T13	530		T14	518
valid_sources[0x4a]	17314	1		T4	1		T13	497		T14	602
valid_sources[0x4b]	17394	1		T5	7		T10	2		T13	579
valid_sources[0x4c]	17423	1		T4	1		T5	1		T10	3
valid_sources[0x4d]	17056	1		T4	1		T7	1		T13	504
valid_sources[0x4e]	17501	1		T5	1		T13	517		T14	651
valid_sources[0x4f]	19123	1		T4	1		T5	6		T13	575
valid_sources[0x50]	16642	1		T5	3		T13	516		T14	594
valid_sources[0x51]	16979	1		T6	1		T13	570		T14	594
valid_sources[0x52]	20111	1		T5	4		T13	523		T14	563
valid_sources[0x53]	18642	1		T13	590		T14	569		T16	261
valid_sources[0x54]	17526	1		T4	3		T13	541		T22	1
valid_sources[0x55]	18821	1		T3	1		T4	1		T13	571
valid_sources[0x56]	17373	1		T4	2		T5	1		T13	541
valid_sources[0x57]	18733	1		T13	565		T14	622		T16	340
valid_sources[0x58]	17560	1		T4	5		T5	7		T13	565
valid_sources[0x59]	18252	1		T4	1		T7	2		T13	504
valid_sources[0x5a]	17914	1		T4	1		T5	6		T13	552
valid_sources[0x5b]	17777	1		T3	1		T13	557		T14	620
valid_sources[0x5c]	17912	1		T4	4		T10	2		T13	546
valid_sources[0x5d]	18073	1		T5	3		T13	539		T14	585
valid_sources[0x5e]	18679	1		T3	1		T4	2		T5	3
valid_sources[0x5f]	18025	1		T5	3		T13	534		T14	572
valid_sources[0x60]	17635	1		T4	3		T13	568		T14	578
valid_sources[0x61]	16631	1		T5	5		T13	567		T14	561
valid_sources[0x62]	18007	1		T3	1		T4	1		T13	555
valid_sources[0x63]	17009	1		T10	6		T13	586		T14	630
valid_sources[0x64]	17801	1		T5	5		T13	563		T14	618
valid_sources[0x65]	17434	1		T13	549		T14	616		T16	237
valid_sources[0x66]	17578	1		T4	1		T5	1		T6	1
valid_sources[0x67]	16088	1		T4	1		T13	546		T14	597
valid_sources[0x68]	19624	1		T5	3		T13	566		T14	582
valid_sources[0x69]	19342	1		T4	5		T5	2		T13	562
valid_sources[0x6a]	19459	1		T13	568		T14	651		T16	217
valid_sources[0x6b]	17307	1		T4	1		T13	585		T14	584
valid_sources[0x6c]	18595	1		T4	1		T13	537		T14	638
valid_sources[0x6d]	17660	1		T3	1		T4	1		T5	1
valid_sources[0x6e]	17095	1		T4	2		T13	526		T14	620
valid_sources[0x6f]	16706	1		T9	1		T13	593		T14	617
valid_sources[0x70]	18680	1		T4	2		T5	6		T13	548
valid_sources[0x71]	18230	1		T4	4		T5	1		T13	590
valid_sources[0x72]	17292	1		T4	4		T13	561		T14	624
valid_sources[0x73]	18314	1		T4	2		T13	559		T14	621
valid_sources[0x74]	19232	1		T3	1		T5	1		T13	556
valid_sources[0x75]	19044	1		T3	1		T4	2		T13	526
valid_sources[0x76]	18953	1		T4	1		T13	569		T14	628
valid_sources[0x77]	18260	1		T13	563		T14	586		T16	150
valid_sources[0x78]	17337	1		T4	2		T13	608		T14	583
valid_sources[0x79]	17895	1		T4	1		T13	537		T14	591
valid_sources[0x7a]	17338	1		T13	547		T14	587		T16	332
valid_sources[0x7b]	17864	1		T13	547		T14	698		T16	149
valid_sources[0x7c]	18524	1		T4	4		T6	1		T13	576
valid_sources[0x7d]	17348	1		T5	3		T6	1		T13	554
valid_sources[0x7e]	17045	1		T4	1		T5	4		T13	564
valid_sources[0x7f]	17242	1		T4	1		T5	5		T13	525
valid_sources[0x80]	16900	1		T4	1		T5	3		T13	568

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1053707

1

T1

1

T2

1

T4

17

values[0x0]

all_enables

biggest_size

1584729

1

T1

5

T2

7

T3

7

values[0x1]

all_enables

biggest_size

1587895

1

T1

9

T2

5

T3

7