Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	732269054	5061126	0	0
wdog_bark_thold_rd_A	732269054	127243	0	0
wdog_bite_thold_rd_A	732269054	110849	0	0
wdog_ctrl_rd_A	732269054	112931	0	0
wdog_regwen_rd_A	732269054	128854	0	0
wkup_ctrl_rd_A	732269054	111949	0	0
wkup_thold_hi_rd_A	732269054	128159	0	0
wkup_thold_lo_rd_A	732269054	112134	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732269054	5061126	0	0
T13	807150	147562	0	0
T14	735120	163849	0	0
T15	42689	0	0	0
T16	350723	95811	0	0
T21	27077	0	0	0
T22	9434	0	0	0
T30	0	133369	0	0
T31	0	66809	0	0
T32	0	26206	0	0
T33	0	76872	0	0
T34	0	76191	0	0
T35	0	169687	0	0
T36	0	44031	0	0
T37	27803	0	0	0
T38	42977	0	0	0
T39	276001	0	0	0
T40	43171	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732269054	127243	0	0
T13	807150	15508	0	0
T14	735120	16674	0	0
T15	42689	0	0	0
T16	350723	0	0	0
T21	27077	0	0	0
T22	9434	0	0	0
T30	0	12844	0	0
T37	27803	0	0	0
T38	42977	0	0	0
T39	276001	0	0	0
T40	43171	0	0	0
T98	0	9412	0	0
T102	0	6734	0	0
T105	0	4810	0	0
T106	0	2105	0	0
T107	0	8255	0	0
T108	0	2340	0	0
T109	0	8161	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732269054	110849	0	0
T13	807150	13280	0	0
T14	735120	14518	0	0
T15	42689	0	0	0
T16	350723	0	0	0
T21	27077	0	0	0
T22	9434	0	0	0
T30	0	10519	0	0
T37	27803	0	0	0
T38	42977	0	0	0
T39	276001	0	0	0
T40	43171	0	0	0
T98	0	8191	0	0
T102	0	5926	0	0
T105	0	4227	0	0
T106	0	1809	0	0
T107	0	6981	0	0
T108	0	1971	0	0
T109	0	7401	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732269054	112931	0	0
T13	807150	13286	0	0
T14	735120	14946	0	0
T15	42689	0	0	0
T16	350723	0	0	0
T21	27077	0	0	0
T22	9434	0	0	0
T30	0	11070	0	0
T37	27803	0	0	0
T38	42977	0	0	0
T39	276001	0	0	0
T40	43171	0	0	0
T98	0	8652	0	0
T102	0	5884	0	0
T105	0	4236	0	0
T106	0	1884	0	0
T107	0	7074	0	0
T108	0	2234	0	0
T109	0	7020	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732269054	128854	0	0
T13	807150	15563	0	0
T14	735120	16865	0	0
T15	42689	0	0	0
T16	350723	0	0	0
T21	27077	0	0	0
T22	9434	0	0	0
T30	0	12318	0	0
T37	27803	0	0	0
T38	42977	0	0	0
T39	276001	0	0	0
T40	43171	0	0	0
T98	0	9441	0	0
T102	0	6493	0	0
T105	0	5269	0	0
T106	0	2169	0	0
T107	0	8203	0	0
T108	0	2517	0	0
T109	0	8092	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732269054	111949	0	0
T13	807150	13071	0	0
T14	735120	13670	0	0
T15	42689	0	0	0
T16	350723	0	0	0
T21	27077	0	0	0
T22	9434	0	0	0
T30	0	11418	0	0
T37	27803	0	0	0
T38	42977	0	0	0
T39	276001	0	0	0
T40	43171	0	0	0
T98	0	8093	0	0
T102	0	5958	0	0
T105	0	4638	0	0
T106	0	2016	0	0
T107	0	6937	0	0
T108	0	2322	0	0
T109	0	7011	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732269054	128159	0	0
T13	807150	15591	0	0
T14	735120	16373	0	0
T15	42689	0	0	0
T16	350723	0	0	0
T21	27077	0	0	0
T22	9434	0	0	0
T30	0	12997	0	0
T37	27803	0	0	0
T38	42977	0	0	0
T39	276001	0	0	0
T40	43171	0	0	0
T98	0	9658	0	0
T102	0	6601	0	0
T105	0	4984	0	0
T106	0	2249	0	0
T107	0	7941	0	0
T108	0	2706	0	0
T109	0	8267	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732269054	112134	0	0
T13	807150	13322	0	0
T14	735120	14724	0	0
T15	42689	0	0	0
T16	350723	0	0	0
T21	27077	0	0	0
T22	9434	0	0	0
T30	0	11544	0	0
T37	27803	0	0	0
T38	42977	0	0	0
T39	276001	0	0	0
T40	43171	0	0	0
T98	0	8376	0	0
T102	0	5528	0	0
T105	0	4311	0	0
T106	0	1891	0	0
T107	0	7097	0	0
T108	0	2297	0	0
T109	0	6902	0	0