Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	410523	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	5066334	1		T1	53271		T2	13		T3	227

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1346492	1		T1	14184		T2	1		T3	61
values[0x0]	1935355	1		T1	20214		T2	6		T3	145
values[0x1]	2195010	1		T1	23297		T2	11		T3	147

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	181940	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	5294917	1		T1	55744		T2	15		T3	253

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	20469	1		T1	128		T8	4		T43	1
valid_sources[0x01]	21147	1		T1	107		T8	3		T9	1
valid_sources[0x02]	22196	1		T1	186		T7	1		T9	1
valid_sources[0x03]	22033	1		T1	117		T31	2		T11	896
valid_sources[0x04]	20808	1		T1	107		T9	1		T31	3
valid_sources[0x05]	21893	1		T1	249		T6	1		T31	1
valid_sources[0x06]	22504	1		T1	25		T8	2		T11	571
valid_sources[0x07]	21658	1		T1	374		T4	1		T8	3
valid_sources[0x08]	20829	1		T1	424		T8	2		T9	1
valid_sources[0x09]	20598	1		T1	152		T7	1		T8	2
valid_sources[0x0a]	20653	1		T1	202		T3	2		T6	1
valid_sources[0x0b]	22884	1		T1	366		T4	1		T8	3
valid_sources[0x0c]	22502	1		T1	148		T3	7		T9	1
valid_sources[0x0d]	20675	1		T1	459		T9	2		T11	390
valid_sources[0x0e]	20872	1		T1	151		T11	182		T12	631
valid_sources[0x0f]	21687	1		T1	192		T9	1		T11	635
valid_sources[0x10]	23787	1		T1	244		T8	6		T31	4
valid_sources[0x11]	19712	1		T1	216		T8	7		T10	1
valid_sources[0x12]	22511	1		T1	146		T11	248		T12	668
valid_sources[0x13]	22099	1		T1	835		T11	651		T12	679
valid_sources[0x14]	21071	1		T1	387		T3	4		T8	2
valid_sources[0x15]	20074	1		T1	293		T3	4		T9	2
valid_sources[0x16]	20829	1		T1	287		T8	5		T9	1
valid_sources[0x17]	20441	1		T1	174		T9	2		T11	548
valid_sources[0x18]	21837	1		T1	423		T8	4		T9	3
valid_sources[0x19]	20068	1		T1	155		T9	4		T11	542
valid_sources[0x1a]	19375	1		T1	23		T3	3		T8	8
valid_sources[0x1b]	21109	1		T1	20		T10	1		T31	7
valid_sources[0x1c]	20357	1		T1	12		T8	3		T9	1
valid_sources[0x1d]	22239	1		T1	379		T7	1		T9	1
valid_sources[0x1e]	21948	1		T1	93		T5	5		T7	1
valid_sources[0x1f]	20500	1		T1	535		T3	3		T8	4
valid_sources[0x20]	23369	1		T1	381		T5	1		T9	1
valid_sources[0x21]	22214	1		T1	179		T3	1		T8	2
valid_sources[0x22]	20860	1		T1	227		T8	4		T9	4
valid_sources[0x23]	20780	1		T1	287		T8	2		T31	5
valid_sources[0x24]	21685	1		T1	167		T11	529		T12	667
valid_sources[0x25]	22235	1		T1	233		T9	1		T31	1
valid_sources[0x26]	21114	1		T1	144		T8	5		T31	6
valid_sources[0x27]	21593	1		T1	307		T3	5		T9	1
valid_sources[0x28]	20502	1		T1	79		T2	6		T9	2
valid_sources[0x29]	20969	1		T1	30		T3	7		T8	4
valid_sources[0x2a]	20874	1		T1	115		T11	624		T46	1
valid_sources[0x2b]	21896	1		T1	177		T3	9		T31	1
valid_sources[0x2c]	22237	1		T1	175		T3	6		T8	2
valid_sources[0x2d]	20121	1		T1	258		T8	3		T11	152
valid_sources[0x2e]	20270	1		T1	67		T8	2		T9	2
valid_sources[0x2f]	21119	1		T1	82		T8	1		T9	1
valid_sources[0x30]	20784	1		T1	68		T3	6		T8	1
valid_sources[0x31]	20901	1		T1	300		T9	1		T11	783
valid_sources[0x32]	20823	1		T1	155		T9	2		T11	468
valid_sources[0x33]	21050	1		T1	468		T6	1		T8	2
valid_sources[0x34]	21528	1		T1	78		T8	2		T9	1
valid_sources[0x35]	20493	1		T1	174		T3	6		T11	262
valid_sources[0x36]	21688	1		T1	344		T3	1		T31	1
valid_sources[0x37]	22062	1		T1	480		T3	3		T8	3
valid_sources[0x38]	21034	1		T1	65		T3	10		T4	1
valid_sources[0x39]	22329	1		T1	378		T8	5		T9	5
valid_sources[0x3a]	20862	1		T1	128		T11	584		T45	1
valid_sources[0x3b]	19960	1		T1	290		T31	1		T11	432
valid_sources[0x3c]	22063	1		T1	267		T4	1		T8	1
valid_sources[0x3d]	21347	1		T1	133		T9	1		T11	72
valid_sources[0x3e]	21370	1		T1	308		T8	1		T9	1
valid_sources[0x3f]	20464	1		T1	276		T31	2		T11	328
valid_sources[0x40]	21355	1		T1	28		T3	4		T8	6
valid_sources[0x41]	22395	1		T1	131		T8	4		T9	6
valid_sources[0x42]	22039	1		T1	333		T3	8		T11	245
valid_sources[0x43]	21528	1		T1	270		T4	1		T6	1
valid_sources[0x44]	21545	1		T1	41		T9	3		T43	4
valid_sources[0x45]	21348	1		T1	514		T8	2		T9	1
valid_sources[0x46]	22777	1		T1	438		T3	10		T9	1
valid_sources[0x47]	21902	1		T1	51		T3	3		T8	1
valid_sources[0x48]	21471	1		T1	249		T8	1		T11	356
valid_sources[0x49]	19742	1		T1	223		T4	1		T8	11
valid_sources[0x4a]	20669	1		T1	123		T5	1		T8	1
valid_sources[0x4b]	22721	1		T1	594		T9	2		T31	1
valid_sources[0x4c]	20316	1		T1	450		T8	1		T9	3
valid_sources[0x4d]	22009	1		T1	127		T9	1		T31	5
valid_sources[0x4e]	23110	1		T1	394		T9	1		T31	3
valid_sources[0x4f]	20676	1		T1	7		T9	1		T11	441
valid_sources[0x50]	19921	1		T1	304		T7	2		T8	2
valid_sources[0x51]	21177	1		T1	50		T3	8		T4	1
valid_sources[0x52]	21086	1		T1	259		T5	1		T9	4
valid_sources[0x53]	20611	1		T1	64		T8	1		T11	648
valid_sources[0x54]	22074	1		T1	420		T9	1		T11	342
valid_sources[0x55]	23039	1		T1	251		T2	4		T8	1
valid_sources[0x56]	20885	1		T1	245		T3	12		T8	5
valid_sources[0x57]	21329	1		T1	542		T31	2		T11	550
valid_sources[0x58]	22273	1		T1	491		T9	2		T11	585
valid_sources[0x59]	20477	1		T1	446		T9	1		T31	3
valid_sources[0x5a]	19640	1		T1	4		T6	1		T7	1
valid_sources[0x5b]	20141	1		T1	34		T9	1		T11	334
valid_sources[0x5c]	21863	1		T1	386		T9	3		T31	5
valid_sources[0x5d]	20809	1		T1	62		T9	3		T11	340
valid_sources[0x5e]	21098	1		T1	291		T9	1		T31	1
valid_sources[0x5f]	21580	1		T1	194		T3	12		T31	1
valid_sources[0x60]	20802	1		T1	204		T8	2		T9	2
valid_sources[0x61]	20126	1		T1	158		T9	3		T31	2
valid_sources[0x62]	22019	1		T1	18		T8	4		T31	1
valid_sources[0x63]	20509	1		T1	234		T3	3		T9	1
valid_sources[0x64]	20314	1		T1	101		T8	1		T9	2
valid_sources[0x65]	19836	1		T1	39		T8	12		T9	1
valid_sources[0x66]	23337	1		T1	22		T9	2		T11	802
valid_sources[0x67]	21319	1		T1	84		T3	19		T9	1
valid_sources[0x68]	20083	1		T1	10		T7	1		T11	362
valid_sources[0x69]	21412	1		T1	254		T8	4		T9	2
valid_sources[0x6a]	20783	1		T1	285		T11	363		T30	1
valid_sources[0x6b]	20708	1		T1	187		T9	5		T31	2
valid_sources[0x6c]	21076	1		T1	102		T4	1		T6	1
valid_sources[0x6d]	20302	1		T1	13		T8	5		T10	1
valid_sources[0x6e]	22642	1		T1	313		T11	467		T12	693
valid_sources[0x6f]	22844	1		T1	9		T8	2		T9	1
valid_sources[0x70]	21625	1		T1	19		T31	1		T11	241
valid_sources[0x71]	22493	1		T1	308		T7	1		T9	2
valid_sources[0x72]	21729	1		T1	292		T4	1		T8	2
valid_sources[0x73]	21878	1		T1	23		T31	9		T11	281
valid_sources[0x74]	20915	1		T1	204		T7	1		T11	507
valid_sources[0x75]	22196	1		T1	641		T4	1		T11	391
valid_sources[0x76]	20983	1		T1	306		T8	6		T11	476
valid_sources[0x77]	22343	1		T1	157		T5	1		T9	3
valid_sources[0x78]	20580	1		T1	148		T8	5		T9	3
valid_sources[0x79]	21438	1		T1	111		T7	1		T9	2
valid_sources[0x7a]	20371	1		T1	241		T4	1		T9	1
valid_sources[0x7b]	19947	1		T1	91		T5	1		T8	3
valid_sources[0x7c]	20876	1		T1	217		T4	1		T11	401
valid_sources[0x7d]	21306	1		T1	379		T3	1		T11	444
valid_sources[0x7e]	22326	1		T1	173		T3	5		T8	1
valid_sources[0x7f]	20608	1		T1	217		T6	1		T7	1
valid_sources[0x80]	20984	1		T1	33		T9	1		T31	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1263921

1

T1

13338

T2

1

T3

30

values[0x0]

all_enables

biggest_size

1901849

1

T1

19859

T2

6

T3

98

values[0x1]

all_enables

biggest_size

1900564

1

T1

20074

T2

6

T3

99