Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	779749985	6002876	0	0
wdog_bark_thold_rd_A	779749985	111915	0	0
wdog_bite_thold_rd_A	779749985	97379	0	0
wdog_ctrl_rd_A	779749985	97040	0	0
wdog_regwen_rd_A	779749985	112554	0	0
wkup_ctrl_rd_A	779749985	96750	0	0
wkup_thold_hi_rd_A	779749985	110396	0	0
wkup_thold_lo_rd_A	779749985	97583	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	779749985	6002876	0	0
T1	277735	64394	0	0
T2	9334	0	0	0
T3	566207	0	0	0
T4	3498	0	0	0
T5	6645	0	0	0
T6	989238	0	0	0
T7	14334	0	0	0
T8	978426	0	0	0
T9	367063	0	0	0
T10	677019	0	0	0
T11	0	131367	0	0
T12	0	192285	0	0
T18	0	61510	0	0
T24	0	80654	0	0
T29	0	163551	0	0
T39	0	34529	0	0
T40	0	58038	0	0
T41	0	153098	0	0
T42	0	161154	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	779749985	111915	0	0
T1	277735	6252	0	0
T2	9334	0	0	0
T3	566207	0	0	0
T4	3498	0	0	0
T5	6645	0	0	0
T6	989238	0	0	0
T7	14334	0	0	0
T8	978426	0	0	0
T9	367063	0	0	0
T10	677019	0	0	0
T18	0	6120	0	0
T39	0	3667	0	0
T54	0	7282	0	0
T79	0	30371	0	0
T82	0	7864	0	0
T83	0	6527	0	0
T84	0	1063	0	0
T85	0	5369	0	0
T86	0	3737	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	779749985	97379	0	0
T1	277735	5384	0	0
T2	9334	0	0	0
T3	566207	0	0	0
T4	3498	0	0	0
T5	6645	0	0	0
T6	989238	0	0	0
T7	14334	0	0	0
T8	978426	0	0	0
T9	367063	0	0	0
T10	677019	0	0	0
T18	0	5034	0	0
T39	0	2986	0	0
T54	0	6811	0	0
T79	0	25950	0	0
T82	0	7152	0	0
T83	0	5635	0	0
T84	0	871	0	0
T85	0	4675	0	0
T86	0	3250	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	779749985	97040	0	0
T1	277735	5494	0	0
T2	9334	0	0	0
T3	566207	0	0	0
T4	3498	0	0	0
T5	6645	0	0	0
T6	989238	0	0	0
T7	14334	0	0	0
T8	978426	0	0	0
T9	367063	0	0	0
T10	677019	0	0	0
T18	0	5063	0	0
T39	0	2698	0	0
T54	0	6494	0	0
T79	0	26309	0	0
T82	0	6854	0	0
T83	0	5538	0	0
T84	0	927	0	0
T85	0	4756	0	0
T86	0	3253	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	779749985	112554	0	0
T1	277735	6667	0	0
T2	9334	0	0	0
T3	566207	0	0	0
T4	3498	0	0	0
T5	6645	0	0	0
T6	989238	0	0	0
T7	14334	0	0	0
T8	978426	0	0	0
T9	367063	0	0	0
T10	677019	0	0	0
T18	0	6498	0	0
T39	0	3488	0	0
T54	0	7312	0	0
T79	0	30049	0	0
T82	0	8082	0	0
T83	0	6562	0	0
T84	0	1132	0	0
T85	0	5188	0	0
T86	0	3825	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	779749985	96750	0	0
T1	277735	5435	0	0
T2	9334	0	0	0
T3	566207	0	0	0
T4	3498	0	0	0
T5	6645	0	0	0
T6	989238	0	0	0
T7	14334	0	0	0
T8	978426	0	0	0
T9	367063	0	0	0
T10	677019	0	0	0
T18	0	5413	0	0
T39	0	2838	0	0
T54	0	6380	0	0
T79	0	25679	0	0
T82	0	6797	0	0
T83	0	5615	0	0
T84	0	857	0	0
T85	0	5185	0	0
T86	0	2997	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	779749985	110396	0	0
T1	277735	6610	0	0
T2	9334	0	0	0
T3	566207	0	0	0
T4	3498	0	0	0
T5	6645	0	0	0
T6	989238	0	0	0
T7	14334	0	0	0
T8	978426	0	0	0
T9	367063	0	0	0
T10	677019	0	0	0
T18	0	6322	0	0
T39	0	3574	0	0
T54	0	7158	0	0
T79	0	28669	0	0
T82	0	8072	0	0
T83	0	6453	0	0
T84	0	1092	0	0
T85	0	5340	0	0
T86	0	3736	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	779749985	97583	0	0
T1	277735	5884	0	0
T2	9334	0	0	0
T3	566207	0	0	0
T4	3498	0	0	0
T5	6645	0	0	0
T6	989238	0	0	0
T7	14334	0	0	0
T8	978426	0	0	0
T9	367063	0	0	0
T10	677019	0	0	0
T18	0	5727	0	0
T39	0	2951	0	0
T54	0	6288	0	0
T79	0	25864	0	0
T82	0	7091	0	0
T83	0	5664	0	0
T84	0	1022	0	0
T85	0	4972	0	0
T86	0	3072	0	0