Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 382246 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 4729180 1 T1 16 T2 16 T3 14



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 1255916 1 T1 1 T2 1 T3 1
values[0x0] 1806884 1 T1 14 T2 8 T3 10
values[0x1] 2048626 1 T1 7 T2 13 T3 7



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 169311 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 4942115 1 T1 17 T2 17 T3 14



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 20035 1 T7 282 T9 106 T11 1135
valid_sources[0x01] 20847 1 T7 300 T8 1 T9 185
valid_sources[0x02] 20022 1 T7 251 T9 111 T11 1357
valid_sources[0x03] 20661 1 T7 259 T9 148 T11 1277
valid_sources[0x04] 20188 1 T7 297 T9 99 T11 1241
valid_sources[0x05] 21192 1 T6 2 T7 281 T9 147
valid_sources[0x06] 20290 1 T7 220 T9 119 T11 1257
valid_sources[0x07] 20646 1 T5 1 T7 278 T9 152
valid_sources[0x08] 20883 1 T7 212 T9 236 T11 1194
valid_sources[0x09] 19761 1 T7 314 T8 1 T9 114
valid_sources[0x0a] 19228 1 T6 1 T7 255 T9 118
valid_sources[0x0b] 21177 1 T7 310 T9 79 T11 1196
valid_sources[0x0c] 21388 1 T7 220 T9 142 T11 1377
valid_sources[0x0d] 20186 1 T7 280 T9 188 T10 1
valid_sources[0x0e] 20209 1 T7 336 T9 98 T11 1386
valid_sources[0x0f] 18860 1 T1 1 T7 242 T9 112
valid_sources[0x10] 18916 1 T7 259 T9 108 T11 1249
valid_sources[0x11] 20050 1 T7 326 T9 179 T11 1320
valid_sources[0x12] 21092 1 T7 290 T9 110 T11 1222
valid_sources[0x13] 19799 1 T7 258 T9 154 T10 1
valid_sources[0x14] 19634 1 T7 229 T9 153 T11 1310
valid_sources[0x15] 19865 1 T5 1 T7 253 T8 1
valid_sources[0x16] 19895 1 T1 1 T7 290 T9 122
valid_sources[0x17] 20418 1 T1 1 T7 241 T9 105
valid_sources[0x18] 19292 1 T7 191 T9 162 T11 1188
valid_sources[0x19] 21211 1 T7 242 T9 109 T11 1198
valid_sources[0x1a] 19315 1 T7 229 T9 92 T11 1258
valid_sources[0x1b] 20322 1 T7 221 T9 152 T11 1214
valid_sources[0x1c] 19918 1 T7 260 T9 62 T10 1
valid_sources[0x1d] 20046 1 T5 1 T7 253 T9 172
valid_sources[0x1e] 19018 1 T7 275 T9 97 T11 1264
valid_sources[0x1f] 20405 1 T5 2 T7 250 T9 66
valid_sources[0x20] 20593 1 T5 1 T7 316 T9 146
valid_sources[0x21] 20457 1 T5 1 T7 258 T9 118
valid_sources[0x22] 19666 1 T7 302 T9 190 T11 1189
valid_sources[0x23] 20708 1 T6 2 T7 228 T9 208
valid_sources[0x24] 20333 1 T7 368 T9 135 T11 969
valid_sources[0x25] 18913 1 T5 1 T7 241 T9 142
valid_sources[0x26] 21140 1 T7 229 T9 131 T11 1327
valid_sources[0x27] 19374 1 T7 296 T9 87 T11 1157
valid_sources[0x28] 21044 1 T7 261 T9 126 T11 1395
valid_sources[0x29] 18875 1 T7 336 T9 118 T11 1250
valid_sources[0x2a] 19480 1 T7 265 T9 85 T11 1507
valid_sources[0x2b] 20509 1 T7 297 T9 85 T11 1296
valid_sources[0x2c] 19210 1 T1 1 T5 2 T7 283
valid_sources[0x2d] 20216 1 T1 2 T7 311 T9 136
valid_sources[0x2e] 20985 1 T7 289 T9 136 T11 1179
valid_sources[0x2f] 20137 1 T7 313 T9 91 T11 1257
valid_sources[0x30] 20247 1 T7 227 T8 1 T9 119
valid_sources[0x31] 19279 1 T1 1 T7 280 T9 112
valid_sources[0x32] 20535 1 T7 279 T9 147 T10 2
valid_sources[0x33] 19473 1 T7 276 T9 59 T11 1320
valid_sources[0x34] 19255 1 T7 296 T9 116 T11 1279
valid_sources[0x35] 20751 1 T7 321 T9 102 T11 1145
valid_sources[0x36] 21838 1 T7 296 T9 154 T11 1345
valid_sources[0x37] 19737 1 T7 269 T9 133 T11 1298
valid_sources[0x38] 19557 1 T7 282 T9 121 T11 1274
valid_sources[0x39] 19512 1 T6 2 T7 313 T9 133
valid_sources[0x3a] 19655 1 T7 214 T8 2 T9 136
valid_sources[0x3b] 20939 1 T7 273 T9 134 T11 1395
valid_sources[0x3c] 21209 1 T7 247 T9 143 T11 1323
valid_sources[0x3d] 19146 1 T6 2 T7 223 T9 109
valid_sources[0x3e] 20753 1 T7 345 T9 113 T11 1264
valid_sources[0x3f] 19478 1 T5 1 T7 258 T9 94
valid_sources[0x40] 19590 1 T7 222 T9 85 T11 1417
valid_sources[0x41] 19751 1 T7 246 T9 132 T11 1233
valid_sources[0x42] 20866 1 T7 238 T9 130 T11 1230
valid_sources[0x43] 20362 1 T7 260 T9 150 T11 1285
valid_sources[0x44] 18335 1 T5 1 T7 229 T9 102
valid_sources[0x45] 20292 1 T1 1 T7 263 T8 4
valid_sources[0x46] 20068 1 T7 325 T9 132 T11 1314
valid_sources[0x47] 18507 1 T7 216 T9 99 T11 1194
valid_sources[0x48] 20336 1 T7 297 T9 102 T11 1067
valid_sources[0x49] 19250 1 T7 208 T9 145 T11 1286
valid_sources[0x4a] 19106 1 T7 267 T9 113 T11 1190
valid_sources[0x4b] 17810 1 T7 322 T9 104 T11 1275
valid_sources[0x4c] 18832 1 T7 275 T9 110 T11 1227
valid_sources[0x4d] 20478 1 T7 298 T9 147 T11 1467
valid_sources[0x4e] 19120 1 T7 265 T9 131 T11 1117
valid_sources[0x4f] 20013 1 T7 276 T9 93 T11 1166
valid_sources[0x50] 19559 1 T7 289 T9 127 T11 1322
valid_sources[0x51] 18739 1 T7 268 T9 135 T11 1157
valid_sources[0x52] 19923 1 T7 258 T9 94 T11 1199
valid_sources[0x53] 19260 1 T7 265 T9 79 T11 1178
valid_sources[0x54] 21101 1 T7 274 T9 115 T11 1237
valid_sources[0x55] 19438 1 T7 244 T9 109 T11 1126
valid_sources[0x56] 20106 1 T7 284 T9 80 T11 1271
valid_sources[0x57] 19214 1 T7 269 T9 168 T11 1262
valid_sources[0x58] 19947 1 T7 353 T9 177 T11 1142
valid_sources[0x59] 19239 1 T7 324 T9 63 T11 1274
valid_sources[0x5a] 21409 1 T7 267 T9 147 T11 1238
valid_sources[0x5b] 19466 1 T7 262 T9 98 T11 1321
valid_sources[0x5c] 19534 1 T7 313 T9 113 T11 1348
valid_sources[0x5d] 19465 1 T7 264 T9 119 T11 1260
valid_sources[0x5e] 20542 1 T7 246 T9 93 T11 1357
valid_sources[0x5f] 20723 1 T7 279 T9 172 T11 1187
valid_sources[0x60] 19438 1 T7 322 T9 136 T11 1281
valid_sources[0x61] 19145 1 T7 261 T9 130 T11 1266
valid_sources[0x62] 22391 1 T5 1 T7 254 T9 116
valid_sources[0x63] 19759 1 T7 241 T9 98 T11 1334
valid_sources[0x64] 19084 1 T7 403 T9 139 T11 1372
valid_sources[0x65] 19885 1 T7 235 T9 83 T11 1351
valid_sources[0x66] 19155 1 T7 261 T9 100 T11 1187
valid_sources[0x67] 20121 1 T1 1 T7 256 T9 114
valid_sources[0x68] 19556 1 T7 179 T9 94 T11 1186
valid_sources[0x69] 19128 1 T7 297 T9 69 T10 1
valid_sources[0x6a] 20107 1 T7 283 T9 117 T11 1332
valid_sources[0x6b] 19567 1 T5 1 T7 304 T9 194
valid_sources[0x6c] 19533 1 T7 255 T9 131 T11 1262
valid_sources[0x6d] 18794 1 T7 283 T9 141 T11 1234
valid_sources[0x6e] 20838 1 T7 327 T9 131 T11 1249
valid_sources[0x6f] 19322 1 T5 1 T7 243 T9 109
valid_sources[0x70] 20097 1 T7 257 T9 204 T11 1086
valid_sources[0x71] 19029 1 T7 308 T9 64 T11 1138
valid_sources[0x72] 20528 1 T7 254 T9 114 T11 1240
valid_sources[0x73] 21237 1 T7 258 T9 120 T11 1366
valid_sources[0x74] 19934 1 T7 260 T9 123 T11 1205
valid_sources[0x75] 19874 1 T7 251 T9 75 T11 1208
valid_sources[0x76] 19464 1 T7 326 T9 152 T10 1
valid_sources[0x77] 19842 1 T7 346 T9 138 T11 1159
valid_sources[0x78] 19319 1 T7 286 T9 106 T11 1271
valid_sources[0x79] 20675 1 T7 294 T9 156 T10 1
valid_sources[0x7a] 21348 1 T7 275 T9 120 T11 1272
valid_sources[0x7b] 20348 1 T7 288 T9 176 T11 1270
valid_sources[0x7c] 18883 1 T7 270 T9 67 T11 1250
valid_sources[0x7d] 20644 1 T7 281 T9 108 T11 1237
valid_sources[0x7e] 19492 1 T7 238 T9 129 T11 1384
valid_sources[0x7f] 19945 1 T7 289 T9 138 T11 1058
valid_sources[0x80] 20085 1 T7 276 T9 95 T11 1101



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 1178915 1 T3 1 T4 26 T5 1
values[0x0] all_enables biggest_size 1775540 1 T1 12 T2 4 T3 7
values[0x1] all_enables biggest_size 1774725 1 T1 4 T2 12 T3 6

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%